1/* 2 * Copyright (c) 2007-2008 The Hewlett-Packard Development Company 3 * All rights reserved. 4 * 5 * Redistribution and use of this software in source and binary forms, 6 * with or without modification, are permitted provided that the 7 * following conditions are met: 8 * --- 172 unchanged lines hidden (view full) --- 181 EntryList::iterator entry = lookupIt(va, false); 182 if (entry != entryList.end()) { 183 freeList.push_back(*entry); 184 entryList.erase(entry); 185 } 186} 187 188Fault |
189TLB::translateInt(RequestPtr req, ThreadContext *tc) |
190{ |
191 DPRINTF(TLB, "Addresses references internal memory.\n"); |
192 Addr vaddr = req->getVaddr(); |
193 Addr prefix = (vaddr >> 3) & IntAddrPrefixMask; 194 if (prefix == IntAddrPrefixCPUID) { 195 panic("CPUID memory space not yet implemented!\n"); 196 } else if (prefix == IntAddrPrefixMSR) { 197 vaddr = vaddr >> 3; 198 req->setMmapedIpr(true); 199 Addr regNum = 0; 200 switch (vaddr & ~IntAddrPrefixMask) { 201 case 0x10: 202 regNum = MISCREG_TSC; 203 break; 204 case 0x1B: 205 regNum = MISCREG_APIC_BASE; 206 break; 207 case 0xFE: 208 regNum = MISCREG_MTRRCAP; 209 break; 210 case 0x174: 211 regNum = MISCREG_SYSENTER_CS; 212 break; 213 case 0x175: 214 regNum = MISCREG_SYSENTER_ESP; 215 break; 216 case 0x176: 217 regNum = MISCREG_SYSENTER_EIP; 218 break; 219 case 0x179: 220 regNum = MISCREG_MCG_CAP; 221 break; 222 case 0x17A: 223 regNum = MISCREG_MCG_STATUS; 224 break; 225 case 0x17B: 226 regNum = MISCREG_MCG_CTL; 227 break; 228 case 0x1D9: 229 regNum = MISCREG_DEBUG_CTL_MSR; 230 break; 231 case 0x1DB: 232 regNum = MISCREG_LAST_BRANCH_FROM_IP; 233 break; 234 case 0x1DC: 235 regNum = MISCREG_LAST_BRANCH_TO_IP; 236 break; 237 case 0x1DD: 238 regNum = MISCREG_LAST_EXCEPTION_FROM_IP; 239 break; 240 case 0x1DE: 241 regNum = MISCREG_LAST_EXCEPTION_TO_IP; 242 break; 243 case 0x200: 244 regNum = MISCREG_MTRR_PHYS_BASE_0; 245 break; 246 case 0x201: 247 regNum = MISCREG_MTRR_PHYS_MASK_0; 248 break; 249 case 0x202: 250 regNum = MISCREG_MTRR_PHYS_BASE_1; 251 break; 252 case 0x203: 253 regNum = MISCREG_MTRR_PHYS_MASK_1; 254 break; 255 case 0x204: 256 regNum = MISCREG_MTRR_PHYS_BASE_2; 257 break; 258 case 0x205: 259 regNum = MISCREG_MTRR_PHYS_MASK_2; 260 break; 261 case 0x206: 262 regNum = MISCREG_MTRR_PHYS_BASE_3; 263 break; 264 case 0x207: 265 regNum = MISCREG_MTRR_PHYS_MASK_3; 266 break; 267 case 0x208: 268 regNum = MISCREG_MTRR_PHYS_BASE_4; 269 break; 270 case 0x209: 271 regNum = MISCREG_MTRR_PHYS_MASK_4; 272 break; 273 case 0x20A: 274 regNum = MISCREG_MTRR_PHYS_BASE_5; 275 break; 276 case 0x20B: 277 regNum = MISCREG_MTRR_PHYS_MASK_5; 278 break; 279 case 0x20C: 280 regNum = MISCREG_MTRR_PHYS_BASE_6; 281 break; 282 case 0x20D: 283 regNum = MISCREG_MTRR_PHYS_MASK_6; 284 break; 285 case 0x20E: 286 regNum = MISCREG_MTRR_PHYS_BASE_7; 287 break; 288 case 0x20F: 289 regNum = MISCREG_MTRR_PHYS_MASK_7; 290 break; 291 case 0x250: 292 regNum = MISCREG_MTRR_FIX_64K_00000; 293 break; 294 case 0x258: 295 regNum = MISCREG_MTRR_FIX_16K_80000; 296 break; 297 case 0x259: 298 regNum = MISCREG_MTRR_FIX_16K_A0000; 299 break; 300 case 0x268: 301 regNum = MISCREG_MTRR_FIX_4K_C0000; 302 break; 303 case 0x269: 304 regNum = MISCREG_MTRR_FIX_4K_C8000; 305 break; 306 case 0x26A: 307 regNum = MISCREG_MTRR_FIX_4K_D0000; 308 break; 309 case 0x26B: 310 regNum = MISCREG_MTRR_FIX_4K_D8000; 311 break; 312 case 0x26C: 313 regNum = MISCREG_MTRR_FIX_4K_E0000; 314 break; 315 case 0x26D: 316 regNum = MISCREG_MTRR_FIX_4K_E8000; 317 break; 318 case 0x26E: 319 regNum = MISCREG_MTRR_FIX_4K_F0000; 320 break; 321 case 0x26F: 322 regNum = MISCREG_MTRR_FIX_4K_F8000; 323 break; 324 case 0x277: 325 regNum = MISCREG_PAT; 326 break; 327 case 0x2FF: 328 regNum = MISCREG_DEF_TYPE; 329 break; 330 case 0x400: 331 regNum = MISCREG_MC0_CTL; 332 break; 333 case 0x404: 334 regNum = MISCREG_MC1_CTL; 335 break; 336 case 0x408: 337 regNum = MISCREG_MC2_CTL; 338 break; 339 case 0x40C: 340 regNum = MISCREG_MC3_CTL; 341 break; 342 case 0x410: 343 regNum = MISCREG_MC4_CTL; 344 break; 345 case 0x414: 346 regNum = MISCREG_MC5_CTL; 347 break; 348 case 0x418: 349 regNum = MISCREG_MC6_CTL; 350 break; 351 case 0x41C: 352 regNum = MISCREG_MC7_CTL; 353 break; 354 case 0x401: 355 regNum = MISCREG_MC0_STATUS; 356 break; 357 case 0x405: 358 regNum = MISCREG_MC1_STATUS; 359 break; 360 case 0x409: 361 regNum = MISCREG_MC2_STATUS; 362 break; 363 case 0x40D: 364 regNum = MISCREG_MC3_STATUS; 365 break; 366 case 0x411: 367 regNum = MISCREG_MC4_STATUS; 368 break; 369 case 0x415: 370 regNum = MISCREG_MC5_STATUS; 371 break; 372 case 0x419: 373 regNum = MISCREG_MC6_STATUS; 374 break; 375 case 0x41D: 376 regNum = MISCREG_MC7_STATUS; 377 break; 378 case 0x402: 379 regNum = MISCREG_MC0_ADDR; 380 break; 381 case 0x406: 382 regNum = MISCREG_MC1_ADDR; 383 break; 384 case 0x40A: 385 regNum = MISCREG_MC2_ADDR; 386 break; 387 case 0x40E: 388 regNum = MISCREG_MC3_ADDR; 389 break; 390 case 0x412: 391 regNum = MISCREG_MC4_ADDR; 392 break; 393 case 0x416: 394 regNum = MISCREG_MC5_ADDR; 395 break; 396 case 0x41A: 397 regNum = MISCREG_MC6_ADDR; 398 break; 399 case 0x41E: 400 regNum = MISCREG_MC7_ADDR; 401 break; 402 case 0x403: 403 regNum = MISCREG_MC0_MISC; 404 break; 405 case 0x407: 406 regNum = MISCREG_MC1_MISC; 407 break; 408 case 0x40B: 409 regNum = MISCREG_MC2_MISC; 410 break; 411 case 0x40F: 412 regNum = MISCREG_MC3_MISC; 413 break; 414 case 0x413: 415 regNum = MISCREG_MC4_MISC; 416 break; 417 case 0x417: 418 regNum = MISCREG_MC5_MISC; 419 break; 420 case 0x41B: 421 regNum = MISCREG_MC6_MISC; 422 break; 423 case 0x41F: 424 regNum = MISCREG_MC7_MISC; 425 break; 426 case 0xC0000080: 427 regNum = MISCREG_EFER; 428 break; 429 case 0xC0000081: 430 regNum = MISCREG_STAR; 431 break; 432 case 0xC0000082: 433 regNum = MISCREG_LSTAR; 434 break; 435 case 0xC0000083: 436 regNum = MISCREG_CSTAR; 437 break; 438 case 0xC0000084: 439 regNum = MISCREG_SF_MASK; 440 break; 441 case 0xC0000100: 442 regNum = MISCREG_FS_BASE; 443 break; 444 case 0xC0000101: 445 regNum = MISCREG_GS_BASE; 446 break; 447 case 0xC0000102: 448 regNum = MISCREG_KERNEL_GS_BASE; 449 break; 450 case 0xC0000103: 451 regNum = MISCREG_TSC_AUX; 452 break; 453 case 0xC0010000: 454 regNum = MISCREG_PERF_EVT_SEL0; 455 break; 456 case 0xC0010001: 457 regNum = MISCREG_PERF_EVT_SEL1; 458 break; 459 case 0xC0010002: 460 regNum = MISCREG_PERF_EVT_SEL2; 461 break; 462 case 0xC0010003: 463 regNum = MISCREG_PERF_EVT_SEL3; 464 break; 465 case 0xC0010004: 466 regNum = MISCREG_PERF_EVT_CTR0; 467 break; 468 case 0xC0010005: 469 regNum = MISCREG_PERF_EVT_CTR1; 470 break; 471 case 0xC0010006: 472 regNum = MISCREG_PERF_EVT_CTR2; 473 break; 474 case 0xC0010007: 475 regNum = MISCREG_PERF_EVT_CTR3; 476 break; 477 case 0xC0010010: 478 regNum = MISCREG_SYSCFG; 479 break; 480 case 0xC0010016: 481 regNum = MISCREG_IORR_BASE0; 482 break; 483 case 0xC0010017: 484 regNum = MISCREG_IORR_BASE1; 485 break; 486 case 0xC0010018: 487 regNum = MISCREG_IORR_MASK0; 488 break; 489 case 0xC0010019: 490 regNum = MISCREG_IORR_MASK1; 491 break; 492 case 0xC001001A: 493 regNum = MISCREG_TOP_MEM; 494 break; 495 case 0xC001001D: 496 regNum = MISCREG_TOP_MEM2; 497 break; 498 case 0xC0010114: 499 regNum = MISCREG_VM_CR; 500 break; 501 case 0xC0010115: 502 regNum = MISCREG_IGNNE; 503 break; 504 case 0xC0010116: 505 regNum = MISCREG_SMM_CTL; 506 break; 507 case 0xC0010117: 508 regNum = MISCREG_VM_HSAVE_PA; 509 break; 510 default: 511 return new GeneralProtection(0); 512 } 513 //The index is multiplied by the size of a MiscReg so that 514 //any memory dependence calculations will not see these as 515 //overlapping. 516 req->setPaddr(regNum * sizeof(MiscReg)); 517 return NoFault; 518 } else if (prefix == IntAddrPrefixIO) { 519 // TODO If CPL > IOPL or in virtual mode, check the I/O permission 520 // bitmap in the TSS. |
521 |
522 Addr IOPort = vaddr & ~IntAddrPrefixMask; 523 // Make sure the address fits in the expected 16 bit IO address 524 // space. 525 assert(!(IOPort & ~0xFFFF)); 526 if (IOPort == 0xCF8 && req->getSize() == 4) { |
527 req->setMmapedIpr(true); |
528 req->setPaddr(MISCREG_PCI_CONFIG_ADDRESS * sizeof(MiscReg)); 529 } else if ((IOPort & ~mask(2)) == 0xCFC) { 530 Addr configAddress = 531 tc->readMiscRegNoEffect(MISCREG_PCI_CONFIG_ADDRESS); 532 if (bits(configAddress, 31, 31)) { 533 req->setPaddr(PhysAddrPrefixPciConfig | 534 mbits(configAddress, 30, 2) | 535 (IOPort & mask(2))); |
536 } |
537 } else { |
538 req->setPaddr(PhysAddrPrefixIO | IOPort); |
539 } |
540 return NoFault; 541 } else { 542 panic("Access to unrecognized internal address space %#x.\n", 543 prefix); |
544 } |
545} |
546 |
547Fault 548TLB::translate(RequestPtr req, ThreadContext *tc, Translation *translation, 549 Mode mode, bool &delayedResponse, bool timing) 550{ 551 uint32_t flags = req->getFlags(); 552 int seg = flags & SegmentFlagMask; 553 bool storeCheck = flags & (StoreCheck << FlagShift); |
554 |
555 // If this is true, we're dealing with a request to a non-memory address 556 // space. 557 if (seg == SEGMENT_REG_MS) { 558 return translateInt(req, tc); 559 } 560 561 delayedResponse = false; 562 Addr vaddr = req->getVaddr(); 563 DPRINTF(TLB, "Translating vaddr %#x.\n", vaddr); 564 565 HandyM5Reg m5Reg = tc->readMiscRegNoEffect(MISCREG_M5_REG); 566 |
567 // If protected mode has been enabled... |
568 if (m5Reg.prot) { |
569 DPRINTF(TLB, "In protected mode.\n"); |
570 // If we're not in 64-bit mode, do protection/limit checks |
571 if (m5Reg.mode != LongMode) { |
572 DPRINTF(TLB, "Not in long mode. Checking segment protection.\n"); 573 // Check for a NULL segment selector. 574 if (!(seg == SEGMENT_REG_TSG || seg == SYS_SEGMENT_REG_IDTR || |
575 seg == SEGMENT_REG_HS || seg == SEGMENT_REG_LS) |
576 && !tc->readMiscRegNoEffect(MISCREG_SEG_SEL(seg))) 577 return new GeneralProtection(0); 578 bool expandDown = false; 579 SegAttr attr = tc->readMiscRegNoEffect(MISCREG_SEG_ATTR(seg)); 580 if (seg >= SEGMENT_REG_ES && seg <= SEGMENT_REG_HS) { 581 if (!attr.writable && (mode == Write || storeCheck)) 582 return new GeneralProtection(0); 583 if (!attr.readable && mode == Read) 584 return new GeneralProtection(0); 585 expandDown = attr.expandDown; 586 587 } 588 Addr base = tc->readMiscRegNoEffect(MISCREG_SEG_BASE(seg)); 589 Addr limit = tc->readMiscRegNoEffect(MISCREG_SEG_LIMIT(seg)); 590 // This assumes we're not in 64 bit mode. If we were, the default 591 // address size is 64 bits, overridable to 32. 592 int size = 32; 593 bool sizeOverride = (flags & (AddrSizeFlagBit << FlagShift)); |
594 SegAttr csAttr = tc->readMiscRegNoEffect(MISCREG_CS_ATTR); |
595 if ((csAttr.defaultSize && sizeOverride) || 596 (!csAttr.defaultSize && !sizeOverride)) 597 size = 16; 598 Addr offset = bits(vaddr - base, size-1, 0); 599 Addr endOffset = offset + req->getSize() - 1; 600 if (expandDown) { 601 DPRINTF(TLB, "Checking an expand down segment.\n"); 602 warn_once("Expand down segments are untested.\n"); 603 if (offset <= limit || endOffset <= limit) 604 return new GeneralProtection(0); 605 } else { 606 if (offset > limit || endOffset > limit) 607 return new GeneralProtection(0); 608 } 609 } 610 // If paging is enabled, do the translation. |
611 if (m5Reg.paging) { |
612 DPRINTF(TLB, "Paging enabled.\n"); 613 // The vaddr already has the segment base applied. 614 TlbEntry *entry = lookup(vaddr); 615 if (!entry) { 616#if FULL_SYSTEM 617 Fault fault = walker->start(tc, translation, req, mode); 618 if (timing || fault != NoFault) { 619 // This gets ignored in atomic mode. --- 21 unchanged lines hidden (view full) --- 641 DPRINTF(TLB, "Mapping %#x to %#x\n", alignedVaddr, 642 newEntry.pageStart()); 643 entry = insert(alignedVaddr, newEntry); 644 } 645 DPRINTF(TLB, "Miss was serviced.\n"); 646#endif 647 } 648 // Do paging protection checks. |
649 bool inUser = (m5Reg.cpl == 3 && |
650 !(flags & (CPL0FlagBit << FlagShift))); 651 if ((inUser && !entry->user) || 652 (mode == Write && !entry->writable)) { 653 // The page must have been present to get into the TLB in 654 // the first place. We'll assume the reserved bits are 655 // fine even though we're not checking them. 656 return new PageFault(vaddr, true, mode, inUser, false); 657 } --- 101 unchanged lines hidden --- |