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< #include "mem/request.hh"
<
< #if !FULL_SYSTEM
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> #include "mem/request.hh"
> #include "sim/full_system.hh"
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< #endif
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< #include "sim/full_system.hh"
<
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< #if !FULL_SYSTEM
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< #endif
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< #if FULL_SYSTEM
< LocalApicBase localApicBase = tc->readMiscRegNoEffect(MISCREG_APIC_BASE);
< Addr baseAddr = localApicBase.base * PageBytes;
< Addr paddr = req->getPaddr();
< if (baseAddr <= paddr && baseAddr + PageBytes > paddr) {
< // The Intel developer's manuals say the below restrictions apply,
< // but the linux kernel, because of a compiler optimization, breaks
< // them.
< /*
< // Check alignment
< if (paddr & ((32/8) - 1))
< return new GeneralProtection(0);
< // Check access size
< if (req->getSize() != (32/8))
< return new GeneralProtection(0);
< */
< // Force the access to be uncacheable.
< req->setFlags(Request::UNCACHEABLE);
< req->setPaddr(x86LocalAPICAddress(tc->contextId(), paddr - baseAddr));
---
> if (FullSystem) {
> LocalApicBase localApicBase =
> tc->readMiscRegNoEffect(MISCREG_APIC_BASE);
> Addr baseAddr = localApicBase.base * PageBytes;
> Addr paddr = req->getPaddr();
> if (baseAddr <= paddr && baseAddr + PageBytes > paddr) {
> // The Intel developer's manuals say the below restrictions apply,
> // but the linux kernel, because of a compiler optimization, breaks
> // them.
> /*
> // Check alignment
> if (paddr & ((32/8) - 1))
> return new GeneralProtection(0);
> // Check access size
> if (req->getSize() != (32/8))
> return new GeneralProtection(0);
> */
> // Force the access to be uncacheable.
> req->setFlags(Request::UNCACHEABLE);
> req->setPaddr(x86LocalAPICAddress(tc->contextId(),
> paddr - baseAddr));
> }
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< #endif