1/*
2 * Copyright (c) 2007-2008 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 */
39
40#include <cstring>
41
| 1/*
2 * Copyright (c) 2007-2008 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 */
39
40#include <cstring>
41
|
42#include "arch/x86/insts/microldstop.hh"
43#include "arch/x86/regs/misc.hh"
44#include "arch/x86/regs/msr.hh"
45#include "arch/x86/faults.hh"
46#include "arch/x86/pagetable.hh"
47#include "arch/x86/pagetable_walker.hh"
48#include "arch/x86/tlb.hh"
49#include "arch/x86/x86_traits.hh"
50#include "base/bitfield.hh"
51#include "base/trace.hh"
52#include "cpu/base.hh"
53#include "cpu/thread_context.hh"
54#include "debug/TLB.hh"
55#include "mem/packet_access.hh"
56#include "mem/page_table.hh"
57#include "mem/request.hh"
58#include "sim/full_system.hh"
59#include "sim/process.hh"
60
61namespace X86ISA {
62
63TLB::TLB(const Params *p) : BaseTLB(p), configAddress(0), size(p->size),
64 lruSeq(0)
65{
66 if (!size)
67 fatal("TLBs must have a non-zero size.\n");
68 tlb = new TlbEntry[size];
69 std::memset(tlb, 0, sizeof(TlbEntry) * size);
70
71 for (int x = 0; x < size; x++) {
72 tlb[x].trieHandle = NULL;
73 freeList.push_back(&tlb[x]);
74 }
75
76 walker = p->walker;
77 walker->setTLB(this);
78}
79
80void
81TLB::evictLRU()
82{
83 // Find the entry with the lowest (and hence least recently updated)
84 // sequence number.
85
86 unsigned lru = 0;
87 for (unsigned i = 1; i < size; i++) {
88 if (tlb[i].lruSeq < tlb[lru].lruSeq)
89 lru = i;
90 }
91
92 assert(tlb[lru].trieHandle);
93 trie.remove(tlb[lru].trieHandle);
94 tlb[lru].trieHandle = NULL;
95 freeList.push_back(&tlb[lru]);
96}
97
98TlbEntry *
99TLB::insert(Addr vpn, TlbEntry &entry)
100{
101 // If somebody beat us to it, just use that existing entry.
102 TlbEntry *newEntry = trie.lookup(vpn);
103 if (newEntry) {
104 assert(newEntry->vaddr == vpn);
105 return newEntry;
106 }
107
108 if (freeList.empty())
109 evictLRU();
110
111 newEntry = freeList.front();
112 freeList.pop_front();
113
114 *newEntry = entry;
115 newEntry->lruSeq = nextSeq();
116 newEntry->vaddr = vpn;
117 newEntry->trieHandle =
118 trie.insert(vpn, TlbEntryTrie::MaxBits - entry.logBytes, newEntry);
119 return newEntry;
120}
121
122TlbEntry *
123TLB::lookup(Addr va, bool update_lru)
124{
125 TlbEntry *entry = trie.lookup(va);
126 if (entry && update_lru)
127 entry->lruSeq = nextSeq();
128 return entry;
129}
130
131void
132TLB::flushAll()
133{
134 DPRINTF(TLB, "Invalidating all entries.\n");
135 for (unsigned i = 0; i < size; i++) {
136 if (tlb[i].trieHandle) {
137 trie.remove(tlb[i].trieHandle);
138 tlb[i].trieHandle = NULL;
139 freeList.push_back(&tlb[i]);
140 }
141 }
142}
143
144void
145TLB::setConfigAddress(uint32_t addr)
146{
147 configAddress = addr;
148}
149
150void
151TLB::flushNonGlobal()
152{
153 DPRINTF(TLB, "Invalidating all non global entries.\n");
154 for (unsigned i = 0; i < size; i++) {
155 if (tlb[i].trieHandle && !tlb[i].global) {
156 trie.remove(tlb[i].trieHandle);
157 tlb[i].trieHandle = NULL;
158 freeList.push_back(&tlb[i]);
159 }
160 }
161}
162
163void
164TLB::demapPage(Addr va, uint64_t asn)
165{
166 TlbEntry *entry = trie.lookup(va);
167 if (entry) {
168 trie.remove(entry->trieHandle);
169 entry->trieHandle = NULL;
170 freeList.push_back(entry);
171 }
172}
173
174Fault
175TLB::translateInt(RequestPtr req, ThreadContext *tc)
176{
177 DPRINTF(TLB, "Addresses references internal memory.\n");
178 Addr vaddr = req->getVaddr();
179 Addr prefix = (vaddr >> 3) & IntAddrPrefixMask;
180 if (prefix == IntAddrPrefixCPUID) {
181 panic("CPUID memory space not yet implemented!\n");
182 } else if (prefix == IntAddrPrefixMSR) {
183 vaddr = (vaddr >> 3) & ~IntAddrPrefixMask;
184 req->setFlags(Request::MMAPPED_IPR);
185
186 MiscRegIndex regNum;
187 if (!msrAddrToIndex(regNum, vaddr))
188 return new GeneralProtection(0);
189
190 //The index is multiplied by the size of a MiscReg so that
191 //any memory dependence calculations will not see these as
192 //overlapping.
193 req->setPaddr((Addr)regNum * sizeof(MiscReg));
194 return NoFault;
195 } else if (prefix == IntAddrPrefixIO) {
196 // TODO If CPL > IOPL or in virtual mode, check the I/O permission
197 // bitmap in the TSS.
198
199 Addr IOPort = vaddr & ~IntAddrPrefixMask;
200 // Make sure the address fits in the expected 16 bit IO address
201 // space.
202 assert(!(IOPort & ~0xFFFF));
203 if (IOPort == 0xCF8 && req->getSize() == 4) {
204 req->setFlags(Request::MMAPPED_IPR);
205 req->setPaddr(MISCREG_PCI_CONFIG_ADDRESS * sizeof(MiscReg));
206 } else if ((IOPort & ~mask(2)) == 0xCFC) {
207 req->setFlags(Request::UNCACHEABLE);
208 Addr configAddress =
209 tc->readMiscRegNoEffect(MISCREG_PCI_CONFIG_ADDRESS);
210 if (bits(configAddress, 31, 31)) {
211 req->setPaddr(PhysAddrPrefixPciConfig |
212 mbits(configAddress, 30, 2) |
213 (IOPort & mask(2)));
214 } else {
215 req->setPaddr(PhysAddrPrefixIO | IOPort);
216 }
217 } else {
218 req->setFlags(Request::UNCACHEABLE);
219 req->setPaddr(PhysAddrPrefixIO | IOPort);
220 }
221 return NoFault;
222 } else {
223 panic("Access to unrecognized internal address space %#x.\n",
224 prefix);
225 }
226}
227
228Fault
229TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const
230{
231 Addr paddr = req->getPaddr();
232
233 // Check for an access to the local APIC
234 if (FullSystem) {
235 LocalApicBase localApicBase =
236 tc->readMiscRegNoEffect(MISCREG_APIC_BASE);
237 AddrRange apicRange(localApicBase.base * PageBytes,
238 (localApicBase.base + 1) * PageBytes - 1);
239
| 43#include "arch/x86/insts/microldstop.hh"
44#include "arch/x86/regs/misc.hh"
45#include "arch/x86/regs/msr.hh"
46#include "arch/x86/faults.hh"
47#include "arch/x86/pagetable.hh"
48#include "arch/x86/pagetable_walker.hh"
49#include "arch/x86/tlb.hh"
50#include "arch/x86/x86_traits.hh"
51#include "base/bitfield.hh"
52#include "base/trace.hh"
53#include "cpu/base.hh"
54#include "cpu/thread_context.hh"
55#include "debug/TLB.hh"
56#include "mem/packet_access.hh"
57#include "mem/page_table.hh"
58#include "mem/request.hh"
59#include "sim/full_system.hh"
60#include "sim/process.hh"
61
62namespace X86ISA {
63
64TLB::TLB(const Params *p) : BaseTLB(p), configAddress(0), size(p->size),
65 lruSeq(0)
66{
67 if (!size)
68 fatal("TLBs must have a non-zero size.\n");
69 tlb = new TlbEntry[size];
70 std::memset(tlb, 0, sizeof(TlbEntry) * size);
71
72 for (int x = 0; x < size; x++) {
73 tlb[x].trieHandle = NULL;
74 freeList.push_back(&tlb[x]);
75 }
76
77 walker = p->walker;
78 walker->setTLB(this);
79}
80
81void
82TLB::evictLRU()
83{
84 // Find the entry with the lowest (and hence least recently updated)
85 // sequence number.
86
87 unsigned lru = 0;
88 for (unsigned i = 1; i < size; i++) {
89 if (tlb[i].lruSeq < tlb[lru].lruSeq)
90 lru = i;
91 }
92
93 assert(tlb[lru].trieHandle);
94 trie.remove(tlb[lru].trieHandle);
95 tlb[lru].trieHandle = NULL;
96 freeList.push_back(&tlb[lru]);
97}
98
99TlbEntry *
100TLB::insert(Addr vpn, TlbEntry &entry)
101{
102 // If somebody beat us to it, just use that existing entry.
103 TlbEntry *newEntry = trie.lookup(vpn);
104 if (newEntry) {
105 assert(newEntry->vaddr == vpn);
106 return newEntry;
107 }
108
109 if (freeList.empty())
110 evictLRU();
111
112 newEntry = freeList.front();
113 freeList.pop_front();
114
115 *newEntry = entry;
116 newEntry->lruSeq = nextSeq();
117 newEntry->vaddr = vpn;
118 newEntry->trieHandle =
119 trie.insert(vpn, TlbEntryTrie::MaxBits - entry.logBytes, newEntry);
120 return newEntry;
121}
122
123TlbEntry *
124TLB::lookup(Addr va, bool update_lru)
125{
126 TlbEntry *entry = trie.lookup(va);
127 if (entry && update_lru)
128 entry->lruSeq = nextSeq();
129 return entry;
130}
131
132void
133TLB::flushAll()
134{
135 DPRINTF(TLB, "Invalidating all entries.\n");
136 for (unsigned i = 0; i < size; i++) {
137 if (tlb[i].trieHandle) {
138 trie.remove(tlb[i].trieHandle);
139 tlb[i].trieHandle = NULL;
140 freeList.push_back(&tlb[i]);
141 }
142 }
143}
144
145void
146TLB::setConfigAddress(uint32_t addr)
147{
148 configAddress = addr;
149}
150
151void
152TLB::flushNonGlobal()
153{
154 DPRINTF(TLB, "Invalidating all non global entries.\n");
155 for (unsigned i = 0; i < size; i++) {
156 if (tlb[i].trieHandle && !tlb[i].global) {
157 trie.remove(tlb[i].trieHandle);
158 tlb[i].trieHandle = NULL;
159 freeList.push_back(&tlb[i]);
160 }
161 }
162}
163
164void
165TLB::demapPage(Addr va, uint64_t asn)
166{
167 TlbEntry *entry = trie.lookup(va);
168 if (entry) {
169 trie.remove(entry->trieHandle);
170 entry->trieHandle = NULL;
171 freeList.push_back(entry);
172 }
173}
174
175Fault
176TLB::translateInt(RequestPtr req, ThreadContext *tc)
177{
178 DPRINTF(TLB, "Addresses references internal memory.\n");
179 Addr vaddr = req->getVaddr();
180 Addr prefix = (vaddr >> 3) & IntAddrPrefixMask;
181 if (prefix == IntAddrPrefixCPUID) {
182 panic("CPUID memory space not yet implemented!\n");
183 } else if (prefix == IntAddrPrefixMSR) {
184 vaddr = (vaddr >> 3) & ~IntAddrPrefixMask;
185 req->setFlags(Request::MMAPPED_IPR);
186
187 MiscRegIndex regNum;
188 if (!msrAddrToIndex(regNum, vaddr))
189 return new GeneralProtection(0);
190
191 //The index is multiplied by the size of a MiscReg so that
192 //any memory dependence calculations will not see these as
193 //overlapping.
194 req->setPaddr((Addr)regNum * sizeof(MiscReg));
195 return NoFault;
196 } else if (prefix == IntAddrPrefixIO) {
197 // TODO If CPL > IOPL or in virtual mode, check the I/O permission
198 // bitmap in the TSS.
199
200 Addr IOPort = vaddr & ~IntAddrPrefixMask;
201 // Make sure the address fits in the expected 16 bit IO address
202 // space.
203 assert(!(IOPort & ~0xFFFF));
204 if (IOPort == 0xCF8 && req->getSize() == 4) {
205 req->setFlags(Request::MMAPPED_IPR);
206 req->setPaddr(MISCREG_PCI_CONFIG_ADDRESS * sizeof(MiscReg));
207 } else if ((IOPort & ~mask(2)) == 0xCFC) {
208 req->setFlags(Request::UNCACHEABLE);
209 Addr configAddress =
210 tc->readMiscRegNoEffect(MISCREG_PCI_CONFIG_ADDRESS);
211 if (bits(configAddress, 31, 31)) {
212 req->setPaddr(PhysAddrPrefixPciConfig |
213 mbits(configAddress, 30, 2) |
214 (IOPort & mask(2)));
215 } else {
216 req->setPaddr(PhysAddrPrefixIO | IOPort);
217 }
218 } else {
219 req->setFlags(Request::UNCACHEABLE);
220 req->setPaddr(PhysAddrPrefixIO | IOPort);
221 }
222 return NoFault;
223 } else {
224 panic("Access to unrecognized internal address space %#x.\n",
225 prefix);
226 }
227}
228
229Fault
230TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const
231{
232 Addr paddr = req->getPaddr();
233
234 // Check for an access to the local APIC
235 if (FullSystem) {
236 LocalApicBase localApicBase =
237 tc->readMiscRegNoEffect(MISCREG_APIC_BASE);
238 AddrRange apicRange(localApicBase.base * PageBytes,
239 (localApicBase.base + 1) * PageBytes - 1);
240
|
256 }
257 }
258
259 return NoFault;
260}
261
262Fault
263TLB::translate(RequestPtr req, ThreadContext *tc, Translation *translation,
264 Mode mode, bool &delayedResponse, bool timing)
265{
266 uint32_t flags = req->getFlags();
267 int seg = flags & SegmentFlagMask;
268 bool storeCheck = flags & (StoreCheck << FlagShift);
269
270 delayedResponse = false;
271
272 // If this is true, we're dealing with a request to a non-memory address
273 // space.
274 if (seg == SEGMENT_REG_MS) {
275 return translateInt(req, tc);
276 }
277
278 Addr vaddr = req->getVaddr();
279 DPRINTF(TLB, "Translating vaddr %#x.\n", vaddr);
280
281 HandyM5Reg m5Reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
282
283 // If protected mode has been enabled...
284 if (m5Reg.prot) {
285 DPRINTF(TLB, "In protected mode.\n");
286 // If we're not in 64-bit mode, do protection/limit checks
287 if (m5Reg.mode != LongMode) {
288 DPRINTF(TLB, "Not in long mode. Checking segment protection.\n");
289 // Check for a NULL segment selector.
290 if (!(seg == SEGMENT_REG_TSG || seg == SYS_SEGMENT_REG_IDTR ||
291 seg == SEGMENT_REG_HS || seg == SEGMENT_REG_LS)
292 && !tc->readMiscRegNoEffect(MISCREG_SEG_SEL(seg)))
293 return new GeneralProtection(0);
294 bool expandDown = false;
295 SegAttr attr = tc->readMiscRegNoEffect(MISCREG_SEG_ATTR(seg));
296 if (seg >= SEGMENT_REG_ES && seg <= SEGMENT_REG_HS) {
297 if (!attr.writable && (mode == Write || storeCheck))
298 return new GeneralProtection(0);
299 if (!attr.readable && mode == Read)
300 return new GeneralProtection(0);
301 expandDown = attr.expandDown;
302
303 }
304 Addr base = tc->readMiscRegNoEffect(MISCREG_SEG_BASE(seg));
305 Addr limit = tc->readMiscRegNoEffect(MISCREG_SEG_LIMIT(seg));
306 bool sizeOverride = (flags & (AddrSizeFlagBit << FlagShift));
307 unsigned logSize = sizeOverride ? (unsigned)m5Reg.altAddr
308 : (unsigned)m5Reg.defAddr;
309 int size = (1 << logSize) * 8;
310 Addr offset = bits(vaddr - base, size - 1, 0);
311 Addr endOffset = offset + req->getSize() - 1;
312 if (expandDown) {
313 DPRINTF(TLB, "Checking an expand down segment.\n");
314 warn_once("Expand down segments are untested.\n");
315 if (offset <= limit || endOffset <= limit)
316 return new GeneralProtection(0);
317 } else {
318 if (offset > limit || endOffset > limit)
319 return new GeneralProtection(0);
320 }
321 }
322 if (m5Reg.submode != SixtyFourBitMode ||
323 (flags & (AddrSizeFlagBit << FlagShift)))
324 vaddr &= mask(32);
325 // If paging is enabled, do the translation.
326 if (m5Reg.paging) {
327 DPRINTF(TLB, "Paging enabled.\n");
328 // The vaddr already has the segment base applied.
329 TlbEntry *entry = lookup(vaddr);
330 if (!entry) {
331 if (FullSystem) {
332 Fault fault = walker->start(tc, translation, req, mode);
333 if (timing || fault != NoFault) {
334 // This gets ignored in atomic mode.
335 delayedResponse = true;
336 return fault;
337 }
338 entry = lookup(vaddr);
339 assert(entry);
340 } else {
341 DPRINTF(TLB, "Handling a TLB miss for "
342 "address %#x at pc %#x.\n",
343 vaddr, tc->instAddr());
344
345 Process *p = tc->getProcessPtr();
346 TlbEntry newEntry;
347 bool success = p->pTable->lookup(vaddr, newEntry);
348 if (!success && mode != Execute) {
349 // Check if we just need to grow the stack.
350 if (p->fixupStackFault(vaddr)) {
351 // If we did, lookup the entry for the new page.
352 success = p->pTable->lookup(vaddr, newEntry);
353 }
354 }
355 if (!success) {
356 return new PageFault(vaddr, true, mode, true, false);
357 } else {
358 Addr alignedVaddr = p->pTable->pageAlign(vaddr);
359 DPRINTF(TLB, "Mapping %#x to %#x\n", alignedVaddr,
360 newEntry.pageStart());
361 entry = insert(alignedVaddr, newEntry);
362 }
363 DPRINTF(TLB, "Miss was serviced.\n");
364 }
365 }
366
367 DPRINTF(TLB, "Entry found with paddr %#x, "
368 "doing protection checks.\n", entry->paddr);
369 // Do paging protection checks.
370 bool inUser = (m5Reg.cpl == 3 &&
371 !(flags & (CPL0FlagBit << FlagShift)));
372 CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0);
373 bool badWrite = (!entry->writable && (inUser || cr0.wp));
374 if ((inUser && !entry->user) || (mode == Write && badWrite)) {
375 // The page must have been present to get into the TLB in
376 // the first place. We'll assume the reserved bits are
377 // fine even though we're not checking them.
378 return new PageFault(vaddr, true, mode, inUser, false);
379 }
380 if (storeCheck && badWrite) {
381 // This would fault if this were a write, so return a page
382 // fault that reflects that happening.
383 return new PageFault(vaddr, true, Write, inUser, false);
384 }
385
386 Addr paddr = entry->paddr | (vaddr & mask(entry->logBytes));
387 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, paddr);
388 req->setPaddr(paddr);
389 if (entry->uncacheable)
390 req->setFlags(Request::UNCACHEABLE);
391 } else {
392 //Use the address which already has segmentation applied.
393 DPRINTF(TLB, "Paging disabled.\n");
394 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr);
395 req->setPaddr(vaddr);
396 }
397 } else {
398 // Real mode
399 DPRINTF(TLB, "In real mode.\n");
400 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr);
401 req->setPaddr(vaddr);
402 }
403
404 return finalizePhysical(req, tc, mode);
405}
406
407Fault
408TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
409{
410 bool delayedResponse;
411 return TLB::translate(req, tc, NULL, mode, delayedResponse, false);
412}
413
414void
415TLB::translateTiming(RequestPtr req, ThreadContext *tc,
416 Translation *translation, Mode mode)
417{
418 bool delayedResponse;
419 assert(translation);
420 Fault fault =
421 TLB::translate(req, tc, translation, mode, delayedResponse, true);
422 if (!delayedResponse)
423 translation->finish(fault, req, tc, mode);
424}
425
426Fault
427TLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode)
428{
429 panic("Not implemented\n");
430 return NoFault;
431}
432
433Walker *
434TLB::getWalker()
435{
436 return walker;
437}
438
439void
440TLB::serialize(std::ostream &os)
441{
442 // Only store the entries in use.
443 uint32_t _size = size - freeList.size();
444 SERIALIZE_SCALAR(_size);
445 SERIALIZE_SCALAR(lruSeq);
446
447 uint32_t _count = 0;
448
449 for (uint32_t x = 0; x < size; x++) {
450 if (tlb[x].trieHandle != NULL) {
451 os << "\n[" << csprintf("%s.Entry%d", name(), _count) << "]\n";
452 tlb[x].serialize(os);
453 _count++;
454 }
455 }
456}
457
458void
459TLB::unserialize(Checkpoint *cp, const std::string §ion)
460{
461 // Do not allow to restore with a smaller tlb.
462 uint32_t _size;
463 UNSERIALIZE_SCALAR(_size);
464 if (_size > size) {
465 fatal("TLB size less than the one in checkpoint!");
466 }
467
468 UNSERIALIZE_SCALAR(lruSeq);
469
470 for (uint32_t x = 0; x < _size; x++) {
471 TlbEntry *newEntry = freeList.front();
472 freeList.pop_front();
473
474 newEntry->unserialize(cp, csprintf("%s.Entry%d", name(), x));
475 newEntry->trieHandle = trie.insert(newEntry->vaddr,
476 TlbEntryTrie::MaxBits - newEntry->logBytes, newEntry);
477 }
478}
479
480BaseMasterPort *
481TLB::getMasterPort()
482{
483 return &walker->getMasterPort("port");
484}
485
486} // namespace X86ISA
487
488X86ISA::TLB *
489X86TLBParams::create()
490{
491 return new X86ISA::TLB(this);
492}
| 264 }
265 }
266
267 return NoFault;
268}
269
270Fault
271TLB::translate(RequestPtr req, ThreadContext *tc, Translation *translation,
272 Mode mode, bool &delayedResponse, bool timing)
273{
274 uint32_t flags = req->getFlags();
275 int seg = flags & SegmentFlagMask;
276 bool storeCheck = flags & (StoreCheck << FlagShift);
277
278 delayedResponse = false;
279
280 // If this is true, we're dealing with a request to a non-memory address
281 // space.
282 if (seg == SEGMENT_REG_MS) {
283 return translateInt(req, tc);
284 }
285
286 Addr vaddr = req->getVaddr();
287 DPRINTF(TLB, "Translating vaddr %#x.\n", vaddr);
288
289 HandyM5Reg m5Reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
290
291 // If protected mode has been enabled...
292 if (m5Reg.prot) {
293 DPRINTF(TLB, "In protected mode.\n");
294 // If we're not in 64-bit mode, do protection/limit checks
295 if (m5Reg.mode != LongMode) {
296 DPRINTF(TLB, "Not in long mode. Checking segment protection.\n");
297 // Check for a NULL segment selector.
298 if (!(seg == SEGMENT_REG_TSG || seg == SYS_SEGMENT_REG_IDTR ||
299 seg == SEGMENT_REG_HS || seg == SEGMENT_REG_LS)
300 && !tc->readMiscRegNoEffect(MISCREG_SEG_SEL(seg)))
301 return new GeneralProtection(0);
302 bool expandDown = false;
303 SegAttr attr = tc->readMiscRegNoEffect(MISCREG_SEG_ATTR(seg));
304 if (seg >= SEGMENT_REG_ES && seg <= SEGMENT_REG_HS) {
305 if (!attr.writable && (mode == Write || storeCheck))
306 return new GeneralProtection(0);
307 if (!attr.readable && mode == Read)
308 return new GeneralProtection(0);
309 expandDown = attr.expandDown;
310
311 }
312 Addr base = tc->readMiscRegNoEffect(MISCREG_SEG_BASE(seg));
313 Addr limit = tc->readMiscRegNoEffect(MISCREG_SEG_LIMIT(seg));
314 bool sizeOverride = (flags & (AddrSizeFlagBit << FlagShift));
315 unsigned logSize = sizeOverride ? (unsigned)m5Reg.altAddr
316 : (unsigned)m5Reg.defAddr;
317 int size = (1 << logSize) * 8;
318 Addr offset = bits(vaddr - base, size - 1, 0);
319 Addr endOffset = offset + req->getSize() - 1;
320 if (expandDown) {
321 DPRINTF(TLB, "Checking an expand down segment.\n");
322 warn_once("Expand down segments are untested.\n");
323 if (offset <= limit || endOffset <= limit)
324 return new GeneralProtection(0);
325 } else {
326 if (offset > limit || endOffset > limit)
327 return new GeneralProtection(0);
328 }
329 }
330 if (m5Reg.submode != SixtyFourBitMode ||
331 (flags & (AddrSizeFlagBit << FlagShift)))
332 vaddr &= mask(32);
333 // If paging is enabled, do the translation.
334 if (m5Reg.paging) {
335 DPRINTF(TLB, "Paging enabled.\n");
336 // The vaddr already has the segment base applied.
337 TlbEntry *entry = lookup(vaddr);
338 if (!entry) {
339 if (FullSystem) {
340 Fault fault = walker->start(tc, translation, req, mode);
341 if (timing || fault != NoFault) {
342 // This gets ignored in atomic mode.
343 delayedResponse = true;
344 return fault;
345 }
346 entry = lookup(vaddr);
347 assert(entry);
348 } else {
349 DPRINTF(TLB, "Handling a TLB miss for "
350 "address %#x at pc %#x.\n",
351 vaddr, tc->instAddr());
352
353 Process *p = tc->getProcessPtr();
354 TlbEntry newEntry;
355 bool success = p->pTable->lookup(vaddr, newEntry);
356 if (!success && mode != Execute) {
357 // Check if we just need to grow the stack.
358 if (p->fixupStackFault(vaddr)) {
359 // If we did, lookup the entry for the new page.
360 success = p->pTable->lookup(vaddr, newEntry);
361 }
362 }
363 if (!success) {
364 return new PageFault(vaddr, true, mode, true, false);
365 } else {
366 Addr alignedVaddr = p->pTable->pageAlign(vaddr);
367 DPRINTF(TLB, "Mapping %#x to %#x\n", alignedVaddr,
368 newEntry.pageStart());
369 entry = insert(alignedVaddr, newEntry);
370 }
371 DPRINTF(TLB, "Miss was serviced.\n");
372 }
373 }
374
375 DPRINTF(TLB, "Entry found with paddr %#x, "
376 "doing protection checks.\n", entry->paddr);
377 // Do paging protection checks.
378 bool inUser = (m5Reg.cpl == 3 &&
379 !(flags & (CPL0FlagBit << FlagShift)));
380 CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0);
381 bool badWrite = (!entry->writable && (inUser || cr0.wp));
382 if ((inUser && !entry->user) || (mode == Write && badWrite)) {
383 // The page must have been present to get into the TLB in
384 // the first place. We'll assume the reserved bits are
385 // fine even though we're not checking them.
386 return new PageFault(vaddr, true, mode, inUser, false);
387 }
388 if (storeCheck && badWrite) {
389 // This would fault if this were a write, so return a page
390 // fault that reflects that happening.
391 return new PageFault(vaddr, true, Write, inUser, false);
392 }
393
394 Addr paddr = entry->paddr | (vaddr & mask(entry->logBytes));
395 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, paddr);
396 req->setPaddr(paddr);
397 if (entry->uncacheable)
398 req->setFlags(Request::UNCACHEABLE);
399 } else {
400 //Use the address which already has segmentation applied.
401 DPRINTF(TLB, "Paging disabled.\n");
402 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr);
403 req->setPaddr(vaddr);
404 }
405 } else {
406 // Real mode
407 DPRINTF(TLB, "In real mode.\n");
408 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr);
409 req->setPaddr(vaddr);
410 }
411
412 return finalizePhysical(req, tc, mode);
413}
414
415Fault
416TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
417{
418 bool delayedResponse;
419 return TLB::translate(req, tc, NULL, mode, delayedResponse, false);
420}
421
422void
423TLB::translateTiming(RequestPtr req, ThreadContext *tc,
424 Translation *translation, Mode mode)
425{
426 bool delayedResponse;
427 assert(translation);
428 Fault fault =
429 TLB::translate(req, tc, translation, mode, delayedResponse, true);
430 if (!delayedResponse)
431 translation->finish(fault, req, tc, mode);
432}
433
434Fault
435TLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode)
436{
437 panic("Not implemented\n");
438 return NoFault;
439}
440
441Walker *
442TLB::getWalker()
443{
444 return walker;
445}
446
447void
448TLB::serialize(std::ostream &os)
449{
450 // Only store the entries in use.
451 uint32_t _size = size - freeList.size();
452 SERIALIZE_SCALAR(_size);
453 SERIALIZE_SCALAR(lruSeq);
454
455 uint32_t _count = 0;
456
457 for (uint32_t x = 0; x < size; x++) {
458 if (tlb[x].trieHandle != NULL) {
459 os << "\n[" << csprintf("%s.Entry%d", name(), _count) << "]\n";
460 tlb[x].serialize(os);
461 _count++;
462 }
463 }
464}
465
466void
467TLB::unserialize(Checkpoint *cp, const std::string §ion)
468{
469 // Do not allow to restore with a smaller tlb.
470 uint32_t _size;
471 UNSERIALIZE_SCALAR(_size);
472 if (_size > size) {
473 fatal("TLB size less than the one in checkpoint!");
474 }
475
476 UNSERIALIZE_SCALAR(lruSeq);
477
478 for (uint32_t x = 0; x < _size; x++) {
479 TlbEntry *newEntry = freeList.front();
480 freeList.pop_front();
481
482 newEntry->unserialize(cp, csprintf("%s.Entry%d", name(), x));
483 newEntry->trieHandle = trie.insert(newEntry->vaddr,
484 TlbEntryTrie::MaxBits - newEntry->logBytes, newEntry);
485 }
486}
487
488BaseMasterPort *
489TLB::getMasterPort()
490{
491 return &walker->getMasterPort("port");
492}
493
494} // namespace X86ISA
495
496X86ISA::TLB *
497X86TLBParams::create()
498{
499 return new X86ISA::TLB(this);
500}
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