tlb.cc (8767:e575781f71b8) tlb.cc (8768:314eb1e2fa94)
1/*
2 * Copyright (c) 2007-2008 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 */
39
40#include <cstring>
41
42#include "arch/x86/insts/microldstop.hh"
43#include "arch/x86/regs/misc.hh"
44#include "arch/x86/regs/msr.hh"
45#include "arch/x86/faults.hh"
46#include "arch/x86/pagetable.hh"
47#include "arch/x86/pagetable_walker.hh"
48#include "arch/x86/tlb.hh"
49#include "arch/x86/x86_traits.hh"
50#include "base/bitfield.hh"
51#include "base/trace.hh"
1/*
2 * Copyright (c) 2007-2008 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 */
39
40#include <cstring>
41
42#include "arch/x86/insts/microldstop.hh"
43#include "arch/x86/regs/misc.hh"
44#include "arch/x86/regs/msr.hh"
45#include "arch/x86/faults.hh"
46#include "arch/x86/pagetable.hh"
47#include "arch/x86/pagetable_walker.hh"
48#include "arch/x86/tlb.hh"
49#include "arch/x86/x86_traits.hh"
50#include "base/bitfield.hh"
51#include "base/trace.hh"
52#include "config/full_system.hh"
53#include "cpu/base.hh"
54#include "cpu/thread_context.hh"
55#include "debug/TLB.hh"
56#include "mem/packet_access.hh"
57#include "mem/page_table.hh"
58#include "mem/request.hh"
59#include "sim/full_system.hh"
60#include "sim/process.hh"
61
62namespace X86ISA {
63
64TLB::TLB(const Params *p) : BaseTLB(p), configAddress(0), size(p->size)
65{
66 tlb = new TlbEntry[size];
67 std::memset(tlb, 0, sizeof(TlbEntry) * size);
68
69 for (int x = 0; x < size; x++)
70 freeList.push_back(&tlb[x]);
71
72 walker = p->walker;
73 walker->setTLB(this);
74}
75
76TlbEntry *
77TLB::insert(Addr vpn, TlbEntry &entry)
78{
79 //TODO Deal with conflicting entries
80
81 TlbEntry *newEntry = NULL;
82 if (!freeList.empty()) {
83 newEntry = freeList.front();
84 freeList.pop_front();
85 } else {
86 newEntry = entryList.back();
87 entryList.pop_back();
88 }
89 *newEntry = entry;
90 newEntry->vaddr = vpn;
91 entryList.push_front(newEntry);
92 return newEntry;
93}
94
95TLB::EntryList::iterator
96TLB::lookupIt(Addr va, bool update_lru)
97{
98 //TODO make this smarter at some point
99 EntryList::iterator entry;
100 for (entry = entryList.begin(); entry != entryList.end(); entry++) {
101 if ((*entry)->vaddr <= va && (*entry)->vaddr + (*entry)->size > va) {
102 DPRINTF(TLB, "Matched vaddr %#x to entry starting at %#x "
103 "with size %#x.\n", va, (*entry)->vaddr, (*entry)->size);
104 if (update_lru) {
105 entryList.push_front(*entry);
106 entryList.erase(entry);
107 entry = entryList.begin();
108 }
109 break;
110 }
111 }
112 return entry;
113}
114
115TlbEntry *
116TLB::lookup(Addr va, bool update_lru)
117{
118 EntryList::iterator entry = lookupIt(va, update_lru);
119 if (entry == entryList.end())
120 return NULL;
121 else
122 return *entry;
123}
124
125void
126TLB::invalidateAll()
127{
128 DPRINTF(TLB, "Invalidating all entries.\n");
129 while (!entryList.empty()) {
130 TlbEntry *entry = entryList.front();
131 entryList.pop_front();
132 freeList.push_back(entry);
133 }
134}
135
136void
137TLB::setConfigAddress(uint32_t addr)
138{
139 configAddress = addr;
140}
141
142void
143TLB::invalidateNonGlobal()
144{
145 DPRINTF(TLB, "Invalidating all non global entries.\n");
146 EntryList::iterator entryIt;
147 for (entryIt = entryList.begin(); entryIt != entryList.end();) {
148 if (!(*entryIt)->global) {
149 freeList.push_back(*entryIt);
150 entryList.erase(entryIt++);
151 } else {
152 entryIt++;
153 }
154 }
155}
156
157void
158TLB::demapPage(Addr va, uint64_t asn)
159{
160 EntryList::iterator entry = lookupIt(va, false);
161 if (entry != entryList.end()) {
162 freeList.push_back(*entry);
163 entryList.erase(entry);
164 }
165}
166
167Fault
168TLB::translateInt(RequestPtr req, ThreadContext *tc)
169{
170 DPRINTF(TLB, "Addresses references internal memory.\n");
171 Addr vaddr = req->getVaddr();
172 Addr prefix = (vaddr >> 3) & IntAddrPrefixMask;
173 if (prefix == IntAddrPrefixCPUID) {
174 panic("CPUID memory space not yet implemented!\n");
175 } else if (prefix == IntAddrPrefixMSR) {
176 vaddr = (vaddr >> 3) & ~IntAddrPrefixMask;
177 req->setFlags(Request::MMAPPED_IPR);
178
179 MiscRegIndex regNum;
180 if (!msrAddrToIndex(regNum, vaddr))
181 return new GeneralProtection(0);
182
183 //The index is multiplied by the size of a MiscReg so that
184 //any memory dependence calculations will not see these as
185 //overlapping.
186 req->setPaddr((Addr)regNum * sizeof(MiscReg));
187 return NoFault;
188 } else if (prefix == IntAddrPrefixIO) {
189 // TODO If CPL > IOPL or in virtual mode, check the I/O permission
190 // bitmap in the TSS.
191
192 Addr IOPort = vaddr & ~IntAddrPrefixMask;
193 // Make sure the address fits in the expected 16 bit IO address
194 // space.
195 assert(!(IOPort & ~0xFFFF));
196 if (IOPort == 0xCF8 && req->getSize() == 4) {
197 req->setFlags(Request::MMAPPED_IPR);
198 req->setPaddr(MISCREG_PCI_CONFIG_ADDRESS * sizeof(MiscReg));
199 } else if ((IOPort & ~mask(2)) == 0xCFC) {
200 req->setFlags(Request::UNCACHEABLE);
201 Addr configAddress =
202 tc->readMiscRegNoEffect(MISCREG_PCI_CONFIG_ADDRESS);
203 if (bits(configAddress, 31, 31)) {
204 req->setPaddr(PhysAddrPrefixPciConfig |
205 mbits(configAddress, 30, 2) |
206 (IOPort & mask(2)));
207 } else {
208 req->setPaddr(PhysAddrPrefixIO | IOPort);
209 }
210 } else {
211 req->setFlags(Request::UNCACHEABLE);
212 req->setPaddr(PhysAddrPrefixIO | IOPort);
213 }
214 return NoFault;
215 } else {
216 panic("Access to unrecognized internal address space %#x.\n",
217 prefix);
218 }
219}
220
221Fault
222TLB::translate(RequestPtr req, ThreadContext *tc, Translation *translation,
223 Mode mode, bool &delayedResponse, bool timing)
224{
225 uint32_t flags = req->getFlags();
226 int seg = flags & SegmentFlagMask;
227 bool storeCheck = flags & (StoreCheck << FlagShift);
228
229 delayedResponse = false;
230
231 // If this is true, we're dealing with a request to a non-memory address
232 // space.
233 if (seg == SEGMENT_REG_MS) {
234 return translateInt(req, tc);
235 }
236
237 Addr vaddr = req->getVaddr();
238 DPRINTF(TLB, "Translating vaddr %#x.\n", vaddr);
239
240 HandyM5Reg m5Reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
241
242 // If protected mode has been enabled...
243 if (m5Reg.prot) {
244 DPRINTF(TLB, "In protected mode.\n");
245 // If we're not in 64-bit mode, do protection/limit checks
246 if (m5Reg.mode != LongMode) {
247 DPRINTF(TLB, "Not in long mode. Checking segment protection.\n");
248 // Check for a NULL segment selector.
249 if (!(seg == SEGMENT_REG_TSG || seg == SYS_SEGMENT_REG_IDTR ||
250 seg == SEGMENT_REG_HS || seg == SEGMENT_REG_LS)
251 && !tc->readMiscRegNoEffect(MISCREG_SEG_SEL(seg)))
252 return new GeneralProtection(0);
253 bool expandDown = false;
254 SegAttr attr = tc->readMiscRegNoEffect(MISCREG_SEG_ATTR(seg));
255 if (seg >= SEGMENT_REG_ES && seg <= SEGMENT_REG_HS) {
256 if (!attr.writable && (mode == Write || storeCheck))
257 return new GeneralProtection(0);
258 if (!attr.readable && mode == Read)
259 return new GeneralProtection(0);
260 expandDown = attr.expandDown;
261
262 }
263 Addr base = tc->readMiscRegNoEffect(MISCREG_SEG_BASE(seg));
264 Addr limit = tc->readMiscRegNoEffect(MISCREG_SEG_LIMIT(seg));
265 // This assumes we're not in 64 bit mode. If we were, the default
266 // address size is 64 bits, overridable to 32.
267 int size = 32;
268 bool sizeOverride = (flags & (AddrSizeFlagBit << FlagShift));
269 SegAttr csAttr = tc->readMiscRegNoEffect(MISCREG_CS_ATTR);
270 if ((csAttr.defaultSize && sizeOverride) ||
271 (!csAttr.defaultSize && !sizeOverride))
272 size = 16;
273 Addr offset = bits(vaddr - base, size-1, 0);
274 Addr endOffset = offset + req->getSize() - 1;
275 if (expandDown) {
276 DPRINTF(TLB, "Checking an expand down segment.\n");
277 warn_once("Expand down segments are untested.\n");
278 if (offset <= limit || endOffset <= limit)
279 return new GeneralProtection(0);
280 } else {
281 if (offset > limit || endOffset > limit)
282 return new GeneralProtection(0);
283 }
284 }
285 // If paging is enabled, do the translation.
286 if (m5Reg.paging) {
287 DPRINTF(TLB, "Paging enabled.\n");
288 // The vaddr already has the segment base applied.
289 TlbEntry *entry = lookup(vaddr);
290 if (!entry) {
291 if (FullSystem) {
292 Fault fault = walker->start(tc, translation, req, mode);
293 if (timing || fault != NoFault) {
294 // This gets ignored in atomic mode.
295 delayedResponse = true;
296 return fault;
297 }
298 entry = lookup(vaddr);
299 assert(entry);
300 } else {
301 DPRINTF(TLB, "Handling a TLB miss for "
302 "address %#x at pc %#x.\n",
303 vaddr, tc->instAddr());
304
305 Process *p = tc->getProcessPtr();
306 TlbEntry newEntry;
307 bool success = p->pTable->lookup(vaddr, newEntry);
308 if (!success && mode != Execute) {
309 // Check if we just need to grow the stack.
310 if (p->fixupStackFault(vaddr)) {
311 // If we did, lookup the entry for the new page.
312 success = p->pTable->lookup(vaddr, newEntry);
313 }
314 }
315 if (!success) {
316 return new PageFault(vaddr, true, mode, true, false);
317 } else {
318 Addr alignedVaddr = p->pTable->pageAlign(vaddr);
319 DPRINTF(TLB, "Mapping %#x to %#x\n", alignedVaddr,
320 newEntry.pageStart());
321 entry = insert(alignedVaddr, newEntry);
322 }
323 DPRINTF(TLB, "Miss was serviced.\n");
324 }
325 }
326 // Do paging protection checks.
327 bool inUser = (m5Reg.cpl == 3 &&
328 !(flags & (CPL0FlagBit << FlagShift)));
329 CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0);
330 bool badWrite = (!entry->writable && (inUser || cr0.wp));
331 if ((inUser && !entry->user) || (mode == Write && badWrite)) {
332 // The page must have been present to get into the TLB in
333 // the first place. We'll assume the reserved bits are
334 // fine even though we're not checking them.
335 return new PageFault(vaddr, true, mode, inUser, false);
336 }
337 if (storeCheck && badWrite) {
338 // This would fault if this were a write, so return a page
339 // fault that reflects that happening.
340 return new PageFault(vaddr, true, Write, inUser, false);
341 }
342
343
344 DPRINTF(TLB, "Entry found with paddr %#x, "
345 "doing protection checks.\n", entry->paddr);
346 Addr paddr = entry->paddr | (vaddr & (entry->size-1));
347 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, paddr);
348 req->setPaddr(paddr);
349 if (entry->uncacheable)
350 req->setFlags(Request::UNCACHEABLE);
351 } else {
352 //Use the address which already has segmentation applied.
353 DPRINTF(TLB, "Paging disabled.\n");
354 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr);
355 req->setPaddr(vaddr);
356 }
357 } else {
358 // Real mode
359 DPRINTF(TLB, "In real mode.\n");
360 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr);
361 req->setPaddr(vaddr);
362 }
363 // Check for an access to the local APIC
364 if (FullSystem) {
365 LocalApicBase localApicBase =
366 tc->readMiscRegNoEffect(MISCREG_APIC_BASE);
367 Addr baseAddr = localApicBase.base * PageBytes;
368 Addr paddr = req->getPaddr();
369 if (baseAddr <= paddr && baseAddr + PageBytes > paddr) {
370 // The Intel developer's manuals say the below restrictions apply,
371 // but the linux kernel, because of a compiler optimization, breaks
372 // them.
373 /*
374 // Check alignment
375 if (paddr & ((32/8) - 1))
376 return new GeneralProtection(0);
377 // Check access size
378 if (req->getSize() != (32/8))
379 return new GeneralProtection(0);
380 */
381 // Force the access to be uncacheable.
382 req->setFlags(Request::UNCACHEABLE);
383 req->setPaddr(x86LocalAPICAddress(tc->contextId(),
384 paddr - baseAddr));
385 }
386 }
387 return NoFault;
388};
389
390Fault
391TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
392{
393 bool delayedResponse;
394 return TLB::translate(req, tc, NULL, mode, delayedResponse, false);
395}
396
397void
398TLB::translateTiming(RequestPtr req, ThreadContext *tc,
399 Translation *translation, Mode mode)
400{
401 bool delayedResponse;
402 assert(translation);
403 Fault fault =
404 TLB::translate(req, tc, translation, mode, delayedResponse, true);
405 if (!delayedResponse)
406 translation->finish(fault, req, tc, mode);
407}
408
52#include "cpu/base.hh"
53#include "cpu/thread_context.hh"
54#include "debug/TLB.hh"
55#include "mem/packet_access.hh"
56#include "mem/page_table.hh"
57#include "mem/request.hh"
58#include "sim/full_system.hh"
59#include "sim/process.hh"
60
61namespace X86ISA {
62
63TLB::TLB(const Params *p) : BaseTLB(p), configAddress(0), size(p->size)
64{
65 tlb = new TlbEntry[size];
66 std::memset(tlb, 0, sizeof(TlbEntry) * size);
67
68 for (int x = 0; x < size; x++)
69 freeList.push_back(&tlb[x]);
70
71 walker = p->walker;
72 walker->setTLB(this);
73}
74
75TlbEntry *
76TLB::insert(Addr vpn, TlbEntry &entry)
77{
78 //TODO Deal with conflicting entries
79
80 TlbEntry *newEntry = NULL;
81 if (!freeList.empty()) {
82 newEntry = freeList.front();
83 freeList.pop_front();
84 } else {
85 newEntry = entryList.back();
86 entryList.pop_back();
87 }
88 *newEntry = entry;
89 newEntry->vaddr = vpn;
90 entryList.push_front(newEntry);
91 return newEntry;
92}
93
94TLB::EntryList::iterator
95TLB::lookupIt(Addr va, bool update_lru)
96{
97 //TODO make this smarter at some point
98 EntryList::iterator entry;
99 for (entry = entryList.begin(); entry != entryList.end(); entry++) {
100 if ((*entry)->vaddr <= va && (*entry)->vaddr + (*entry)->size > va) {
101 DPRINTF(TLB, "Matched vaddr %#x to entry starting at %#x "
102 "with size %#x.\n", va, (*entry)->vaddr, (*entry)->size);
103 if (update_lru) {
104 entryList.push_front(*entry);
105 entryList.erase(entry);
106 entry = entryList.begin();
107 }
108 break;
109 }
110 }
111 return entry;
112}
113
114TlbEntry *
115TLB::lookup(Addr va, bool update_lru)
116{
117 EntryList::iterator entry = lookupIt(va, update_lru);
118 if (entry == entryList.end())
119 return NULL;
120 else
121 return *entry;
122}
123
124void
125TLB::invalidateAll()
126{
127 DPRINTF(TLB, "Invalidating all entries.\n");
128 while (!entryList.empty()) {
129 TlbEntry *entry = entryList.front();
130 entryList.pop_front();
131 freeList.push_back(entry);
132 }
133}
134
135void
136TLB::setConfigAddress(uint32_t addr)
137{
138 configAddress = addr;
139}
140
141void
142TLB::invalidateNonGlobal()
143{
144 DPRINTF(TLB, "Invalidating all non global entries.\n");
145 EntryList::iterator entryIt;
146 for (entryIt = entryList.begin(); entryIt != entryList.end();) {
147 if (!(*entryIt)->global) {
148 freeList.push_back(*entryIt);
149 entryList.erase(entryIt++);
150 } else {
151 entryIt++;
152 }
153 }
154}
155
156void
157TLB::demapPage(Addr va, uint64_t asn)
158{
159 EntryList::iterator entry = lookupIt(va, false);
160 if (entry != entryList.end()) {
161 freeList.push_back(*entry);
162 entryList.erase(entry);
163 }
164}
165
166Fault
167TLB::translateInt(RequestPtr req, ThreadContext *tc)
168{
169 DPRINTF(TLB, "Addresses references internal memory.\n");
170 Addr vaddr = req->getVaddr();
171 Addr prefix = (vaddr >> 3) & IntAddrPrefixMask;
172 if (prefix == IntAddrPrefixCPUID) {
173 panic("CPUID memory space not yet implemented!\n");
174 } else if (prefix == IntAddrPrefixMSR) {
175 vaddr = (vaddr >> 3) & ~IntAddrPrefixMask;
176 req->setFlags(Request::MMAPPED_IPR);
177
178 MiscRegIndex regNum;
179 if (!msrAddrToIndex(regNum, vaddr))
180 return new GeneralProtection(0);
181
182 //The index is multiplied by the size of a MiscReg so that
183 //any memory dependence calculations will not see these as
184 //overlapping.
185 req->setPaddr((Addr)regNum * sizeof(MiscReg));
186 return NoFault;
187 } else if (prefix == IntAddrPrefixIO) {
188 // TODO If CPL > IOPL or in virtual mode, check the I/O permission
189 // bitmap in the TSS.
190
191 Addr IOPort = vaddr & ~IntAddrPrefixMask;
192 // Make sure the address fits in the expected 16 bit IO address
193 // space.
194 assert(!(IOPort & ~0xFFFF));
195 if (IOPort == 0xCF8 && req->getSize() == 4) {
196 req->setFlags(Request::MMAPPED_IPR);
197 req->setPaddr(MISCREG_PCI_CONFIG_ADDRESS * sizeof(MiscReg));
198 } else if ((IOPort & ~mask(2)) == 0xCFC) {
199 req->setFlags(Request::UNCACHEABLE);
200 Addr configAddress =
201 tc->readMiscRegNoEffect(MISCREG_PCI_CONFIG_ADDRESS);
202 if (bits(configAddress, 31, 31)) {
203 req->setPaddr(PhysAddrPrefixPciConfig |
204 mbits(configAddress, 30, 2) |
205 (IOPort & mask(2)));
206 } else {
207 req->setPaddr(PhysAddrPrefixIO | IOPort);
208 }
209 } else {
210 req->setFlags(Request::UNCACHEABLE);
211 req->setPaddr(PhysAddrPrefixIO | IOPort);
212 }
213 return NoFault;
214 } else {
215 panic("Access to unrecognized internal address space %#x.\n",
216 prefix);
217 }
218}
219
220Fault
221TLB::translate(RequestPtr req, ThreadContext *tc, Translation *translation,
222 Mode mode, bool &delayedResponse, bool timing)
223{
224 uint32_t flags = req->getFlags();
225 int seg = flags & SegmentFlagMask;
226 bool storeCheck = flags & (StoreCheck << FlagShift);
227
228 delayedResponse = false;
229
230 // If this is true, we're dealing with a request to a non-memory address
231 // space.
232 if (seg == SEGMENT_REG_MS) {
233 return translateInt(req, tc);
234 }
235
236 Addr vaddr = req->getVaddr();
237 DPRINTF(TLB, "Translating vaddr %#x.\n", vaddr);
238
239 HandyM5Reg m5Reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
240
241 // If protected mode has been enabled...
242 if (m5Reg.prot) {
243 DPRINTF(TLB, "In protected mode.\n");
244 // If we're not in 64-bit mode, do protection/limit checks
245 if (m5Reg.mode != LongMode) {
246 DPRINTF(TLB, "Not in long mode. Checking segment protection.\n");
247 // Check for a NULL segment selector.
248 if (!(seg == SEGMENT_REG_TSG || seg == SYS_SEGMENT_REG_IDTR ||
249 seg == SEGMENT_REG_HS || seg == SEGMENT_REG_LS)
250 && !tc->readMiscRegNoEffect(MISCREG_SEG_SEL(seg)))
251 return new GeneralProtection(0);
252 bool expandDown = false;
253 SegAttr attr = tc->readMiscRegNoEffect(MISCREG_SEG_ATTR(seg));
254 if (seg >= SEGMENT_REG_ES && seg <= SEGMENT_REG_HS) {
255 if (!attr.writable && (mode == Write || storeCheck))
256 return new GeneralProtection(0);
257 if (!attr.readable && mode == Read)
258 return new GeneralProtection(0);
259 expandDown = attr.expandDown;
260
261 }
262 Addr base = tc->readMiscRegNoEffect(MISCREG_SEG_BASE(seg));
263 Addr limit = tc->readMiscRegNoEffect(MISCREG_SEG_LIMIT(seg));
264 // This assumes we're not in 64 bit mode. If we were, the default
265 // address size is 64 bits, overridable to 32.
266 int size = 32;
267 bool sizeOverride = (flags & (AddrSizeFlagBit << FlagShift));
268 SegAttr csAttr = tc->readMiscRegNoEffect(MISCREG_CS_ATTR);
269 if ((csAttr.defaultSize && sizeOverride) ||
270 (!csAttr.defaultSize && !sizeOverride))
271 size = 16;
272 Addr offset = bits(vaddr - base, size-1, 0);
273 Addr endOffset = offset + req->getSize() - 1;
274 if (expandDown) {
275 DPRINTF(TLB, "Checking an expand down segment.\n");
276 warn_once("Expand down segments are untested.\n");
277 if (offset <= limit || endOffset <= limit)
278 return new GeneralProtection(0);
279 } else {
280 if (offset > limit || endOffset > limit)
281 return new GeneralProtection(0);
282 }
283 }
284 // If paging is enabled, do the translation.
285 if (m5Reg.paging) {
286 DPRINTF(TLB, "Paging enabled.\n");
287 // The vaddr already has the segment base applied.
288 TlbEntry *entry = lookup(vaddr);
289 if (!entry) {
290 if (FullSystem) {
291 Fault fault = walker->start(tc, translation, req, mode);
292 if (timing || fault != NoFault) {
293 // This gets ignored in atomic mode.
294 delayedResponse = true;
295 return fault;
296 }
297 entry = lookup(vaddr);
298 assert(entry);
299 } else {
300 DPRINTF(TLB, "Handling a TLB miss for "
301 "address %#x at pc %#x.\n",
302 vaddr, tc->instAddr());
303
304 Process *p = tc->getProcessPtr();
305 TlbEntry newEntry;
306 bool success = p->pTable->lookup(vaddr, newEntry);
307 if (!success && mode != Execute) {
308 // Check if we just need to grow the stack.
309 if (p->fixupStackFault(vaddr)) {
310 // If we did, lookup the entry for the new page.
311 success = p->pTable->lookup(vaddr, newEntry);
312 }
313 }
314 if (!success) {
315 return new PageFault(vaddr, true, mode, true, false);
316 } else {
317 Addr alignedVaddr = p->pTable->pageAlign(vaddr);
318 DPRINTF(TLB, "Mapping %#x to %#x\n", alignedVaddr,
319 newEntry.pageStart());
320 entry = insert(alignedVaddr, newEntry);
321 }
322 DPRINTF(TLB, "Miss was serviced.\n");
323 }
324 }
325 // Do paging protection checks.
326 bool inUser = (m5Reg.cpl == 3 &&
327 !(flags & (CPL0FlagBit << FlagShift)));
328 CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0);
329 bool badWrite = (!entry->writable && (inUser || cr0.wp));
330 if ((inUser && !entry->user) || (mode == Write && badWrite)) {
331 // The page must have been present to get into the TLB in
332 // the first place. We'll assume the reserved bits are
333 // fine even though we're not checking them.
334 return new PageFault(vaddr, true, mode, inUser, false);
335 }
336 if (storeCheck && badWrite) {
337 // This would fault if this were a write, so return a page
338 // fault that reflects that happening.
339 return new PageFault(vaddr, true, Write, inUser, false);
340 }
341
342
343 DPRINTF(TLB, "Entry found with paddr %#x, "
344 "doing protection checks.\n", entry->paddr);
345 Addr paddr = entry->paddr | (vaddr & (entry->size-1));
346 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, paddr);
347 req->setPaddr(paddr);
348 if (entry->uncacheable)
349 req->setFlags(Request::UNCACHEABLE);
350 } else {
351 //Use the address which already has segmentation applied.
352 DPRINTF(TLB, "Paging disabled.\n");
353 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr);
354 req->setPaddr(vaddr);
355 }
356 } else {
357 // Real mode
358 DPRINTF(TLB, "In real mode.\n");
359 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr);
360 req->setPaddr(vaddr);
361 }
362 // Check for an access to the local APIC
363 if (FullSystem) {
364 LocalApicBase localApicBase =
365 tc->readMiscRegNoEffect(MISCREG_APIC_BASE);
366 Addr baseAddr = localApicBase.base * PageBytes;
367 Addr paddr = req->getPaddr();
368 if (baseAddr <= paddr && baseAddr + PageBytes > paddr) {
369 // The Intel developer's manuals say the below restrictions apply,
370 // but the linux kernel, because of a compiler optimization, breaks
371 // them.
372 /*
373 // Check alignment
374 if (paddr & ((32/8) - 1))
375 return new GeneralProtection(0);
376 // Check access size
377 if (req->getSize() != (32/8))
378 return new GeneralProtection(0);
379 */
380 // Force the access to be uncacheable.
381 req->setFlags(Request::UNCACHEABLE);
382 req->setPaddr(x86LocalAPICAddress(tc->contextId(),
383 paddr - baseAddr));
384 }
385 }
386 return NoFault;
387};
388
389Fault
390TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
391{
392 bool delayedResponse;
393 return TLB::translate(req, tc, NULL, mode, delayedResponse, false);
394}
395
396void
397TLB::translateTiming(RequestPtr req, ThreadContext *tc,
398 Translation *translation, Mode mode)
399{
400 bool delayedResponse;
401 assert(translation);
402 Fault fault =
403 TLB::translate(req, tc, translation, mode, delayedResponse, true);
404 if (!delayedResponse)
405 translation->finish(fault, req, tc, mode);
406}
407
409#if FULL_SYSTEM
410
411Tick
412TLB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
413{
414 return tc->getCpuPtr()->ticks(1);
415}
416
417Tick
418TLB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
419{
420 return tc->getCpuPtr()->ticks(1);
421}
422
423Walker *
424TLB::getWalker()
425{
426 return walker;
427}
428
408Walker *
409TLB::getWalker()
410{
411 return walker;
412}
413
429#endif
430
431void
432TLB::serialize(std::ostream &os)
433{
434}
435
436void
437TLB::unserialize(Checkpoint *cp, const std::string &section)
438{
439}
440
441} // namespace X86ISA
442
443X86ISA::TLB *
444X86TLBParams::create()
445{
446 return new X86ISA::TLB(this);
447}
414void
415TLB::serialize(std::ostream &os)
416{
417}
418
419void
420TLB::unserialize(Checkpoint *cp, const std::string &section)
421{
422}
423
424} // namespace X86ISA
425
426X86ISA::TLB *
427X86TLBParams::create()
428{
429 return new X86ISA::TLB(this);
430}