1/*
2 * Copyright (c) 2007-2008 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 */
39
40#include <cstring>
41
42#include "arch/x86/insts/microldstop.hh"
43#include "arch/x86/regs/misc.hh"
44#include "arch/x86/faults.hh"
45#include "arch/x86/pagetable.hh"
46#include "arch/x86/tlb.hh"
47#include "arch/x86/x86_traits.hh"
48#include "base/bitfield.hh"
49#include "base/trace.hh"
50#include "config/full_system.hh"
51#include "cpu/base.hh"
52#include "cpu/thread_context.hh"
| 1/*
2 * Copyright (c) 2007-2008 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 */
39
40#include <cstring>
41
42#include "arch/x86/insts/microldstop.hh"
43#include "arch/x86/regs/misc.hh"
44#include "arch/x86/faults.hh"
45#include "arch/x86/pagetable.hh"
46#include "arch/x86/tlb.hh"
47#include "arch/x86/x86_traits.hh"
48#include "base/bitfield.hh"
49#include "base/trace.hh"
50#include "config/full_system.hh"
51#include "cpu/base.hh"
52#include "cpu/thread_context.hh"
|
53#include "mem/packet_access.hh"
54#include "mem/request.hh"
55
56#if FULL_SYSTEM
57#include "arch/x86/pagetable_walker.hh"
58#else
59#include "mem/page_table.hh"
60#include "sim/process.hh"
61#endif
62
63namespace X86ISA {
64
65TLB::TLB(const Params *p) : BaseTLB(p), configAddress(0), size(p->size)
66{
67 tlb = new TlbEntry[size];
68 std::memset(tlb, 0, sizeof(TlbEntry) * size);
69
70 for (int x = 0; x < size; x++)
71 freeList.push_back(&tlb[x]);
72
73#if FULL_SYSTEM
74 walker = p->walker;
75 walker->setTLB(this);
76#endif
77}
78
79TlbEntry *
80TLB::insert(Addr vpn, TlbEntry &entry)
81{
82 //TODO Deal with conflicting entries
83
84 TlbEntry *newEntry = NULL;
85 if (!freeList.empty()) {
86 newEntry = freeList.front();
87 freeList.pop_front();
88 } else {
89 newEntry = entryList.back();
90 entryList.pop_back();
91 }
92 *newEntry = entry;
93 newEntry->vaddr = vpn;
94 entryList.push_front(newEntry);
95 return newEntry;
96}
97
98TLB::EntryList::iterator
99TLB::lookupIt(Addr va, bool update_lru)
100{
101 //TODO make this smarter at some point
102 EntryList::iterator entry;
103 for (entry = entryList.begin(); entry != entryList.end(); entry++) {
104 if ((*entry)->vaddr <= va && (*entry)->vaddr + (*entry)->size > va) {
105 DPRINTF(TLB, "Matched vaddr %#x to entry starting at %#x "
106 "with size %#x.\n", va, (*entry)->vaddr, (*entry)->size);
107 if (update_lru) {
108 entryList.push_front(*entry);
109 entryList.erase(entry);
110 entry = entryList.begin();
111 }
112 break;
113 }
114 }
115 return entry;
116}
117
118TlbEntry *
119TLB::lookup(Addr va, bool update_lru)
120{
121 EntryList::iterator entry = lookupIt(va, update_lru);
122 if (entry == entryList.end())
123 return NULL;
124 else
125 return *entry;
126}
127
128void
129TLB::invalidateAll()
130{
131 DPRINTF(TLB, "Invalidating all entries.\n");
132 while (!entryList.empty()) {
133 TlbEntry *entry = entryList.front();
134 entryList.pop_front();
135 freeList.push_back(entry);
136 }
137}
138
139void
140TLB::setConfigAddress(uint32_t addr)
141{
142 configAddress = addr;
143}
144
145void
146TLB::invalidateNonGlobal()
147{
148 DPRINTF(TLB, "Invalidating all non global entries.\n");
149 EntryList::iterator entryIt;
150 for (entryIt = entryList.begin(); entryIt != entryList.end();) {
151 if (!(*entryIt)->global) {
152 freeList.push_back(*entryIt);
153 entryList.erase(entryIt++);
154 } else {
155 entryIt++;
156 }
157 }
158}
159
160void
161TLB::demapPage(Addr va, uint64_t asn)
162{
163 EntryList::iterator entry = lookupIt(va, false);
164 if (entry != entryList.end()) {
165 freeList.push_back(*entry);
166 entryList.erase(entry);
167 }
168}
169
170Fault
171TLB::translateInt(RequestPtr req, ThreadContext *tc)
172{
173 DPRINTF(TLB, "Addresses references internal memory.\n");
174 Addr vaddr = req->getVaddr();
175 Addr prefix = (vaddr >> 3) & IntAddrPrefixMask;
176 if (prefix == IntAddrPrefixCPUID) {
177 panic("CPUID memory space not yet implemented!\n");
178 } else if (prefix == IntAddrPrefixMSR) {
179 vaddr = vaddr >> 3;
180 req->setFlags(Request::MMAPPED_IPR);
181 Addr regNum = 0;
182 switch (vaddr & ~IntAddrPrefixMask) {
183 case 0x10:
184 regNum = MISCREG_TSC;
185 break;
186 case 0x1B:
187 regNum = MISCREG_APIC_BASE;
188 break;
189 case 0xFE:
190 regNum = MISCREG_MTRRCAP;
191 break;
192 case 0x174:
193 regNum = MISCREG_SYSENTER_CS;
194 break;
195 case 0x175:
196 regNum = MISCREG_SYSENTER_ESP;
197 break;
198 case 0x176:
199 regNum = MISCREG_SYSENTER_EIP;
200 break;
201 case 0x179:
202 regNum = MISCREG_MCG_CAP;
203 break;
204 case 0x17A:
205 regNum = MISCREG_MCG_STATUS;
206 break;
207 case 0x17B:
208 regNum = MISCREG_MCG_CTL;
209 break;
210 case 0x1D9:
211 regNum = MISCREG_DEBUG_CTL_MSR;
212 break;
213 case 0x1DB:
214 regNum = MISCREG_LAST_BRANCH_FROM_IP;
215 break;
216 case 0x1DC:
217 regNum = MISCREG_LAST_BRANCH_TO_IP;
218 break;
219 case 0x1DD:
220 regNum = MISCREG_LAST_EXCEPTION_FROM_IP;
221 break;
222 case 0x1DE:
223 regNum = MISCREG_LAST_EXCEPTION_TO_IP;
224 break;
225 case 0x200:
226 regNum = MISCREG_MTRR_PHYS_BASE_0;
227 break;
228 case 0x201:
229 regNum = MISCREG_MTRR_PHYS_MASK_0;
230 break;
231 case 0x202:
232 regNum = MISCREG_MTRR_PHYS_BASE_1;
233 break;
234 case 0x203:
235 regNum = MISCREG_MTRR_PHYS_MASK_1;
236 break;
237 case 0x204:
238 regNum = MISCREG_MTRR_PHYS_BASE_2;
239 break;
240 case 0x205:
241 regNum = MISCREG_MTRR_PHYS_MASK_2;
242 break;
243 case 0x206:
244 regNum = MISCREG_MTRR_PHYS_BASE_3;
245 break;
246 case 0x207:
247 regNum = MISCREG_MTRR_PHYS_MASK_3;
248 break;
249 case 0x208:
250 regNum = MISCREG_MTRR_PHYS_BASE_4;
251 break;
252 case 0x209:
253 regNum = MISCREG_MTRR_PHYS_MASK_4;
254 break;
255 case 0x20A:
256 regNum = MISCREG_MTRR_PHYS_BASE_5;
257 break;
258 case 0x20B:
259 regNum = MISCREG_MTRR_PHYS_MASK_5;
260 break;
261 case 0x20C:
262 regNum = MISCREG_MTRR_PHYS_BASE_6;
263 break;
264 case 0x20D:
265 regNum = MISCREG_MTRR_PHYS_MASK_6;
266 break;
267 case 0x20E:
268 regNum = MISCREG_MTRR_PHYS_BASE_7;
269 break;
270 case 0x20F:
271 regNum = MISCREG_MTRR_PHYS_MASK_7;
272 break;
273 case 0x250:
274 regNum = MISCREG_MTRR_FIX_64K_00000;
275 break;
276 case 0x258:
277 regNum = MISCREG_MTRR_FIX_16K_80000;
278 break;
279 case 0x259:
280 regNum = MISCREG_MTRR_FIX_16K_A0000;
281 break;
282 case 0x268:
283 regNum = MISCREG_MTRR_FIX_4K_C0000;
284 break;
285 case 0x269:
286 regNum = MISCREG_MTRR_FIX_4K_C8000;
287 break;
288 case 0x26A:
289 regNum = MISCREG_MTRR_FIX_4K_D0000;
290 break;
291 case 0x26B:
292 regNum = MISCREG_MTRR_FIX_4K_D8000;
293 break;
294 case 0x26C:
295 regNum = MISCREG_MTRR_FIX_4K_E0000;
296 break;
297 case 0x26D:
298 regNum = MISCREG_MTRR_FIX_4K_E8000;
299 break;
300 case 0x26E:
301 regNum = MISCREG_MTRR_FIX_4K_F0000;
302 break;
303 case 0x26F:
304 regNum = MISCREG_MTRR_FIX_4K_F8000;
305 break;
306 case 0x277:
307 regNum = MISCREG_PAT;
308 break;
309 case 0x2FF:
310 regNum = MISCREG_DEF_TYPE;
311 break;
312 case 0x400:
313 regNum = MISCREG_MC0_CTL;
314 break;
315 case 0x404:
316 regNum = MISCREG_MC1_CTL;
317 break;
318 case 0x408:
319 regNum = MISCREG_MC2_CTL;
320 break;
321 case 0x40C:
322 regNum = MISCREG_MC3_CTL;
323 break;
324 case 0x410:
325 regNum = MISCREG_MC4_CTL;
326 break;
327 case 0x414:
328 regNum = MISCREG_MC5_CTL;
329 break;
330 case 0x418:
331 regNum = MISCREG_MC6_CTL;
332 break;
333 case 0x41C:
334 regNum = MISCREG_MC7_CTL;
335 break;
336 case 0x401:
337 regNum = MISCREG_MC0_STATUS;
338 break;
339 case 0x405:
340 regNum = MISCREG_MC1_STATUS;
341 break;
342 case 0x409:
343 regNum = MISCREG_MC2_STATUS;
344 break;
345 case 0x40D:
346 regNum = MISCREG_MC3_STATUS;
347 break;
348 case 0x411:
349 regNum = MISCREG_MC4_STATUS;
350 break;
351 case 0x415:
352 regNum = MISCREG_MC5_STATUS;
353 break;
354 case 0x419:
355 regNum = MISCREG_MC6_STATUS;
356 break;
357 case 0x41D:
358 regNum = MISCREG_MC7_STATUS;
359 break;
360 case 0x402:
361 regNum = MISCREG_MC0_ADDR;
362 break;
363 case 0x406:
364 regNum = MISCREG_MC1_ADDR;
365 break;
366 case 0x40A:
367 regNum = MISCREG_MC2_ADDR;
368 break;
369 case 0x40E:
370 regNum = MISCREG_MC3_ADDR;
371 break;
372 case 0x412:
373 regNum = MISCREG_MC4_ADDR;
374 break;
375 case 0x416:
376 regNum = MISCREG_MC5_ADDR;
377 break;
378 case 0x41A:
379 regNum = MISCREG_MC6_ADDR;
380 break;
381 case 0x41E:
382 regNum = MISCREG_MC7_ADDR;
383 break;
384 case 0x403:
385 regNum = MISCREG_MC0_MISC;
386 break;
387 case 0x407:
388 regNum = MISCREG_MC1_MISC;
389 break;
390 case 0x40B:
391 regNum = MISCREG_MC2_MISC;
392 break;
393 case 0x40F:
394 regNum = MISCREG_MC3_MISC;
395 break;
396 case 0x413:
397 regNum = MISCREG_MC4_MISC;
398 break;
399 case 0x417:
400 regNum = MISCREG_MC5_MISC;
401 break;
402 case 0x41B:
403 regNum = MISCREG_MC6_MISC;
404 break;
405 case 0x41F:
406 regNum = MISCREG_MC7_MISC;
407 break;
408 case 0xC0000080:
409 regNum = MISCREG_EFER;
410 break;
411 case 0xC0000081:
412 regNum = MISCREG_STAR;
413 break;
414 case 0xC0000082:
415 regNum = MISCREG_LSTAR;
416 break;
417 case 0xC0000083:
418 regNum = MISCREG_CSTAR;
419 break;
420 case 0xC0000084:
421 regNum = MISCREG_SF_MASK;
422 break;
423 case 0xC0000100:
424 regNum = MISCREG_FS_BASE;
425 break;
426 case 0xC0000101:
427 regNum = MISCREG_GS_BASE;
428 break;
429 case 0xC0000102:
430 regNum = MISCREG_KERNEL_GS_BASE;
431 break;
432 case 0xC0000103:
433 regNum = MISCREG_TSC_AUX;
434 break;
435 case 0xC0010000:
436 regNum = MISCREG_PERF_EVT_SEL0;
437 break;
438 case 0xC0010001:
439 regNum = MISCREG_PERF_EVT_SEL1;
440 break;
441 case 0xC0010002:
442 regNum = MISCREG_PERF_EVT_SEL2;
443 break;
444 case 0xC0010003:
445 regNum = MISCREG_PERF_EVT_SEL3;
446 break;
447 case 0xC0010004:
448 regNum = MISCREG_PERF_EVT_CTR0;
449 break;
450 case 0xC0010005:
451 regNum = MISCREG_PERF_EVT_CTR1;
452 break;
453 case 0xC0010006:
454 regNum = MISCREG_PERF_EVT_CTR2;
455 break;
456 case 0xC0010007:
457 regNum = MISCREG_PERF_EVT_CTR3;
458 break;
459 case 0xC0010010:
460 regNum = MISCREG_SYSCFG;
461 break;
462 case 0xC0010016:
463 regNum = MISCREG_IORR_BASE0;
464 break;
465 case 0xC0010017:
466 regNum = MISCREG_IORR_BASE1;
467 break;
468 case 0xC0010018:
469 regNum = MISCREG_IORR_MASK0;
470 break;
471 case 0xC0010019:
472 regNum = MISCREG_IORR_MASK1;
473 break;
474 case 0xC001001A:
475 regNum = MISCREG_TOP_MEM;
476 break;
477 case 0xC001001D:
478 regNum = MISCREG_TOP_MEM2;
479 break;
480 case 0xC0010114:
481 regNum = MISCREG_VM_CR;
482 break;
483 case 0xC0010115:
484 regNum = MISCREG_IGNNE;
485 break;
486 case 0xC0010116:
487 regNum = MISCREG_SMM_CTL;
488 break;
489 case 0xC0010117:
490 regNum = MISCREG_VM_HSAVE_PA;
491 break;
492 default:
493 return new GeneralProtection(0);
494 }
495 //The index is multiplied by the size of a MiscReg so that
496 //any memory dependence calculations will not see these as
497 //overlapping.
498 req->setPaddr(regNum * sizeof(MiscReg));
499 return NoFault;
500 } else if (prefix == IntAddrPrefixIO) {
501 // TODO If CPL > IOPL or in virtual mode, check the I/O permission
502 // bitmap in the TSS.
503
504 Addr IOPort = vaddr & ~IntAddrPrefixMask;
505 // Make sure the address fits in the expected 16 bit IO address
506 // space.
507 assert(!(IOPort & ~0xFFFF));
508 if (IOPort == 0xCF8 && req->getSize() == 4) {
509 req->setFlags(Request::MMAPPED_IPR);
510 req->setPaddr(MISCREG_PCI_CONFIG_ADDRESS * sizeof(MiscReg));
511 } else if ((IOPort & ~mask(2)) == 0xCFC) {
512 req->setFlags(Request::UNCACHEABLE);
513 Addr configAddress =
514 tc->readMiscRegNoEffect(MISCREG_PCI_CONFIG_ADDRESS);
515 if (bits(configAddress, 31, 31)) {
516 req->setPaddr(PhysAddrPrefixPciConfig |
517 mbits(configAddress, 30, 2) |
518 (IOPort & mask(2)));
519 } else {
520 req->setPaddr(PhysAddrPrefixIO | IOPort);
521 }
522 } else {
523 req->setFlags(Request::UNCACHEABLE);
524 req->setPaddr(PhysAddrPrefixIO | IOPort);
525 }
526 return NoFault;
527 } else {
528 panic("Access to unrecognized internal address space %#x.\n",
529 prefix);
530 }
531}
532
533Fault
534TLB::translate(RequestPtr req, ThreadContext *tc, Translation *translation,
535 Mode mode, bool &delayedResponse, bool timing)
536{
537 uint32_t flags = req->getFlags();
538 int seg = flags & SegmentFlagMask;
539 bool storeCheck = flags & (StoreCheck << FlagShift);
540
541 // If this is true, we're dealing with a request to a non-memory address
542 // space.
543 if (seg == SEGMENT_REG_MS) {
544 return translateInt(req, tc);
545 }
546
547 delayedResponse = false;
548 Addr vaddr = req->getVaddr();
549 DPRINTF(TLB, "Translating vaddr %#x.\n", vaddr);
550
551 HandyM5Reg m5Reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
552
553 // If protected mode has been enabled...
554 if (m5Reg.prot) {
555 DPRINTF(TLB, "In protected mode.\n");
556 // If we're not in 64-bit mode, do protection/limit checks
557 if (m5Reg.mode != LongMode) {
558 DPRINTF(TLB, "Not in long mode. Checking segment protection.\n");
559 // Check for a NULL segment selector.
560 if (!(seg == SEGMENT_REG_TSG || seg == SYS_SEGMENT_REG_IDTR ||
561 seg == SEGMENT_REG_HS || seg == SEGMENT_REG_LS)
562 && !tc->readMiscRegNoEffect(MISCREG_SEG_SEL(seg)))
563 return new GeneralProtection(0);
564 bool expandDown = false;
565 SegAttr attr = tc->readMiscRegNoEffect(MISCREG_SEG_ATTR(seg));
566 if (seg >= SEGMENT_REG_ES && seg <= SEGMENT_REG_HS) {
567 if (!attr.writable && (mode == Write || storeCheck))
568 return new GeneralProtection(0);
569 if (!attr.readable && mode == Read)
570 return new GeneralProtection(0);
571 expandDown = attr.expandDown;
572
573 }
574 Addr base = tc->readMiscRegNoEffect(MISCREG_SEG_BASE(seg));
575 Addr limit = tc->readMiscRegNoEffect(MISCREG_SEG_LIMIT(seg));
576 // This assumes we're not in 64 bit mode. If we were, the default
577 // address size is 64 bits, overridable to 32.
578 int size = 32;
579 bool sizeOverride = (flags & (AddrSizeFlagBit << FlagShift));
580 SegAttr csAttr = tc->readMiscRegNoEffect(MISCREG_CS_ATTR);
581 if ((csAttr.defaultSize && sizeOverride) ||
582 (!csAttr.defaultSize && !sizeOverride))
583 size = 16;
584 Addr offset = bits(vaddr - base, size-1, 0);
585 Addr endOffset = offset + req->getSize() - 1;
586 if (expandDown) {
587 DPRINTF(TLB, "Checking an expand down segment.\n");
588 warn_once("Expand down segments are untested.\n");
589 if (offset <= limit || endOffset <= limit)
590 return new GeneralProtection(0);
591 } else {
592 if (offset > limit || endOffset > limit)
593 return new GeneralProtection(0);
594 }
595 }
596 // If paging is enabled, do the translation.
597 if (m5Reg.paging) {
598 DPRINTF(TLB, "Paging enabled.\n");
599 // The vaddr already has the segment base applied.
600 TlbEntry *entry = lookup(vaddr);
601 if (!entry) {
602#if FULL_SYSTEM
603 Fault fault = walker->start(tc, translation, req, mode);
604 if (timing || fault != NoFault) {
605 // This gets ignored in atomic mode.
606 delayedResponse = true;
607 return fault;
608 }
609 entry = lookup(vaddr);
610 assert(entry);
611#else
612 DPRINTF(TLB, "Handling a TLB miss for "
613 "address %#x at pc %#x.\n",
614 vaddr, tc->instAddr());
615
616 Process *p = tc->getProcessPtr();
617 TlbEntry newEntry;
618 bool success = p->pTable->lookup(vaddr, newEntry);
619 if (!success && mode != Execute) {
620 p->checkAndAllocNextPage(vaddr);
621 success = p->pTable->lookup(vaddr, newEntry);
622 }
623 if (!success) {
624 return new PageFault(vaddr, true, mode, true, false);
625 } else {
626 Addr alignedVaddr = p->pTable->pageAlign(vaddr);
627 DPRINTF(TLB, "Mapping %#x to %#x\n", alignedVaddr,
628 newEntry.pageStart());
629 entry = insert(alignedVaddr, newEntry);
630 }
631 DPRINTF(TLB, "Miss was serviced.\n");
632#endif
633 }
634 // Do paging protection checks.
635 bool inUser = (m5Reg.cpl == 3 &&
636 !(flags & (CPL0FlagBit << FlagShift)));
637 CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0);
638 bool badWrite = (!entry->writable && (inUser || cr0.wp));
639 if ((inUser && !entry->user) || (mode == Write && badWrite)) {
640 // The page must have been present to get into the TLB in
641 // the first place. We'll assume the reserved bits are
642 // fine even though we're not checking them.
643 return new PageFault(vaddr, true, mode, inUser, false);
644 }
645 if (storeCheck && badWrite) {
646 // This would fault if this were a write, so return a page
647 // fault that reflects that happening.
648 return new PageFault(vaddr, true, Write, inUser, false);
649 }
650
651
652 DPRINTF(TLB, "Entry found with paddr %#x, "
653 "doing protection checks.\n", entry->paddr);
654 Addr paddr = entry->paddr | (vaddr & (entry->size-1));
655 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, paddr);
656 req->setPaddr(paddr);
657 if (entry->uncacheable)
658 req->setFlags(Request::UNCACHEABLE);
659 } else {
660 //Use the address which already has segmentation applied.
661 DPRINTF(TLB, "Paging disabled.\n");
662 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr);
663 req->setPaddr(vaddr);
664 }
665 } else {
666 // Real mode
667 DPRINTF(TLB, "In real mode.\n");
668 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr);
669 req->setPaddr(vaddr);
670 }
671 // Check for an access to the local APIC
672#if FULL_SYSTEM
673 LocalApicBase localApicBase = tc->readMiscRegNoEffect(MISCREG_APIC_BASE);
674 Addr baseAddr = localApicBase.base * PageBytes;
675 Addr paddr = req->getPaddr();
676 if (baseAddr <= paddr && baseAddr + PageBytes > paddr) {
677 // The Intel developer's manuals say the below restrictions apply,
678 // but the linux kernel, because of a compiler optimization, breaks
679 // them.
680 /*
681 // Check alignment
682 if (paddr & ((32/8) - 1))
683 return new GeneralProtection(0);
684 // Check access size
685 if (req->getSize() != (32/8))
686 return new GeneralProtection(0);
687 */
688 // Force the access to be uncacheable.
689 req->setFlags(Request::UNCACHEABLE);
690 req->setPaddr(x86LocalAPICAddress(tc->contextId(), paddr - baseAddr));
691 }
692#endif
693 return NoFault;
694};
695
696Fault
697TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
698{
699 bool delayedResponse;
700 return TLB::translate(req, tc, NULL, mode, delayedResponse, false);
701}
702
703void
704TLB::translateTiming(RequestPtr req, ThreadContext *tc,
705 Translation *translation, Mode mode)
706{
707 bool delayedResponse;
708 assert(translation);
709 Fault fault =
710 TLB::translate(req, tc, translation, mode, delayedResponse, true);
711 if (!delayedResponse)
712 translation->finish(fault, req, tc, mode);
713}
714
715#if FULL_SYSTEM
716
717Tick
718TLB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
719{
720 return tc->getCpuPtr()->ticks(1);
721}
722
723Tick
724TLB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
725{
726 return tc->getCpuPtr()->ticks(1);
727}
728
729Walker *
730TLB::getWalker()
731{
732 return walker;
733}
734
735#endif
736
737void
738TLB::serialize(std::ostream &os)
739{
740}
741
742void
743TLB::unserialize(Checkpoint *cp, const std::string §ion)
744{
745}
746
747} // namespace X86ISA
748
749X86ISA::TLB *
750X86TLBParams::create()
751{
752 return new X86ISA::TLB(this);
753}
| 54#include "mem/packet_access.hh"
55#include "mem/request.hh"
56
57#if FULL_SYSTEM
58#include "arch/x86/pagetable_walker.hh"
59#else
60#include "mem/page_table.hh"
61#include "sim/process.hh"
62#endif
63
64namespace X86ISA {
65
66TLB::TLB(const Params *p) : BaseTLB(p), configAddress(0), size(p->size)
67{
68 tlb = new TlbEntry[size];
69 std::memset(tlb, 0, sizeof(TlbEntry) * size);
70
71 for (int x = 0; x < size; x++)
72 freeList.push_back(&tlb[x]);
73
74#if FULL_SYSTEM
75 walker = p->walker;
76 walker->setTLB(this);
77#endif
78}
79
80TlbEntry *
81TLB::insert(Addr vpn, TlbEntry &entry)
82{
83 //TODO Deal with conflicting entries
84
85 TlbEntry *newEntry = NULL;
86 if (!freeList.empty()) {
87 newEntry = freeList.front();
88 freeList.pop_front();
89 } else {
90 newEntry = entryList.back();
91 entryList.pop_back();
92 }
93 *newEntry = entry;
94 newEntry->vaddr = vpn;
95 entryList.push_front(newEntry);
96 return newEntry;
97}
98
99TLB::EntryList::iterator
100TLB::lookupIt(Addr va, bool update_lru)
101{
102 //TODO make this smarter at some point
103 EntryList::iterator entry;
104 for (entry = entryList.begin(); entry != entryList.end(); entry++) {
105 if ((*entry)->vaddr <= va && (*entry)->vaddr + (*entry)->size > va) {
106 DPRINTF(TLB, "Matched vaddr %#x to entry starting at %#x "
107 "with size %#x.\n", va, (*entry)->vaddr, (*entry)->size);
108 if (update_lru) {
109 entryList.push_front(*entry);
110 entryList.erase(entry);
111 entry = entryList.begin();
112 }
113 break;
114 }
115 }
116 return entry;
117}
118
119TlbEntry *
120TLB::lookup(Addr va, bool update_lru)
121{
122 EntryList::iterator entry = lookupIt(va, update_lru);
123 if (entry == entryList.end())
124 return NULL;
125 else
126 return *entry;
127}
128
129void
130TLB::invalidateAll()
131{
132 DPRINTF(TLB, "Invalidating all entries.\n");
133 while (!entryList.empty()) {
134 TlbEntry *entry = entryList.front();
135 entryList.pop_front();
136 freeList.push_back(entry);
137 }
138}
139
140void
141TLB::setConfigAddress(uint32_t addr)
142{
143 configAddress = addr;
144}
145
146void
147TLB::invalidateNonGlobal()
148{
149 DPRINTF(TLB, "Invalidating all non global entries.\n");
150 EntryList::iterator entryIt;
151 for (entryIt = entryList.begin(); entryIt != entryList.end();) {
152 if (!(*entryIt)->global) {
153 freeList.push_back(*entryIt);
154 entryList.erase(entryIt++);
155 } else {
156 entryIt++;
157 }
158 }
159}
160
161void
162TLB::demapPage(Addr va, uint64_t asn)
163{
164 EntryList::iterator entry = lookupIt(va, false);
165 if (entry != entryList.end()) {
166 freeList.push_back(*entry);
167 entryList.erase(entry);
168 }
169}
170
171Fault
172TLB::translateInt(RequestPtr req, ThreadContext *tc)
173{
174 DPRINTF(TLB, "Addresses references internal memory.\n");
175 Addr vaddr = req->getVaddr();
176 Addr prefix = (vaddr >> 3) & IntAddrPrefixMask;
177 if (prefix == IntAddrPrefixCPUID) {
178 panic("CPUID memory space not yet implemented!\n");
179 } else if (prefix == IntAddrPrefixMSR) {
180 vaddr = vaddr >> 3;
181 req->setFlags(Request::MMAPPED_IPR);
182 Addr regNum = 0;
183 switch (vaddr & ~IntAddrPrefixMask) {
184 case 0x10:
185 regNum = MISCREG_TSC;
186 break;
187 case 0x1B:
188 regNum = MISCREG_APIC_BASE;
189 break;
190 case 0xFE:
191 regNum = MISCREG_MTRRCAP;
192 break;
193 case 0x174:
194 regNum = MISCREG_SYSENTER_CS;
195 break;
196 case 0x175:
197 regNum = MISCREG_SYSENTER_ESP;
198 break;
199 case 0x176:
200 regNum = MISCREG_SYSENTER_EIP;
201 break;
202 case 0x179:
203 regNum = MISCREG_MCG_CAP;
204 break;
205 case 0x17A:
206 regNum = MISCREG_MCG_STATUS;
207 break;
208 case 0x17B:
209 regNum = MISCREG_MCG_CTL;
210 break;
211 case 0x1D9:
212 regNum = MISCREG_DEBUG_CTL_MSR;
213 break;
214 case 0x1DB:
215 regNum = MISCREG_LAST_BRANCH_FROM_IP;
216 break;
217 case 0x1DC:
218 regNum = MISCREG_LAST_BRANCH_TO_IP;
219 break;
220 case 0x1DD:
221 regNum = MISCREG_LAST_EXCEPTION_FROM_IP;
222 break;
223 case 0x1DE:
224 regNum = MISCREG_LAST_EXCEPTION_TO_IP;
225 break;
226 case 0x200:
227 regNum = MISCREG_MTRR_PHYS_BASE_0;
228 break;
229 case 0x201:
230 regNum = MISCREG_MTRR_PHYS_MASK_0;
231 break;
232 case 0x202:
233 regNum = MISCREG_MTRR_PHYS_BASE_1;
234 break;
235 case 0x203:
236 regNum = MISCREG_MTRR_PHYS_MASK_1;
237 break;
238 case 0x204:
239 regNum = MISCREG_MTRR_PHYS_BASE_2;
240 break;
241 case 0x205:
242 regNum = MISCREG_MTRR_PHYS_MASK_2;
243 break;
244 case 0x206:
245 regNum = MISCREG_MTRR_PHYS_BASE_3;
246 break;
247 case 0x207:
248 regNum = MISCREG_MTRR_PHYS_MASK_3;
249 break;
250 case 0x208:
251 regNum = MISCREG_MTRR_PHYS_BASE_4;
252 break;
253 case 0x209:
254 regNum = MISCREG_MTRR_PHYS_MASK_4;
255 break;
256 case 0x20A:
257 regNum = MISCREG_MTRR_PHYS_BASE_5;
258 break;
259 case 0x20B:
260 regNum = MISCREG_MTRR_PHYS_MASK_5;
261 break;
262 case 0x20C:
263 regNum = MISCREG_MTRR_PHYS_BASE_6;
264 break;
265 case 0x20D:
266 regNum = MISCREG_MTRR_PHYS_MASK_6;
267 break;
268 case 0x20E:
269 regNum = MISCREG_MTRR_PHYS_BASE_7;
270 break;
271 case 0x20F:
272 regNum = MISCREG_MTRR_PHYS_MASK_7;
273 break;
274 case 0x250:
275 regNum = MISCREG_MTRR_FIX_64K_00000;
276 break;
277 case 0x258:
278 regNum = MISCREG_MTRR_FIX_16K_80000;
279 break;
280 case 0x259:
281 regNum = MISCREG_MTRR_FIX_16K_A0000;
282 break;
283 case 0x268:
284 regNum = MISCREG_MTRR_FIX_4K_C0000;
285 break;
286 case 0x269:
287 regNum = MISCREG_MTRR_FIX_4K_C8000;
288 break;
289 case 0x26A:
290 regNum = MISCREG_MTRR_FIX_4K_D0000;
291 break;
292 case 0x26B:
293 regNum = MISCREG_MTRR_FIX_4K_D8000;
294 break;
295 case 0x26C:
296 regNum = MISCREG_MTRR_FIX_4K_E0000;
297 break;
298 case 0x26D:
299 regNum = MISCREG_MTRR_FIX_4K_E8000;
300 break;
301 case 0x26E:
302 regNum = MISCREG_MTRR_FIX_4K_F0000;
303 break;
304 case 0x26F:
305 regNum = MISCREG_MTRR_FIX_4K_F8000;
306 break;
307 case 0x277:
308 regNum = MISCREG_PAT;
309 break;
310 case 0x2FF:
311 regNum = MISCREG_DEF_TYPE;
312 break;
313 case 0x400:
314 regNum = MISCREG_MC0_CTL;
315 break;
316 case 0x404:
317 regNum = MISCREG_MC1_CTL;
318 break;
319 case 0x408:
320 regNum = MISCREG_MC2_CTL;
321 break;
322 case 0x40C:
323 regNum = MISCREG_MC3_CTL;
324 break;
325 case 0x410:
326 regNum = MISCREG_MC4_CTL;
327 break;
328 case 0x414:
329 regNum = MISCREG_MC5_CTL;
330 break;
331 case 0x418:
332 regNum = MISCREG_MC6_CTL;
333 break;
334 case 0x41C:
335 regNum = MISCREG_MC7_CTL;
336 break;
337 case 0x401:
338 regNum = MISCREG_MC0_STATUS;
339 break;
340 case 0x405:
341 regNum = MISCREG_MC1_STATUS;
342 break;
343 case 0x409:
344 regNum = MISCREG_MC2_STATUS;
345 break;
346 case 0x40D:
347 regNum = MISCREG_MC3_STATUS;
348 break;
349 case 0x411:
350 regNum = MISCREG_MC4_STATUS;
351 break;
352 case 0x415:
353 regNum = MISCREG_MC5_STATUS;
354 break;
355 case 0x419:
356 regNum = MISCREG_MC6_STATUS;
357 break;
358 case 0x41D:
359 regNum = MISCREG_MC7_STATUS;
360 break;
361 case 0x402:
362 regNum = MISCREG_MC0_ADDR;
363 break;
364 case 0x406:
365 regNum = MISCREG_MC1_ADDR;
366 break;
367 case 0x40A:
368 regNum = MISCREG_MC2_ADDR;
369 break;
370 case 0x40E:
371 regNum = MISCREG_MC3_ADDR;
372 break;
373 case 0x412:
374 regNum = MISCREG_MC4_ADDR;
375 break;
376 case 0x416:
377 regNum = MISCREG_MC5_ADDR;
378 break;
379 case 0x41A:
380 regNum = MISCREG_MC6_ADDR;
381 break;
382 case 0x41E:
383 regNum = MISCREG_MC7_ADDR;
384 break;
385 case 0x403:
386 regNum = MISCREG_MC0_MISC;
387 break;
388 case 0x407:
389 regNum = MISCREG_MC1_MISC;
390 break;
391 case 0x40B:
392 regNum = MISCREG_MC2_MISC;
393 break;
394 case 0x40F:
395 regNum = MISCREG_MC3_MISC;
396 break;
397 case 0x413:
398 regNum = MISCREG_MC4_MISC;
399 break;
400 case 0x417:
401 regNum = MISCREG_MC5_MISC;
402 break;
403 case 0x41B:
404 regNum = MISCREG_MC6_MISC;
405 break;
406 case 0x41F:
407 regNum = MISCREG_MC7_MISC;
408 break;
409 case 0xC0000080:
410 regNum = MISCREG_EFER;
411 break;
412 case 0xC0000081:
413 regNum = MISCREG_STAR;
414 break;
415 case 0xC0000082:
416 regNum = MISCREG_LSTAR;
417 break;
418 case 0xC0000083:
419 regNum = MISCREG_CSTAR;
420 break;
421 case 0xC0000084:
422 regNum = MISCREG_SF_MASK;
423 break;
424 case 0xC0000100:
425 regNum = MISCREG_FS_BASE;
426 break;
427 case 0xC0000101:
428 regNum = MISCREG_GS_BASE;
429 break;
430 case 0xC0000102:
431 regNum = MISCREG_KERNEL_GS_BASE;
432 break;
433 case 0xC0000103:
434 regNum = MISCREG_TSC_AUX;
435 break;
436 case 0xC0010000:
437 regNum = MISCREG_PERF_EVT_SEL0;
438 break;
439 case 0xC0010001:
440 regNum = MISCREG_PERF_EVT_SEL1;
441 break;
442 case 0xC0010002:
443 regNum = MISCREG_PERF_EVT_SEL2;
444 break;
445 case 0xC0010003:
446 regNum = MISCREG_PERF_EVT_SEL3;
447 break;
448 case 0xC0010004:
449 regNum = MISCREG_PERF_EVT_CTR0;
450 break;
451 case 0xC0010005:
452 regNum = MISCREG_PERF_EVT_CTR1;
453 break;
454 case 0xC0010006:
455 regNum = MISCREG_PERF_EVT_CTR2;
456 break;
457 case 0xC0010007:
458 regNum = MISCREG_PERF_EVT_CTR3;
459 break;
460 case 0xC0010010:
461 regNum = MISCREG_SYSCFG;
462 break;
463 case 0xC0010016:
464 regNum = MISCREG_IORR_BASE0;
465 break;
466 case 0xC0010017:
467 regNum = MISCREG_IORR_BASE1;
468 break;
469 case 0xC0010018:
470 regNum = MISCREG_IORR_MASK0;
471 break;
472 case 0xC0010019:
473 regNum = MISCREG_IORR_MASK1;
474 break;
475 case 0xC001001A:
476 regNum = MISCREG_TOP_MEM;
477 break;
478 case 0xC001001D:
479 regNum = MISCREG_TOP_MEM2;
480 break;
481 case 0xC0010114:
482 regNum = MISCREG_VM_CR;
483 break;
484 case 0xC0010115:
485 regNum = MISCREG_IGNNE;
486 break;
487 case 0xC0010116:
488 regNum = MISCREG_SMM_CTL;
489 break;
490 case 0xC0010117:
491 regNum = MISCREG_VM_HSAVE_PA;
492 break;
493 default:
494 return new GeneralProtection(0);
495 }
496 //The index is multiplied by the size of a MiscReg so that
497 //any memory dependence calculations will not see these as
498 //overlapping.
499 req->setPaddr(regNum * sizeof(MiscReg));
500 return NoFault;
501 } else if (prefix == IntAddrPrefixIO) {
502 // TODO If CPL > IOPL or in virtual mode, check the I/O permission
503 // bitmap in the TSS.
504
505 Addr IOPort = vaddr & ~IntAddrPrefixMask;
506 // Make sure the address fits in the expected 16 bit IO address
507 // space.
508 assert(!(IOPort & ~0xFFFF));
509 if (IOPort == 0xCF8 && req->getSize() == 4) {
510 req->setFlags(Request::MMAPPED_IPR);
511 req->setPaddr(MISCREG_PCI_CONFIG_ADDRESS * sizeof(MiscReg));
512 } else if ((IOPort & ~mask(2)) == 0xCFC) {
513 req->setFlags(Request::UNCACHEABLE);
514 Addr configAddress =
515 tc->readMiscRegNoEffect(MISCREG_PCI_CONFIG_ADDRESS);
516 if (bits(configAddress, 31, 31)) {
517 req->setPaddr(PhysAddrPrefixPciConfig |
518 mbits(configAddress, 30, 2) |
519 (IOPort & mask(2)));
520 } else {
521 req->setPaddr(PhysAddrPrefixIO | IOPort);
522 }
523 } else {
524 req->setFlags(Request::UNCACHEABLE);
525 req->setPaddr(PhysAddrPrefixIO | IOPort);
526 }
527 return NoFault;
528 } else {
529 panic("Access to unrecognized internal address space %#x.\n",
530 prefix);
531 }
532}
533
534Fault
535TLB::translate(RequestPtr req, ThreadContext *tc, Translation *translation,
536 Mode mode, bool &delayedResponse, bool timing)
537{
538 uint32_t flags = req->getFlags();
539 int seg = flags & SegmentFlagMask;
540 bool storeCheck = flags & (StoreCheck << FlagShift);
541
542 // If this is true, we're dealing with a request to a non-memory address
543 // space.
544 if (seg == SEGMENT_REG_MS) {
545 return translateInt(req, tc);
546 }
547
548 delayedResponse = false;
549 Addr vaddr = req->getVaddr();
550 DPRINTF(TLB, "Translating vaddr %#x.\n", vaddr);
551
552 HandyM5Reg m5Reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
553
554 // If protected mode has been enabled...
555 if (m5Reg.prot) {
556 DPRINTF(TLB, "In protected mode.\n");
557 // If we're not in 64-bit mode, do protection/limit checks
558 if (m5Reg.mode != LongMode) {
559 DPRINTF(TLB, "Not in long mode. Checking segment protection.\n");
560 // Check for a NULL segment selector.
561 if (!(seg == SEGMENT_REG_TSG || seg == SYS_SEGMENT_REG_IDTR ||
562 seg == SEGMENT_REG_HS || seg == SEGMENT_REG_LS)
563 && !tc->readMiscRegNoEffect(MISCREG_SEG_SEL(seg)))
564 return new GeneralProtection(0);
565 bool expandDown = false;
566 SegAttr attr = tc->readMiscRegNoEffect(MISCREG_SEG_ATTR(seg));
567 if (seg >= SEGMENT_REG_ES && seg <= SEGMENT_REG_HS) {
568 if (!attr.writable && (mode == Write || storeCheck))
569 return new GeneralProtection(0);
570 if (!attr.readable && mode == Read)
571 return new GeneralProtection(0);
572 expandDown = attr.expandDown;
573
574 }
575 Addr base = tc->readMiscRegNoEffect(MISCREG_SEG_BASE(seg));
576 Addr limit = tc->readMiscRegNoEffect(MISCREG_SEG_LIMIT(seg));
577 // This assumes we're not in 64 bit mode. If we were, the default
578 // address size is 64 bits, overridable to 32.
579 int size = 32;
580 bool sizeOverride = (flags & (AddrSizeFlagBit << FlagShift));
581 SegAttr csAttr = tc->readMiscRegNoEffect(MISCREG_CS_ATTR);
582 if ((csAttr.defaultSize && sizeOverride) ||
583 (!csAttr.defaultSize && !sizeOverride))
584 size = 16;
585 Addr offset = bits(vaddr - base, size-1, 0);
586 Addr endOffset = offset + req->getSize() - 1;
587 if (expandDown) {
588 DPRINTF(TLB, "Checking an expand down segment.\n");
589 warn_once("Expand down segments are untested.\n");
590 if (offset <= limit || endOffset <= limit)
591 return new GeneralProtection(0);
592 } else {
593 if (offset > limit || endOffset > limit)
594 return new GeneralProtection(0);
595 }
596 }
597 // If paging is enabled, do the translation.
598 if (m5Reg.paging) {
599 DPRINTF(TLB, "Paging enabled.\n");
600 // The vaddr already has the segment base applied.
601 TlbEntry *entry = lookup(vaddr);
602 if (!entry) {
603#if FULL_SYSTEM
604 Fault fault = walker->start(tc, translation, req, mode);
605 if (timing || fault != NoFault) {
606 // This gets ignored in atomic mode.
607 delayedResponse = true;
608 return fault;
609 }
610 entry = lookup(vaddr);
611 assert(entry);
612#else
613 DPRINTF(TLB, "Handling a TLB miss for "
614 "address %#x at pc %#x.\n",
615 vaddr, tc->instAddr());
616
617 Process *p = tc->getProcessPtr();
618 TlbEntry newEntry;
619 bool success = p->pTable->lookup(vaddr, newEntry);
620 if (!success && mode != Execute) {
621 p->checkAndAllocNextPage(vaddr);
622 success = p->pTable->lookup(vaddr, newEntry);
623 }
624 if (!success) {
625 return new PageFault(vaddr, true, mode, true, false);
626 } else {
627 Addr alignedVaddr = p->pTable->pageAlign(vaddr);
628 DPRINTF(TLB, "Mapping %#x to %#x\n", alignedVaddr,
629 newEntry.pageStart());
630 entry = insert(alignedVaddr, newEntry);
631 }
632 DPRINTF(TLB, "Miss was serviced.\n");
633#endif
634 }
635 // Do paging protection checks.
636 bool inUser = (m5Reg.cpl == 3 &&
637 !(flags & (CPL0FlagBit << FlagShift)));
638 CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0);
639 bool badWrite = (!entry->writable && (inUser || cr0.wp));
640 if ((inUser && !entry->user) || (mode == Write && badWrite)) {
641 // The page must have been present to get into the TLB in
642 // the first place. We'll assume the reserved bits are
643 // fine even though we're not checking them.
644 return new PageFault(vaddr, true, mode, inUser, false);
645 }
646 if (storeCheck && badWrite) {
647 // This would fault if this were a write, so return a page
648 // fault that reflects that happening.
649 return new PageFault(vaddr, true, Write, inUser, false);
650 }
651
652
653 DPRINTF(TLB, "Entry found with paddr %#x, "
654 "doing protection checks.\n", entry->paddr);
655 Addr paddr = entry->paddr | (vaddr & (entry->size-1));
656 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, paddr);
657 req->setPaddr(paddr);
658 if (entry->uncacheable)
659 req->setFlags(Request::UNCACHEABLE);
660 } else {
661 //Use the address which already has segmentation applied.
662 DPRINTF(TLB, "Paging disabled.\n");
663 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr);
664 req->setPaddr(vaddr);
665 }
666 } else {
667 // Real mode
668 DPRINTF(TLB, "In real mode.\n");
669 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr);
670 req->setPaddr(vaddr);
671 }
672 // Check for an access to the local APIC
673#if FULL_SYSTEM
674 LocalApicBase localApicBase = tc->readMiscRegNoEffect(MISCREG_APIC_BASE);
675 Addr baseAddr = localApicBase.base * PageBytes;
676 Addr paddr = req->getPaddr();
677 if (baseAddr <= paddr && baseAddr + PageBytes > paddr) {
678 // The Intel developer's manuals say the below restrictions apply,
679 // but the linux kernel, because of a compiler optimization, breaks
680 // them.
681 /*
682 // Check alignment
683 if (paddr & ((32/8) - 1))
684 return new GeneralProtection(0);
685 // Check access size
686 if (req->getSize() != (32/8))
687 return new GeneralProtection(0);
688 */
689 // Force the access to be uncacheable.
690 req->setFlags(Request::UNCACHEABLE);
691 req->setPaddr(x86LocalAPICAddress(tc->contextId(), paddr - baseAddr));
692 }
693#endif
694 return NoFault;
695};
696
697Fault
698TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
699{
700 bool delayedResponse;
701 return TLB::translate(req, tc, NULL, mode, delayedResponse, false);
702}
703
704void
705TLB::translateTiming(RequestPtr req, ThreadContext *tc,
706 Translation *translation, Mode mode)
707{
708 bool delayedResponse;
709 assert(translation);
710 Fault fault =
711 TLB::translate(req, tc, translation, mode, delayedResponse, true);
712 if (!delayedResponse)
713 translation->finish(fault, req, tc, mode);
714}
715
716#if FULL_SYSTEM
717
718Tick
719TLB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
720{
721 return tc->getCpuPtr()->ticks(1);
722}
723
724Tick
725TLB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
726{
727 return tc->getCpuPtr()->ticks(1);
728}
729
730Walker *
731TLB::getWalker()
732{
733 return walker;
734}
735
736#endif
737
738void
739TLB::serialize(std::ostream &os)
740{
741}
742
743void
744TLB::unserialize(Checkpoint *cp, const std::string §ion)
745{
746}
747
748} // namespace X86ISA
749
750X86ISA::TLB *
751X86TLBParams::create()
752{
753 return new X86ISA::TLB(this);
754}
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