1/* 2 * Copyright (c) 2007-2008 The Hewlett-Packard Development Company 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Gabe Black 38 */ 39 40#include <cstring> 41 42#include "config/full_system.hh" 43 44#include "arch/x86/faults.hh" 45#include "arch/x86/insts/microldstop.hh" 46#include "arch/x86/pagetable.hh" 47#include "arch/x86/regs/misc.hh" 48#include "arch/x86/tlb.hh" 49#include "arch/x86/x86_traits.hh" 50#include "base/bitfield.hh" 51#include "base/trace.hh" 52#include "config/full_system.hh" 53#include "cpu/thread_context.hh" 54#include "cpu/base.hh" 55#include "mem/packet_access.hh" 56#include "mem/request.hh" 57 58#if FULL_SYSTEM 59#include "arch/x86/pagetable_walker.hh" 60#else 61#include "mem/page_table.hh" 62#include "sim/process.hh" 63#endif 64 65namespace X86ISA { 66 67TLB::TLB(const Params *p) : BaseTLB(p), configAddress(0), size(p->size) 68{ 69 tlb = new TlbEntry[size]; 70 std::memset(tlb, 0, sizeof(TlbEntry) * size); 71 72 for (int x = 0; x < size; x++) 73 freeList.push_back(&tlb[x]); 74 75#if FULL_SYSTEM 76 walker = p->walker; 77 walker->setTLB(this); 78#endif 79} 80 81TlbEntry * 82TLB::insert(Addr vpn, TlbEntry &entry) 83{ 84 //TODO Deal with conflicting entries 85 86 TlbEntry *newEntry = NULL; 87 if (!freeList.empty()) { 88 newEntry = freeList.front(); 89 freeList.pop_front(); 90 } else { 91 newEntry = entryList.back(); 92 entryList.pop_back(); 93 } 94 *newEntry = entry; 95 newEntry->vaddr = vpn; 96 entryList.push_front(newEntry); 97 return newEntry; 98} 99 100TLB::EntryList::iterator 101TLB::lookupIt(Addr va, bool update_lru) 102{ 103 //TODO make this smarter at some point 104 EntryList::iterator entry; 105 for (entry = entryList.begin(); entry != entryList.end(); entry++) { 106 if ((*entry)->vaddr <= va && (*entry)->vaddr + (*entry)->size > va) { 107 DPRINTF(TLB, "Matched vaddr %#x to entry starting at %#x " 108 "with size %#x.\n", va, (*entry)->vaddr, (*entry)->size); 109 if (update_lru) { 110 entryList.push_front(*entry); 111 entryList.erase(entry); 112 entry = entryList.begin(); 113 } 114 break; 115 } 116 } 117 return entry; 118} 119 120TlbEntry * 121TLB::lookup(Addr va, bool update_lru) 122{ 123 EntryList::iterator entry = lookupIt(va, update_lru); 124 if (entry == entryList.end()) 125 return NULL; 126 else 127 return *entry; 128} 129 130void 131TLB::invalidateAll() 132{ 133 DPRINTF(TLB, "Invalidating all entries.\n"); 134 while (!entryList.empty()) { 135 TlbEntry *entry = entryList.front(); 136 entryList.pop_front(); 137 freeList.push_back(entry); 138 } 139} 140 141void 142TLB::setConfigAddress(uint32_t addr) 143{ 144 configAddress = addr; 145} 146 147void 148TLB::invalidateNonGlobal() 149{ 150 DPRINTF(TLB, "Invalidating all non global entries.\n"); 151 EntryList::iterator entryIt; 152 for (entryIt = entryList.begin(); entryIt != entryList.end();) { 153 if (!(*entryIt)->global) { 154 freeList.push_back(*entryIt); 155 entryList.erase(entryIt++); 156 } else { 157 entryIt++; 158 } 159 } 160} 161 162void 163TLB::demapPage(Addr va, uint64_t asn) 164{ 165 EntryList::iterator entry = lookupIt(va, false); 166 if (entry != entryList.end()) { 167 freeList.push_back(*entry); 168 entryList.erase(entry); 169 } 170} 171 172Fault 173TLB::translateInt(RequestPtr req, ThreadContext *tc) 174{ 175 DPRINTF(TLB, "Addresses references internal memory.\n"); 176 Addr vaddr = req->getVaddr(); 177 Addr prefix = (vaddr >> 3) & IntAddrPrefixMask; 178 if (prefix == IntAddrPrefixCPUID) { 179 panic("CPUID memory space not yet implemented!\n"); 180 } else if (prefix == IntAddrPrefixMSR) { 181 vaddr = vaddr >> 3;
| 1/* 2 * Copyright (c) 2007-2008 The Hewlett-Packard Development Company 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Gabe Black 38 */ 39 40#include <cstring> 41 42#include "config/full_system.hh" 43 44#include "arch/x86/faults.hh" 45#include "arch/x86/insts/microldstop.hh" 46#include "arch/x86/pagetable.hh" 47#include "arch/x86/regs/misc.hh" 48#include "arch/x86/tlb.hh" 49#include "arch/x86/x86_traits.hh" 50#include "base/bitfield.hh" 51#include "base/trace.hh" 52#include "config/full_system.hh" 53#include "cpu/thread_context.hh" 54#include "cpu/base.hh" 55#include "mem/packet_access.hh" 56#include "mem/request.hh" 57 58#if FULL_SYSTEM 59#include "arch/x86/pagetable_walker.hh" 60#else 61#include "mem/page_table.hh" 62#include "sim/process.hh" 63#endif 64 65namespace X86ISA { 66 67TLB::TLB(const Params *p) : BaseTLB(p), configAddress(0), size(p->size) 68{ 69 tlb = new TlbEntry[size]; 70 std::memset(tlb, 0, sizeof(TlbEntry) * size); 71 72 for (int x = 0; x < size; x++) 73 freeList.push_back(&tlb[x]); 74 75#if FULL_SYSTEM 76 walker = p->walker; 77 walker->setTLB(this); 78#endif 79} 80 81TlbEntry * 82TLB::insert(Addr vpn, TlbEntry &entry) 83{ 84 //TODO Deal with conflicting entries 85 86 TlbEntry *newEntry = NULL; 87 if (!freeList.empty()) { 88 newEntry = freeList.front(); 89 freeList.pop_front(); 90 } else { 91 newEntry = entryList.back(); 92 entryList.pop_back(); 93 } 94 *newEntry = entry; 95 newEntry->vaddr = vpn; 96 entryList.push_front(newEntry); 97 return newEntry; 98} 99 100TLB::EntryList::iterator 101TLB::lookupIt(Addr va, bool update_lru) 102{ 103 //TODO make this smarter at some point 104 EntryList::iterator entry; 105 for (entry = entryList.begin(); entry != entryList.end(); entry++) { 106 if ((*entry)->vaddr <= va && (*entry)->vaddr + (*entry)->size > va) { 107 DPRINTF(TLB, "Matched vaddr %#x to entry starting at %#x " 108 "with size %#x.\n", va, (*entry)->vaddr, (*entry)->size); 109 if (update_lru) { 110 entryList.push_front(*entry); 111 entryList.erase(entry); 112 entry = entryList.begin(); 113 } 114 break; 115 } 116 } 117 return entry; 118} 119 120TlbEntry * 121TLB::lookup(Addr va, bool update_lru) 122{ 123 EntryList::iterator entry = lookupIt(va, update_lru); 124 if (entry == entryList.end()) 125 return NULL; 126 else 127 return *entry; 128} 129 130void 131TLB::invalidateAll() 132{ 133 DPRINTF(TLB, "Invalidating all entries.\n"); 134 while (!entryList.empty()) { 135 TlbEntry *entry = entryList.front(); 136 entryList.pop_front(); 137 freeList.push_back(entry); 138 } 139} 140 141void 142TLB::setConfigAddress(uint32_t addr) 143{ 144 configAddress = addr; 145} 146 147void 148TLB::invalidateNonGlobal() 149{ 150 DPRINTF(TLB, "Invalidating all non global entries.\n"); 151 EntryList::iterator entryIt; 152 for (entryIt = entryList.begin(); entryIt != entryList.end();) { 153 if (!(*entryIt)->global) { 154 freeList.push_back(*entryIt); 155 entryList.erase(entryIt++); 156 } else { 157 entryIt++; 158 } 159 } 160} 161 162void 163TLB::demapPage(Addr va, uint64_t asn) 164{ 165 EntryList::iterator entry = lookupIt(va, false); 166 if (entry != entryList.end()) { 167 freeList.push_back(*entry); 168 entryList.erase(entry); 169 } 170} 171 172Fault 173TLB::translateInt(RequestPtr req, ThreadContext *tc) 174{ 175 DPRINTF(TLB, "Addresses references internal memory.\n"); 176 Addr vaddr = req->getVaddr(); 177 Addr prefix = (vaddr >> 3) & IntAddrPrefixMask; 178 if (prefix == IntAddrPrefixCPUID) { 179 panic("CPUID memory space not yet implemented!\n"); 180 } else if (prefix == IntAddrPrefixMSR) { 181 vaddr = vaddr >> 3;
|
512 req->setPaddr(MISCREG_PCI_CONFIG_ADDRESS * sizeof(MiscReg)); 513 } else if ((IOPort & ~mask(2)) == 0xCFC) { 514 req->setFlags(Request::UNCACHEABLE); 515 Addr configAddress = 516 tc->readMiscRegNoEffect(MISCREG_PCI_CONFIG_ADDRESS); 517 if (bits(configAddress, 31, 31)) { 518 req->setPaddr(PhysAddrPrefixPciConfig | 519 mbits(configAddress, 30, 2) | 520 (IOPort & mask(2))); 521 } else { 522 req->setPaddr(PhysAddrPrefixIO | IOPort); 523 } 524 } else { 525 req->setFlags(Request::UNCACHEABLE); 526 req->setPaddr(PhysAddrPrefixIO | IOPort); 527 } 528 return NoFault; 529 } else { 530 panic("Access to unrecognized internal address space %#x.\n", 531 prefix); 532 } 533} 534 535Fault 536TLB::translate(RequestPtr req, ThreadContext *tc, Translation *translation, 537 Mode mode, bool &delayedResponse, bool timing) 538{ 539 uint32_t flags = req->getFlags(); 540 int seg = flags & SegmentFlagMask; 541 bool storeCheck = flags & (StoreCheck << FlagShift); 542 543 // If this is true, we're dealing with a request to a non-memory address 544 // space. 545 if (seg == SEGMENT_REG_MS) { 546 return translateInt(req, tc); 547 } 548 549 delayedResponse = false; 550 Addr vaddr = req->getVaddr(); 551 DPRINTF(TLB, "Translating vaddr %#x.\n", vaddr); 552 553 HandyM5Reg m5Reg = tc->readMiscRegNoEffect(MISCREG_M5_REG); 554 555 // If protected mode has been enabled... 556 if (m5Reg.prot) { 557 DPRINTF(TLB, "In protected mode.\n"); 558 // If we're not in 64-bit mode, do protection/limit checks 559 if (m5Reg.mode != LongMode) { 560 DPRINTF(TLB, "Not in long mode. Checking segment protection.\n"); 561 // Check for a NULL segment selector. 562 if (!(seg == SEGMENT_REG_TSG || seg == SYS_SEGMENT_REG_IDTR || 563 seg == SEGMENT_REG_HS || seg == SEGMENT_REG_LS) 564 && !tc->readMiscRegNoEffect(MISCREG_SEG_SEL(seg))) 565 return new GeneralProtection(0); 566 bool expandDown = false; 567 SegAttr attr = tc->readMiscRegNoEffect(MISCREG_SEG_ATTR(seg)); 568 if (seg >= SEGMENT_REG_ES && seg <= SEGMENT_REG_HS) { 569 if (!attr.writable && (mode == Write || storeCheck)) 570 return new GeneralProtection(0); 571 if (!attr.readable && mode == Read) 572 return new GeneralProtection(0); 573 expandDown = attr.expandDown; 574 575 } 576 Addr base = tc->readMiscRegNoEffect(MISCREG_SEG_BASE(seg)); 577 Addr limit = tc->readMiscRegNoEffect(MISCREG_SEG_LIMIT(seg)); 578 // This assumes we're not in 64 bit mode. If we were, the default 579 // address size is 64 bits, overridable to 32. 580 int size = 32; 581 bool sizeOverride = (flags & (AddrSizeFlagBit << FlagShift)); 582 SegAttr csAttr = tc->readMiscRegNoEffect(MISCREG_CS_ATTR); 583 if ((csAttr.defaultSize && sizeOverride) || 584 (!csAttr.defaultSize && !sizeOverride)) 585 size = 16; 586 Addr offset = bits(vaddr - base, size-1, 0); 587 Addr endOffset = offset + req->getSize() - 1; 588 if (expandDown) { 589 DPRINTF(TLB, "Checking an expand down segment.\n"); 590 warn_once("Expand down segments are untested.\n"); 591 if (offset <= limit || endOffset <= limit) 592 return new GeneralProtection(0); 593 } else { 594 if (offset > limit || endOffset > limit) 595 return new GeneralProtection(0); 596 } 597 } 598 // If paging is enabled, do the translation. 599 if (m5Reg.paging) { 600 DPRINTF(TLB, "Paging enabled.\n"); 601 // The vaddr already has the segment base applied. 602 TlbEntry *entry = lookup(vaddr); 603 if (!entry) { 604#if FULL_SYSTEM 605 Fault fault = walker->start(tc, translation, req, mode); 606 if (timing || fault != NoFault) { 607 // This gets ignored in atomic mode. 608 delayedResponse = true; 609 return fault; 610 } 611 entry = lookup(vaddr); 612 assert(entry); 613#else 614 DPRINTF(TLB, "Handling a TLB miss for " 615 "address %#x at pc %#x.\n", 616 vaddr, tc->instAddr()); 617 618 Process *p = tc->getProcessPtr(); 619 TlbEntry newEntry; 620 bool success = p->pTable->lookup(vaddr, newEntry); 621 if (!success && mode != Execute) { 622 p->checkAndAllocNextPage(vaddr); 623 success = p->pTable->lookup(vaddr, newEntry); 624 } 625 if (!success) { 626 return new PageFault(vaddr, true, mode, true, false); 627 } else { 628 Addr alignedVaddr = p->pTable->pageAlign(vaddr); 629 DPRINTF(TLB, "Mapping %#x to %#x\n", alignedVaddr, 630 newEntry.pageStart()); 631 entry = insert(alignedVaddr, newEntry); 632 } 633 DPRINTF(TLB, "Miss was serviced.\n"); 634#endif 635 } 636 // Do paging protection checks. 637 bool inUser = (m5Reg.cpl == 3 && 638 !(flags & (CPL0FlagBit << FlagShift))); 639 CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0); 640 bool badWrite = (!entry->writable && (inUser || cr0.wp)); 641 if ((inUser && !entry->user) || (mode == Write && badWrite)) { 642 // The page must have been present to get into the TLB in 643 // the first place. We'll assume the reserved bits are 644 // fine even though we're not checking them. 645 return new PageFault(vaddr, true, mode, inUser, false); 646 } 647 if (storeCheck && badWrite) { 648 // This would fault if this were a write, so return a page 649 // fault that reflects that happening. 650 return new PageFault(vaddr, true, Write, inUser, false); 651 } 652 653 654 DPRINTF(TLB, "Entry found with paddr %#x, " 655 "doing protection checks.\n", entry->paddr); 656 Addr paddr = entry->paddr | (vaddr & (entry->size-1)); 657 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, paddr); 658 req->setPaddr(paddr); 659 if (entry->uncacheable) 660 req->setFlags(Request::UNCACHEABLE); 661 } else { 662 //Use the address which already has segmentation applied. 663 DPRINTF(TLB, "Paging disabled.\n"); 664 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr); 665 req->setPaddr(vaddr); 666 } 667 } else { 668 // Real mode 669 DPRINTF(TLB, "In real mode.\n"); 670 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr); 671 req->setPaddr(vaddr); 672 } 673 // Check for an access to the local APIC 674#if FULL_SYSTEM 675 LocalApicBase localApicBase = tc->readMiscRegNoEffect(MISCREG_APIC_BASE); 676 Addr baseAddr = localApicBase.base * PageBytes; 677 Addr paddr = req->getPaddr(); 678 if (baseAddr <= paddr && baseAddr + PageBytes > paddr) { 679 // The Intel developer's manuals say the below restrictions apply, 680 // but the linux kernel, because of a compiler optimization, breaks 681 // them. 682 /* 683 // Check alignment 684 if (paddr & ((32/8) - 1)) 685 return new GeneralProtection(0); 686 // Check access size 687 if (req->getSize() != (32/8)) 688 return new GeneralProtection(0); 689 */ 690 // Force the access to be uncacheable. 691 req->setFlags(Request::UNCACHEABLE); 692 req->setPaddr(x86LocalAPICAddress(tc->contextId(), paddr - baseAddr)); 693 } 694#endif 695 return NoFault; 696}; 697 698Fault 699TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode) 700{ 701 bool delayedResponse; 702 return TLB::translate(req, tc, NULL, mode, delayedResponse, false); 703} 704 705void 706TLB::translateTiming(RequestPtr req, ThreadContext *tc, 707 Translation *translation, Mode mode) 708{ 709 bool delayedResponse; 710 assert(translation); 711 Fault fault = 712 TLB::translate(req, tc, translation, mode, delayedResponse, true); 713 if (!delayedResponse) 714 translation->finish(fault, req, tc, mode); 715} 716 717#if FULL_SYSTEM 718 719Tick 720TLB::doMmuRegRead(ThreadContext *tc, Packet *pkt) 721{ 722 return tc->getCpuPtr()->ticks(1); 723} 724 725Tick 726TLB::doMmuRegWrite(ThreadContext *tc, Packet *pkt) 727{ 728 return tc->getCpuPtr()->ticks(1); 729} 730 731Walker * 732TLB::getWalker() 733{ 734 return walker; 735} 736 737#endif 738 739void 740TLB::serialize(std::ostream &os) 741{ 742} 743 744void 745TLB::unserialize(Checkpoint *cp, const std::string §ion) 746{ 747} 748 749} // namespace X86ISA 750 751X86ISA::TLB * 752X86TLBParams::create() 753{ 754 return new X86ISA::TLB(this); 755}
| 512 req->setPaddr(MISCREG_PCI_CONFIG_ADDRESS * sizeof(MiscReg)); 513 } else if ((IOPort & ~mask(2)) == 0xCFC) { 514 req->setFlags(Request::UNCACHEABLE); 515 Addr configAddress = 516 tc->readMiscRegNoEffect(MISCREG_PCI_CONFIG_ADDRESS); 517 if (bits(configAddress, 31, 31)) { 518 req->setPaddr(PhysAddrPrefixPciConfig | 519 mbits(configAddress, 30, 2) | 520 (IOPort & mask(2))); 521 } else { 522 req->setPaddr(PhysAddrPrefixIO | IOPort); 523 } 524 } else { 525 req->setFlags(Request::UNCACHEABLE); 526 req->setPaddr(PhysAddrPrefixIO | IOPort); 527 } 528 return NoFault; 529 } else { 530 panic("Access to unrecognized internal address space %#x.\n", 531 prefix); 532 } 533} 534 535Fault 536TLB::translate(RequestPtr req, ThreadContext *tc, Translation *translation, 537 Mode mode, bool &delayedResponse, bool timing) 538{ 539 uint32_t flags = req->getFlags(); 540 int seg = flags & SegmentFlagMask; 541 bool storeCheck = flags & (StoreCheck << FlagShift); 542 543 // If this is true, we're dealing with a request to a non-memory address 544 // space. 545 if (seg == SEGMENT_REG_MS) { 546 return translateInt(req, tc); 547 } 548 549 delayedResponse = false; 550 Addr vaddr = req->getVaddr(); 551 DPRINTF(TLB, "Translating vaddr %#x.\n", vaddr); 552 553 HandyM5Reg m5Reg = tc->readMiscRegNoEffect(MISCREG_M5_REG); 554 555 // If protected mode has been enabled... 556 if (m5Reg.prot) { 557 DPRINTF(TLB, "In protected mode.\n"); 558 // If we're not in 64-bit mode, do protection/limit checks 559 if (m5Reg.mode != LongMode) { 560 DPRINTF(TLB, "Not in long mode. Checking segment protection.\n"); 561 // Check for a NULL segment selector. 562 if (!(seg == SEGMENT_REG_TSG || seg == SYS_SEGMENT_REG_IDTR || 563 seg == SEGMENT_REG_HS || seg == SEGMENT_REG_LS) 564 && !tc->readMiscRegNoEffect(MISCREG_SEG_SEL(seg))) 565 return new GeneralProtection(0); 566 bool expandDown = false; 567 SegAttr attr = tc->readMiscRegNoEffect(MISCREG_SEG_ATTR(seg)); 568 if (seg >= SEGMENT_REG_ES && seg <= SEGMENT_REG_HS) { 569 if (!attr.writable && (mode == Write || storeCheck)) 570 return new GeneralProtection(0); 571 if (!attr.readable && mode == Read) 572 return new GeneralProtection(0); 573 expandDown = attr.expandDown; 574 575 } 576 Addr base = tc->readMiscRegNoEffect(MISCREG_SEG_BASE(seg)); 577 Addr limit = tc->readMiscRegNoEffect(MISCREG_SEG_LIMIT(seg)); 578 // This assumes we're not in 64 bit mode. If we were, the default 579 // address size is 64 bits, overridable to 32. 580 int size = 32; 581 bool sizeOverride = (flags & (AddrSizeFlagBit << FlagShift)); 582 SegAttr csAttr = tc->readMiscRegNoEffect(MISCREG_CS_ATTR); 583 if ((csAttr.defaultSize && sizeOverride) || 584 (!csAttr.defaultSize && !sizeOverride)) 585 size = 16; 586 Addr offset = bits(vaddr - base, size-1, 0); 587 Addr endOffset = offset + req->getSize() - 1; 588 if (expandDown) { 589 DPRINTF(TLB, "Checking an expand down segment.\n"); 590 warn_once("Expand down segments are untested.\n"); 591 if (offset <= limit || endOffset <= limit) 592 return new GeneralProtection(0); 593 } else { 594 if (offset > limit || endOffset > limit) 595 return new GeneralProtection(0); 596 } 597 } 598 // If paging is enabled, do the translation. 599 if (m5Reg.paging) { 600 DPRINTF(TLB, "Paging enabled.\n"); 601 // The vaddr already has the segment base applied. 602 TlbEntry *entry = lookup(vaddr); 603 if (!entry) { 604#if FULL_SYSTEM 605 Fault fault = walker->start(tc, translation, req, mode); 606 if (timing || fault != NoFault) { 607 // This gets ignored in atomic mode. 608 delayedResponse = true; 609 return fault; 610 } 611 entry = lookup(vaddr); 612 assert(entry); 613#else 614 DPRINTF(TLB, "Handling a TLB miss for " 615 "address %#x at pc %#x.\n", 616 vaddr, tc->instAddr()); 617 618 Process *p = tc->getProcessPtr(); 619 TlbEntry newEntry; 620 bool success = p->pTable->lookup(vaddr, newEntry); 621 if (!success && mode != Execute) { 622 p->checkAndAllocNextPage(vaddr); 623 success = p->pTable->lookup(vaddr, newEntry); 624 } 625 if (!success) { 626 return new PageFault(vaddr, true, mode, true, false); 627 } else { 628 Addr alignedVaddr = p->pTable->pageAlign(vaddr); 629 DPRINTF(TLB, "Mapping %#x to %#x\n", alignedVaddr, 630 newEntry.pageStart()); 631 entry = insert(alignedVaddr, newEntry); 632 } 633 DPRINTF(TLB, "Miss was serviced.\n"); 634#endif 635 } 636 // Do paging protection checks. 637 bool inUser = (m5Reg.cpl == 3 && 638 !(flags & (CPL0FlagBit << FlagShift))); 639 CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0); 640 bool badWrite = (!entry->writable && (inUser || cr0.wp)); 641 if ((inUser && !entry->user) || (mode == Write && badWrite)) { 642 // The page must have been present to get into the TLB in 643 // the first place. We'll assume the reserved bits are 644 // fine even though we're not checking them. 645 return new PageFault(vaddr, true, mode, inUser, false); 646 } 647 if (storeCheck && badWrite) { 648 // This would fault if this were a write, so return a page 649 // fault that reflects that happening. 650 return new PageFault(vaddr, true, Write, inUser, false); 651 } 652 653 654 DPRINTF(TLB, "Entry found with paddr %#x, " 655 "doing protection checks.\n", entry->paddr); 656 Addr paddr = entry->paddr | (vaddr & (entry->size-1)); 657 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, paddr); 658 req->setPaddr(paddr); 659 if (entry->uncacheable) 660 req->setFlags(Request::UNCACHEABLE); 661 } else { 662 //Use the address which already has segmentation applied. 663 DPRINTF(TLB, "Paging disabled.\n"); 664 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr); 665 req->setPaddr(vaddr); 666 } 667 } else { 668 // Real mode 669 DPRINTF(TLB, "In real mode.\n"); 670 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr); 671 req->setPaddr(vaddr); 672 } 673 // Check for an access to the local APIC 674#if FULL_SYSTEM 675 LocalApicBase localApicBase = tc->readMiscRegNoEffect(MISCREG_APIC_BASE); 676 Addr baseAddr = localApicBase.base * PageBytes; 677 Addr paddr = req->getPaddr(); 678 if (baseAddr <= paddr && baseAddr + PageBytes > paddr) { 679 // The Intel developer's manuals say the below restrictions apply, 680 // but the linux kernel, because of a compiler optimization, breaks 681 // them. 682 /* 683 // Check alignment 684 if (paddr & ((32/8) - 1)) 685 return new GeneralProtection(0); 686 // Check access size 687 if (req->getSize() != (32/8)) 688 return new GeneralProtection(0); 689 */ 690 // Force the access to be uncacheable. 691 req->setFlags(Request::UNCACHEABLE); 692 req->setPaddr(x86LocalAPICAddress(tc->contextId(), paddr - baseAddr)); 693 } 694#endif 695 return NoFault; 696}; 697 698Fault 699TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode) 700{ 701 bool delayedResponse; 702 return TLB::translate(req, tc, NULL, mode, delayedResponse, false); 703} 704 705void 706TLB::translateTiming(RequestPtr req, ThreadContext *tc, 707 Translation *translation, Mode mode) 708{ 709 bool delayedResponse; 710 assert(translation); 711 Fault fault = 712 TLB::translate(req, tc, translation, mode, delayedResponse, true); 713 if (!delayedResponse) 714 translation->finish(fault, req, tc, mode); 715} 716 717#if FULL_SYSTEM 718 719Tick 720TLB::doMmuRegRead(ThreadContext *tc, Packet *pkt) 721{ 722 return tc->getCpuPtr()->ticks(1); 723} 724 725Tick 726TLB::doMmuRegWrite(ThreadContext *tc, Packet *pkt) 727{ 728 return tc->getCpuPtr()->ticks(1); 729} 730 731Walker * 732TLB::getWalker() 733{ 734 return walker; 735} 736 737#endif 738 739void 740TLB::serialize(std::ostream &os) 741{ 742} 743 744void 745TLB::unserialize(Checkpoint *cp, const std::string §ion) 746{ 747} 748 749} // namespace X86ISA 750 751X86ISA::TLB * 752X86TLBParams::create() 753{ 754 return new X86ISA::TLB(this); 755}
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