1/*
2 * Copyright (c) 2007-2008 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * Redistribution and use of this software in source and binary forms,
6 * with or without modification, are permitted provided that the
7 * following conditions are met:
8 *
9 * The software must be used only for Non-Commercial Use which means any
10 * use which is NOT directed to receiving any direct monetary
11 * compensation for, or commercial advantage from such use. Illustrative
12 * examples of non-commercial use are academic research, personal study,
13 * teaching, education and corporate research & development.
14 * Illustrative examples of commercial use are distributing products for
15 * commercial advantage and providing services using the software for
16 * commercial advantage.
17 *
18 * If you wish to use this software or functionality therein that may be
19 * covered by patents for commercial use, please contact:
20 * Director of Intellectual Property Licensing
21 * Office of Strategy and Technology
22 * Hewlett-Packard Company
23 * 1501 Page Mill Road
24 * Palo Alto, California 94304
25 *
26 * Redistributions of source code must retain the above copyright notice,
27 * this list of conditions and the following disclaimer. Redistributions
28 * in binary form must reproduce the above copyright notice, this list of
29 * conditions and the following disclaimer in the documentation and/or
30 * other materials provided with the distribution. Neither the name of
31 * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
32 * contributors may be used to endorse or promote products derived from
33 * this software without specific prior written permission. No right of
34 * sublicense is granted herewith. Derivatives of the software and
35 * output created using the software may be prepared, but only for
36 * Non-Commercial Uses. Derivatives of the software may be shared with
37 * others provided: (i) the others agree to abide by the list of
38 * conditions herein which includes the Non-Commercial Use restrictions;
39 * and (ii) such Derivatives of the software include the above copyright
40 * notice to acknowledge the contribution from this software where
41 * applicable, this list of conditions and the disclaimer below.
42 *
43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
46 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
47 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
49 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 *
55 * Authors: Gabe Black
56 */
57
58#include <cstring>
59
60#include "config/full_system.hh"
61
| 1/*
2 * Copyright (c) 2007-2008 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * Redistribution and use of this software in source and binary forms,
6 * with or without modification, are permitted provided that the
7 * following conditions are met:
8 *
9 * The software must be used only for Non-Commercial Use which means any
10 * use which is NOT directed to receiving any direct monetary
11 * compensation for, or commercial advantage from such use. Illustrative
12 * examples of non-commercial use are academic research, personal study,
13 * teaching, education and corporate research & development.
14 * Illustrative examples of commercial use are distributing products for
15 * commercial advantage and providing services using the software for
16 * commercial advantage.
17 *
18 * If you wish to use this software or functionality therein that may be
19 * covered by patents for commercial use, please contact:
20 * Director of Intellectual Property Licensing
21 * Office of Strategy and Technology
22 * Hewlett-Packard Company
23 * 1501 Page Mill Road
24 * Palo Alto, California 94304
25 *
26 * Redistributions of source code must retain the above copyright notice,
27 * this list of conditions and the following disclaimer. Redistributions
28 * in binary form must reproduce the above copyright notice, this list of
29 * conditions and the following disclaimer in the documentation and/or
30 * other materials provided with the distribution. Neither the name of
31 * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
32 * contributors may be used to endorse or promote products derived from
33 * this software without specific prior written permission. No right of
34 * sublicense is granted herewith. Derivatives of the software and
35 * output created using the software may be prepared, but only for
36 * Non-Commercial Uses. Derivatives of the software may be shared with
37 * others provided: (i) the others agree to abide by the list of
38 * conditions herein which includes the Non-Commercial Use restrictions;
39 * and (ii) such Derivatives of the software include the above copyright
40 * notice to acknowledge the contribution from this software where
41 * applicable, this list of conditions and the disclaimer below.
42 *
43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
46 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
47 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
49 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 *
55 * Authors: Gabe Black
56 */
57
58#include <cstring>
59
60#include "config/full_system.hh"
61
|
62#include "arch/x86/pagetable.hh"
63#include "arch/x86/tlb.hh"
64#include "arch/x86/x86_traits.hh"
65#include "base/bitfield.hh"
66#include "base/trace.hh"
67#include "config/full_system.hh"
68#include "cpu/thread_context.hh"
69#include "cpu/base.hh"
70#include "mem/packet_access.hh"
71#include "mem/request.hh"
72
73#if FULL_SYSTEM
74#include "arch/x86/pagetable_walker.hh"
75#else
76#include "mem/page_table.hh"
77#include "sim/process.hh"
78#endif
79
80namespace X86ISA {
81
82TLB::TLB(const Params *p) : BaseTLB(p), configAddress(0), size(p->size)
83{
84 tlb = new TlbEntry[size];
85 std::memset(tlb, 0, sizeof(TlbEntry) * size);
86
87 for (int x = 0; x < size; x++)
88 freeList.push_back(&tlb[x]);
89
90#if FULL_SYSTEM
91 walker = p->walker;
92 walker->setTLB(this);
93#endif
94}
95
96TlbEntry *
97TLB::insert(Addr vpn, TlbEntry &entry)
98{
99 //TODO Deal with conflicting entries
100
101 TlbEntry *newEntry = NULL;
102 if (!freeList.empty()) {
103 newEntry = freeList.front();
104 freeList.pop_front();
105 } else {
106 newEntry = entryList.back();
107 entryList.pop_back();
108 }
109 *newEntry = entry;
110 newEntry->vaddr = vpn;
111 entryList.push_front(newEntry);
112 return newEntry;
113}
114
115TLB::EntryList::iterator
116TLB::lookupIt(Addr va, bool update_lru)
117{
118 //TODO make this smarter at some point
119 EntryList::iterator entry;
120 for (entry = entryList.begin(); entry != entryList.end(); entry++) {
121 if ((*entry)->vaddr <= va && (*entry)->vaddr + (*entry)->size > va) {
122 DPRINTF(TLB, "Matched vaddr %#x to entry starting at %#x "
123 "with size %#x.\n", va, (*entry)->vaddr, (*entry)->size);
124 if (update_lru) {
125 entryList.push_front(*entry);
126 entryList.erase(entry);
127 entry = entryList.begin();
128 }
129 break;
130 }
131 }
132 return entry;
133}
134
135TlbEntry *
136TLB::lookup(Addr va, bool update_lru)
137{
138 EntryList::iterator entry = lookupIt(va, update_lru);
139 if (entry == entryList.end())
140 return NULL;
141 else
142 return *entry;
143}
144
145void
146TLB::invalidateAll()
147{
148 DPRINTF(TLB, "Invalidating all entries.\n");
149 while (!entryList.empty()) {
150 TlbEntry *entry = entryList.front();
151 entryList.pop_front();
152 freeList.push_back(entry);
153 }
154}
155
156void
157TLB::setConfigAddress(uint32_t addr)
158{
159 configAddress = addr;
160}
161
162void
163TLB::invalidateNonGlobal()
164{
165 DPRINTF(TLB, "Invalidating all non global entries.\n");
166 EntryList::iterator entryIt;
167 for (entryIt = entryList.begin(); entryIt != entryList.end();) {
168 if (!(*entryIt)->global) {
169 freeList.push_back(*entryIt);
170 entryList.erase(entryIt++);
171 } else {
172 entryIt++;
173 }
174 }
175}
176
177void
178TLB::demapPage(Addr va, uint64_t asn)
179{
180 EntryList::iterator entry = lookupIt(va, false);
181 if (entry != entryList.end()) {
182 freeList.push_back(*entry);
183 entryList.erase(entry);
184 }
185}
186
187Fault
188TLB::translate(RequestPtr req, ThreadContext *tc,
189 Translation *translation, bool write, bool execute,
190 bool &delayedResponse, bool timing)
191{
192 delayedResponse = false;
193 Addr vaddr = req->getVaddr();
194 DPRINTF(TLB, "Translating vaddr %#x.\n", vaddr);
195 uint32_t flags = req->getFlags();
196 bool storeCheck = flags & StoreCheck;
197
| 63#include "arch/x86/pagetable.hh"
64#include "arch/x86/tlb.hh"
65#include "arch/x86/x86_traits.hh"
66#include "base/bitfield.hh"
67#include "base/trace.hh"
68#include "config/full_system.hh"
69#include "cpu/thread_context.hh"
70#include "cpu/base.hh"
71#include "mem/packet_access.hh"
72#include "mem/request.hh"
73
74#if FULL_SYSTEM
75#include "arch/x86/pagetable_walker.hh"
76#else
77#include "mem/page_table.hh"
78#include "sim/process.hh"
79#endif
80
81namespace X86ISA {
82
83TLB::TLB(const Params *p) : BaseTLB(p), configAddress(0), size(p->size)
84{
85 tlb = new TlbEntry[size];
86 std::memset(tlb, 0, sizeof(TlbEntry) * size);
87
88 for (int x = 0; x < size; x++)
89 freeList.push_back(&tlb[x]);
90
91#if FULL_SYSTEM
92 walker = p->walker;
93 walker->setTLB(this);
94#endif
95}
96
97TlbEntry *
98TLB::insert(Addr vpn, TlbEntry &entry)
99{
100 //TODO Deal with conflicting entries
101
102 TlbEntry *newEntry = NULL;
103 if (!freeList.empty()) {
104 newEntry = freeList.front();
105 freeList.pop_front();
106 } else {
107 newEntry = entryList.back();
108 entryList.pop_back();
109 }
110 *newEntry = entry;
111 newEntry->vaddr = vpn;
112 entryList.push_front(newEntry);
113 return newEntry;
114}
115
116TLB::EntryList::iterator
117TLB::lookupIt(Addr va, bool update_lru)
118{
119 //TODO make this smarter at some point
120 EntryList::iterator entry;
121 for (entry = entryList.begin(); entry != entryList.end(); entry++) {
122 if ((*entry)->vaddr <= va && (*entry)->vaddr + (*entry)->size > va) {
123 DPRINTF(TLB, "Matched vaddr %#x to entry starting at %#x "
124 "with size %#x.\n", va, (*entry)->vaddr, (*entry)->size);
125 if (update_lru) {
126 entryList.push_front(*entry);
127 entryList.erase(entry);
128 entry = entryList.begin();
129 }
130 break;
131 }
132 }
133 return entry;
134}
135
136TlbEntry *
137TLB::lookup(Addr va, bool update_lru)
138{
139 EntryList::iterator entry = lookupIt(va, update_lru);
140 if (entry == entryList.end())
141 return NULL;
142 else
143 return *entry;
144}
145
146void
147TLB::invalidateAll()
148{
149 DPRINTF(TLB, "Invalidating all entries.\n");
150 while (!entryList.empty()) {
151 TlbEntry *entry = entryList.front();
152 entryList.pop_front();
153 freeList.push_back(entry);
154 }
155}
156
157void
158TLB::setConfigAddress(uint32_t addr)
159{
160 configAddress = addr;
161}
162
163void
164TLB::invalidateNonGlobal()
165{
166 DPRINTF(TLB, "Invalidating all non global entries.\n");
167 EntryList::iterator entryIt;
168 for (entryIt = entryList.begin(); entryIt != entryList.end();) {
169 if (!(*entryIt)->global) {
170 freeList.push_back(*entryIt);
171 entryList.erase(entryIt++);
172 } else {
173 entryIt++;
174 }
175 }
176}
177
178void
179TLB::demapPage(Addr va, uint64_t asn)
180{
181 EntryList::iterator entry = lookupIt(va, false);
182 if (entry != entryList.end()) {
183 freeList.push_back(*entry);
184 entryList.erase(entry);
185 }
186}
187
188Fault
189TLB::translate(RequestPtr req, ThreadContext *tc,
190 Translation *translation, bool write, bool execute,
191 bool &delayedResponse, bool timing)
192{
193 delayedResponse = false;
194 Addr vaddr = req->getVaddr();
195 DPRINTF(TLB, "Translating vaddr %#x.\n", vaddr);
196 uint32_t flags = req->getFlags();
197 bool storeCheck = flags & StoreCheck;
198
|
199
200 //XXX Junk code to surpress the warning
201 if (storeCheck);
202
203 // If this is true, we're dealing with a request to read an internal
204 // value.
205 if (seg == SEGMENT_REG_MS) {
206 DPRINTF(TLB, "Addresses references internal memory.\n");
207 Addr prefix = (vaddr >> 3) & IntAddrPrefixMask;
208 if (prefix == IntAddrPrefixCPUID) {
209 panic("CPUID memory space not yet implemented!\n");
210 } else if (prefix == IntAddrPrefixMSR) {
211 vaddr = vaddr >> 3;
212 req->setMmapedIpr(true);
213 Addr regNum = 0;
214 switch (vaddr & ~IntAddrPrefixMask) {
215 case 0x10:
216 regNum = MISCREG_TSC;
217 break;
218 case 0x1B:
219 regNum = MISCREG_APIC_BASE;
220 break;
221 case 0xFE:
222 regNum = MISCREG_MTRRCAP;
223 break;
224 case 0x174:
225 regNum = MISCREG_SYSENTER_CS;
226 break;
227 case 0x175:
228 regNum = MISCREG_SYSENTER_ESP;
229 break;
230 case 0x176:
231 regNum = MISCREG_SYSENTER_EIP;
232 break;
233 case 0x179:
234 regNum = MISCREG_MCG_CAP;
235 break;
236 case 0x17A:
237 regNum = MISCREG_MCG_STATUS;
238 break;
239 case 0x17B:
240 regNum = MISCREG_MCG_CTL;
241 break;
242 case 0x1D9:
243 regNum = MISCREG_DEBUG_CTL_MSR;
244 break;
245 case 0x1DB:
246 regNum = MISCREG_LAST_BRANCH_FROM_IP;
247 break;
248 case 0x1DC:
249 regNum = MISCREG_LAST_BRANCH_TO_IP;
250 break;
251 case 0x1DD:
252 regNum = MISCREG_LAST_EXCEPTION_FROM_IP;
253 break;
254 case 0x1DE:
255 regNum = MISCREG_LAST_EXCEPTION_TO_IP;
256 break;
257 case 0x200:
258 regNum = MISCREG_MTRR_PHYS_BASE_0;
259 break;
260 case 0x201:
261 regNum = MISCREG_MTRR_PHYS_MASK_0;
262 break;
263 case 0x202:
264 regNum = MISCREG_MTRR_PHYS_BASE_1;
265 break;
266 case 0x203:
267 regNum = MISCREG_MTRR_PHYS_MASK_1;
268 break;
269 case 0x204:
270 regNum = MISCREG_MTRR_PHYS_BASE_2;
271 break;
272 case 0x205:
273 regNum = MISCREG_MTRR_PHYS_MASK_2;
274 break;
275 case 0x206:
276 regNum = MISCREG_MTRR_PHYS_BASE_3;
277 break;
278 case 0x207:
279 regNum = MISCREG_MTRR_PHYS_MASK_3;
280 break;
281 case 0x208:
282 regNum = MISCREG_MTRR_PHYS_BASE_4;
283 break;
284 case 0x209:
285 regNum = MISCREG_MTRR_PHYS_MASK_4;
286 break;
287 case 0x20A:
288 regNum = MISCREG_MTRR_PHYS_BASE_5;
289 break;
290 case 0x20B:
291 regNum = MISCREG_MTRR_PHYS_MASK_5;
292 break;
293 case 0x20C:
294 regNum = MISCREG_MTRR_PHYS_BASE_6;
295 break;
296 case 0x20D:
297 regNum = MISCREG_MTRR_PHYS_MASK_6;
298 break;
299 case 0x20E:
300 regNum = MISCREG_MTRR_PHYS_BASE_7;
301 break;
302 case 0x20F:
303 regNum = MISCREG_MTRR_PHYS_MASK_7;
304 break;
305 case 0x250:
306 regNum = MISCREG_MTRR_FIX_64K_00000;
307 break;
308 case 0x258:
309 regNum = MISCREG_MTRR_FIX_16K_80000;
310 break;
311 case 0x259:
312 regNum = MISCREG_MTRR_FIX_16K_A0000;
313 break;
314 case 0x268:
315 regNum = MISCREG_MTRR_FIX_4K_C0000;
316 break;
317 case 0x269:
318 regNum = MISCREG_MTRR_FIX_4K_C8000;
319 break;
320 case 0x26A:
321 regNum = MISCREG_MTRR_FIX_4K_D0000;
322 break;
323 case 0x26B:
324 regNum = MISCREG_MTRR_FIX_4K_D8000;
325 break;
326 case 0x26C:
327 regNum = MISCREG_MTRR_FIX_4K_E0000;
328 break;
329 case 0x26D:
330 regNum = MISCREG_MTRR_FIX_4K_E8000;
331 break;
332 case 0x26E:
333 regNum = MISCREG_MTRR_FIX_4K_F0000;
334 break;
335 case 0x26F:
336 regNum = MISCREG_MTRR_FIX_4K_F8000;
337 break;
338 case 0x277:
339 regNum = MISCREG_PAT;
340 break;
341 case 0x2FF:
342 regNum = MISCREG_DEF_TYPE;
343 break;
344 case 0x400:
345 regNum = MISCREG_MC0_CTL;
346 break;
347 case 0x404:
348 regNum = MISCREG_MC1_CTL;
349 break;
350 case 0x408:
351 regNum = MISCREG_MC2_CTL;
352 break;
353 case 0x40C:
354 regNum = MISCREG_MC3_CTL;
355 break;
356 case 0x410:
357 regNum = MISCREG_MC4_CTL;
358 break;
359 case 0x414:
360 regNum = MISCREG_MC5_CTL;
361 break;
362 case 0x418:
363 regNum = MISCREG_MC6_CTL;
364 break;
365 case 0x41C:
366 regNum = MISCREG_MC7_CTL;
367 break;
368 case 0x401:
369 regNum = MISCREG_MC0_STATUS;
370 break;
371 case 0x405:
372 regNum = MISCREG_MC1_STATUS;
373 break;
374 case 0x409:
375 regNum = MISCREG_MC2_STATUS;
376 break;
377 case 0x40D:
378 regNum = MISCREG_MC3_STATUS;
379 break;
380 case 0x411:
381 regNum = MISCREG_MC4_STATUS;
382 break;
383 case 0x415:
384 regNum = MISCREG_MC5_STATUS;
385 break;
386 case 0x419:
387 regNum = MISCREG_MC6_STATUS;
388 break;
389 case 0x41D:
390 regNum = MISCREG_MC7_STATUS;
391 break;
392 case 0x402:
393 regNum = MISCREG_MC0_ADDR;
394 break;
395 case 0x406:
396 regNum = MISCREG_MC1_ADDR;
397 break;
398 case 0x40A:
399 regNum = MISCREG_MC2_ADDR;
400 break;
401 case 0x40E:
402 regNum = MISCREG_MC3_ADDR;
403 break;
404 case 0x412:
405 regNum = MISCREG_MC4_ADDR;
406 break;
407 case 0x416:
408 regNum = MISCREG_MC5_ADDR;
409 break;
410 case 0x41A:
411 regNum = MISCREG_MC6_ADDR;
412 break;
413 case 0x41E:
414 regNum = MISCREG_MC7_ADDR;
415 break;
416 case 0x403:
417 regNum = MISCREG_MC0_MISC;
418 break;
419 case 0x407:
420 regNum = MISCREG_MC1_MISC;
421 break;
422 case 0x40B:
423 regNum = MISCREG_MC2_MISC;
424 break;
425 case 0x40F:
426 regNum = MISCREG_MC3_MISC;
427 break;
428 case 0x413:
429 regNum = MISCREG_MC4_MISC;
430 break;
431 case 0x417:
432 regNum = MISCREG_MC5_MISC;
433 break;
434 case 0x41B:
435 regNum = MISCREG_MC6_MISC;
436 break;
437 case 0x41F:
438 regNum = MISCREG_MC7_MISC;
439 break;
440 case 0xC0000080:
441 regNum = MISCREG_EFER;
442 break;
443 case 0xC0000081:
444 regNum = MISCREG_STAR;
445 break;
446 case 0xC0000082:
447 regNum = MISCREG_LSTAR;
448 break;
449 case 0xC0000083:
450 regNum = MISCREG_CSTAR;
451 break;
452 case 0xC0000084:
453 regNum = MISCREG_SF_MASK;
454 break;
455 case 0xC0000100:
456 regNum = MISCREG_FS_BASE;
457 break;
458 case 0xC0000101:
459 regNum = MISCREG_GS_BASE;
460 break;
461 case 0xC0000102:
462 regNum = MISCREG_KERNEL_GS_BASE;
463 break;
464 case 0xC0000103:
465 regNum = MISCREG_TSC_AUX;
466 break;
467 case 0xC0010000:
468 regNum = MISCREG_PERF_EVT_SEL0;
469 break;
470 case 0xC0010001:
471 regNum = MISCREG_PERF_EVT_SEL1;
472 break;
473 case 0xC0010002:
474 regNum = MISCREG_PERF_EVT_SEL2;
475 break;
476 case 0xC0010003:
477 regNum = MISCREG_PERF_EVT_SEL3;
478 break;
479 case 0xC0010004:
480 regNum = MISCREG_PERF_EVT_CTR0;
481 break;
482 case 0xC0010005:
483 regNum = MISCREG_PERF_EVT_CTR1;
484 break;
485 case 0xC0010006:
486 regNum = MISCREG_PERF_EVT_CTR2;
487 break;
488 case 0xC0010007:
489 regNum = MISCREG_PERF_EVT_CTR3;
490 break;
491 case 0xC0010010:
492 regNum = MISCREG_SYSCFG;
493 break;
494 case 0xC0010016:
495 regNum = MISCREG_IORR_BASE0;
496 break;
497 case 0xC0010017:
498 regNum = MISCREG_IORR_BASE1;
499 break;
500 case 0xC0010018:
501 regNum = MISCREG_IORR_MASK0;
502 break;
503 case 0xC0010019:
504 regNum = MISCREG_IORR_MASK1;
505 break;
506 case 0xC001001A:
507 regNum = MISCREG_TOP_MEM;
508 break;
509 case 0xC001001D:
510 regNum = MISCREG_TOP_MEM2;
511 break;
512 case 0xC0010114:
513 regNum = MISCREG_VM_CR;
514 break;
515 case 0xC0010115:
516 regNum = MISCREG_IGNNE;
517 break;
518 case 0xC0010116:
519 regNum = MISCREG_SMM_CTL;
520 break;
521 case 0xC0010117:
522 regNum = MISCREG_VM_HSAVE_PA;
523 break;
524 default:
525 return new GeneralProtection(0);
526 }
527 //The index is multiplied by the size of a MiscReg so that
528 //any memory dependence calculations will not see these as
529 //overlapping.
530 req->setPaddr(regNum * sizeof(MiscReg));
531 return NoFault;
532 } else if (prefix == IntAddrPrefixIO) {
533 // TODO If CPL > IOPL or in virtual mode, check the I/O permission
534 // bitmap in the TSS.
535
536 Addr IOPort = vaddr & ~IntAddrPrefixMask;
537 // Make sure the address fits in the expected 16 bit IO address
538 // space.
539 assert(!(IOPort & ~0xFFFF));
540 if (IOPort == 0xCF8 && req->getSize() == 4) {
541 req->setMmapedIpr(true);
542 req->setPaddr(MISCREG_PCI_CONFIG_ADDRESS * sizeof(MiscReg));
543 } else if ((IOPort & ~mask(2)) == 0xCFC) {
544 Addr configAddress =
545 tc->readMiscRegNoEffect(MISCREG_PCI_CONFIG_ADDRESS);
546 if (bits(configAddress, 31, 31)) {
547 req->setPaddr(PhysAddrPrefixPciConfig |
548 mbits(configAddress, 30, 2) |
549 (IOPort & mask(2)));
550 }
551 } else {
552 req->setPaddr(PhysAddrPrefixIO | IOPort);
553 }
554 return NoFault;
555 } else {
556 panic("Access to unrecognized internal address space %#x.\n",
557 prefix);
558 }
559 }
560
561 // Get cr0. This will tell us how to do translation. We'll assume it was
562 // verified to be correct and consistent when set.
563 CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0);
564
565 // If protected mode has been enabled...
566 if (cr0.pe) {
567 DPRINTF(TLB, "In protected mode.\n");
568 Efer efer = tc->readMiscRegNoEffect(MISCREG_EFER);
569 SegAttr csAttr = tc->readMiscRegNoEffect(MISCREG_CS_ATTR);
570 // If we're not in 64-bit mode, do protection/limit checks
571 if (!efer.lma || !csAttr.longMode) {
572 DPRINTF(TLB, "Not in long mode. Checking segment protection.\n");
573 // Check for a NULL segment selector.
574 if (!tc->readMiscRegNoEffect(MISCREG_SEG_SEL(seg)))
575 return new GeneralProtection(0);
576 bool expandDown = false;
577 if (seg >= SEGMENT_REG_ES && seg <= SEGMENT_REG_HS) {
578 SegAttr attr = tc->readMiscRegNoEffect(MISCREG_SEG_ATTR(seg));
579 if (!attr.writable && write)
580 return new GeneralProtection(0);
581 if (!attr.readable && !write && !execute)
582 return new GeneralProtection(0);
583 expandDown = attr.expandDown;
584 }
585 Addr base = tc->readMiscRegNoEffect(MISCREG_SEG_BASE(seg));
586 Addr limit = tc->readMiscRegNoEffect(MISCREG_SEG_LIMIT(seg));
587 if (expandDown) {
588 DPRINTF(TLB, "Checking an expand down segment.\n");
589 // We don't have to worry about the access going around the
590 // end of memory because accesses will be broken up into
591 // pieces at boundaries aligned on sizes smaller than an
592 // entire address space. We do have to worry about the limit
593 // being less than the base.
594 if (limit < base) {
595 if (limit < vaddr + req->getSize() && vaddr < base)
596 return new GeneralProtection(0);
597 } else {
598 if (limit < vaddr + req->getSize())
599 return new GeneralProtection(0);
600 }
601 } else {
602 if (limit < base) {
603 if (vaddr <= limit || vaddr + req->getSize() >= base)
604 return new GeneralProtection(0);
605 } else {
606 if (vaddr <= limit && vaddr + req->getSize() >= base)
607 return new GeneralProtection(0);
608 }
609 }
610 }
611 // If paging is enabled, do the translation.
612 if (cr0.pg) {
613 DPRINTF(TLB, "Paging enabled.\n");
614 // The vaddr already has the segment base applied.
615 TlbEntry *entry = lookup(vaddr);
616 if (!entry) {
617#if FULL_SYSTEM
618 Fault fault = walker->start(tc, translation, req,
619 write, execute);
620 if (timing || fault != NoFault) {
621 // This gets ignored in atomic mode.
622 delayedResponse = true;
623 return fault;
624 }
625 entry = lookup(vaddr);
626 assert(entry);
627#else
628 DPRINTF(TLB, "Handling a TLB miss for "
629 "address %#x at pc %#x.\n",
630 vaddr, tc->readPC());
631
632 Process *p = tc->getProcessPtr();
633 TlbEntry newEntry;
634 bool success = p->pTable->lookup(vaddr, newEntry);
635 if(!success && !execute) {
636 p->checkAndAllocNextPage(vaddr);
637 success = p->pTable->lookup(vaddr, newEntry);
638 }
639 if(!success) {
640 panic("Tried to execute unmapped address %#x.\n", vaddr);
641 } else {
642 Addr alignedVaddr = p->pTable->pageAlign(vaddr);
643 DPRINTF(TLB, "Mapping %#x to %#x\n", alignedVaddr,
644 newEntry.pageStart());
645 entry = insert(alignedVaddr, newEntry);
646 }
647 DPRINTF(TLB, "Miss was serviced.\n");
648#endif
649 }
650 // Do paging protection checks.
651 DPRINTF(TLB, "Entry found with paddr %#x, "
652 "doing protection checks.\n", entry->paddr);
653 Addr paddr = entry->paddr | (vaddr & (entry->size-1));
654 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, paddr);
655 req->setPaddr(paddr);
656 } else {
657 //Use the address which already has segmentation applied.
658 DPRINTF(TLB, "Paging disabled.\n");
659 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr);
660 req->setPaddr(vaddr);
661 }
662 } else {
663 // Real mode
664 DPRINTF(TLB, "In real mode.\n");
665 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr);
666 req->setPaddr(vaddr);
667 }
668 // Check for an access to the local APIC
669#if FULL_SYSTEM
670 LocalApicBase localApicBase = tc->readMiscRegNoEffect(MISCREG_APIC_BASE);
671 Addr baseAddr = localApicBase.base * PageBytes;
672 Addr paddr = req->getPaddr();
673 if (baseAddr <= paddr && baseAddr + PageBytes > paddr) {
674 // The Intel developer's manuals say the below restrictions apply,
675 // but the linux kernel, because of a compiler optimization, breaks
676 // them.
677 /*
678 // Check alignment
679 if (paddr & ((32/8) - 1))
680 return new GeneralProtection(0);
681 // Check access size
682 if (req->getSize() != (32/8))
683 return new GeneralProtection(0);
684 */
685 // Force the access to be uncacheable.
686 req->setFlags(Request::UNCACHEABLE);
687 req->setPaddr(x86LocalAPICAddress(tc->contextId(), paddr - baseAddr));
688 }
689#endif
690 return NoFault;
691};
692
693Fault
694DTB::translateAtomic(RequestPtr req, ThreadContext *tc, bool write)
695{
696 bool delayedResponse;
697 return TLB::translate(req, tc, NULL, write,
698 false, delayedResponse, false);
699}
700
701void
702DTB::translateTiming(RequestPtr req, ThreadContext *tc,
703 Translation *translation, bool write)
704{
705 bool delayedResponse;
706 assert(translation);
707 Fault fault = TLB::translate(req, tc, translation,
708 write, false, delayedResponse, true);
709 if (!delayedResponse)
710 translation->finish(fault, req, tc, write);
711}
712
713Fault
714ITB::translateAtomic(RequestPtr req, ThreadContext *tc)
715{
716 bool delayedResponse;
717 return TLB::translate(req, tc, NULL, false,
718 true, delayedResponse, false);
719}
720
721void
722ITB::translateTiming(RequestPtr req, ThreadContext *tc,
723 Translation *translation)
724{
725 bool delayedResponse;
726 assert(translation);
727 Fault fault = TLB::translate(req, tc, translation,
728 false, true, delayedResponse, true);
729 if (!delayedResponse)
730 translation->finish(fault, req, tc, false);
731}
732
733#if FULL_SYSTEM
734
735Tick
736DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
737{
738 return tc->getCpuPtr()->ticks(1);
739}
740
741Tick
742DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
743{
744 return tc->getCpuPtr()->ticks(1);
745}
746
747#endif
748
749void
750TLB::serialize(std::ostream &os)
751{
752}
753
754void
755TLB::unserialize(Checkpoint *cp, const std::string §ion)
756{
757}
758
759void
760DTB::serialize(std::ostream &os)
761{
762 TLB::serialize(os);
763}
764
765void
766DTB::unserialize(Checkpoint *cp, const std::string §ion)
767{
768 TLB::unserialize(cp, section);
769}
770
771/* end namespace X86ISA */ }
772
773X86ISA::ITB *
774X86ITBParams::create()
775{
776 return new X86ISA::ITB(this);
777}
778
779X86ISA::DTB *
780X86DTBParams::create()
781{
782 return new X86ISA::DTB(this);
783}
| 200
201 //XXX Junk code to surpress the warning
202 if (storeCheck);
203
204 // If this is true, we're dealing with a request to read an internal
205 // value.
206 if (seg == SEGMENT_REG_MS) {
207 DPRINTF(TLB, "Addresses references internal memory.\n");
208 Addr prefix = (vaddr >> 3) & IntAddrPrefixMask;
209 if (prefix == IntAddrPrefixCPUID) {
210 panic("CPUID memory space not yet implemented!\n");
211 } else if (prefix == IntAddrPrefixMSR) {
212 vaddr = vaddr >> 3;
213 req->setMmapedIpr(true);
214 Addr regNum = 0;
215 switch (vaddr & ~IntAddrPrefixMask) {
216 case 0x10:
217 regNum = MISCREG_TSC;
218 break;
219 case 0x1B:
220 regNum = MISCREG_APIC_BASE;
221 break;
222 case 0xFE:
223 regNum = MISCREG_MTRRCAP;
224 break;
225 case 0x174:
226 regNum = MISCREG_SYSENTER_CS;
227 break;
228 case 0x175:
229 regNum = MISCREG_SYSENTER_ESP;
230 break;
231 case 0x176:
232 regNum = MISCREG_SYSENTER_EIP;
233 break;
234 case 0x179:
235 regNum = MISCREG_MCG_CAP;
236 break;
237 case 0x17A:
238 regNum = MISCREG_MCG_STATUS;
239 break;
240 case 0x17B:
241 regNum = MISCREG_MCG_CTL;
242 break;
243 case 0x1D9:
244 regNum = MISCREG_DEBUG_CTL_MSR;
245 break;
246 case 0x1DB:
247 regNum = MISCREG_LAST_BRANCH_FROM_IP;
248 break;
249 case 0x1DC:
250 regNum = MISCREG_LAST_BRANCH_TO_IP;
251 break;
252 case 0x1DD:
253 regNum = MISCREG_LAST_EXCEPTION_FROM_IP;
254 break;
255 case 0x1DE:
256 regNum = MISCREG_LAST_EXCEPTION_TO_IP;
257 break;
258 case 0x200:
259 regNum = MISCREG_MTRR_PHYS_BASE_0;
260 break;
261 case 0x201:
262 regNum = MISCREG_MTRR_PHYS_MASK_0;
263 break;
264 case 0x202:
265 regNum = MISCREG_MTRR_PHYS_BASE_1;
266 break;
267 case 0x203:
268 regNum = MISCREG_MTRR_PHYS_MASK_1;
269 break;
270 case 0x204:
271 regNum = MISCREG_MTRR_PHYS_BASE_2;
272 break;
273 case 0x205:
274 regNum = MISCREG_MTRR_PHYS_MASK_2;
275 break;
276 case 0x206:
277 regNum = MISCREG_MTRR_PHYS_BASE_3;
278 break;
279 case 0x207:
280 regNum = MISCREG_MTRR_PHYS_MASK_3;
281 break;
282 case 0x208:
283 regNum = MISCREG_MTRR_PHYS_BASE_4;
284 break;
285 case 0x209:
286 regNum = MISCREG_MTRR_PHYS_MASK_4;
287 break;
288 case 0x20A:
289 regNum = MISCREG_MTRR_PHYS_BASE_5;
290 break;
291 case 0x20B:
292 regNum = MISCREG_MTRR_PHYS_MASK_5;
293 break;
294 case 0x20C:
295 regNum = MISCREG_MTRR_PHYS_BASE_6;
296 break;
297 case 0x20D:
298 regNum = MISCREG_MTRR_PHYS_MASK_6;
299 break;
300 case 0x20E:
301 regNum = MISCREG_MTRR_PHYS_BASE_7;
302 break;
303 case 0x20F:
304 regNum = MISCREG_MTRR_PHYS_MASK_7;
305 break;
306 case 0x250:
307 regNum = MISCREG_MTRR_FIX_64K_00000;
308 break;
309 case 0x258:
310 regNum = MISCREG_MTRR_FIX_16K_80000;
311 break;
312 case 0x259:
313 regNum = MISCREG_MTRR_FIX_16K_A0000;
314 break;
315 case 0x268:
316 regNum = MISCREG_MTRR_FIX_4K_C0000;
317 break;
318 case 0x269:
319 regNum = MISCREG_MTRR_FIX_4K_C8000;
320 break;
321 case 0x26A:
322 regNum = MISCREG_MTRR_FIX_4K_D0000;
323 break;
324 case 0x26B:
325 regNum = MISCREG_MTRR_FIX_4K_D8000;
326 break;
327 case 0x26C:
328 regNum = MISCREG_MTRR_FIX_4K_E0000;
329 break;
330 case 0x26D:
331 regNum = MISCREG_MTRR_FIX_4K_E8000;
332 break;
333 case 0x26E:
334 regNum = MISCREG_MTRR_FIX_4K_F0000;
335 break;
336 case 0x26F:
337 regNum = MISCREG_MTRR_FIX_4K_F8000;
338 break;
339 case 0x277:
340 regNum = MISCREG_PAT;
341 break;
342 case 0x2FF:
343 regNum = MISCREG_DEF_TYPE;
344 break;
345 case 0x400:
346 regNum = MISCREG_MC0_CTL;
347 break;
348 case 0x404:
349 regNum = MISCREG_MC1_CTL;
350 break;
351 case 0x408:
352 regNum = MISCREG_MC2_CTL;
353 break;
354 case 0x40C:
355 regNum = MISCREG_MC3_CTL;
356 break;
357 case 0x410:
358 regNum = MISCREG_MC4_CTL;
359 break;
360 case 0x414:
361 regNum = MISCREG_MC5_CTL;
362 break;
363 case 0x418:
364 regNum = MISCREG_MC6_CTL;
365 break;
366 case 0x41C:
367 regNum = MISCREG_MC7_CTL;
368 break;
369 case 0x401:
370 regNum = MISCREG_MC0_STATUS;
371 break;
372 case 0x405:
373 regNum = MISCREG_MC1_STATUS;
374 break;
375 case 0x409:
376 regNum = MISCREG_MC2_STATUS;
377 break;
378 case 0x40D:
379 regNum = MISCREG_MC3_STATUS;
380 break;
381 case 0x411:
382 regNum = MISCREG_MC4_STATUS;
383 break;
384 case 0x415:
385 regNum = MISCREG_MC5_STATUS;
386 break;
387 case 0x419:
388 regNum = MISCREG_MC6_STATUS;
389 break;
390 case 0x41D:
391 regNum = MISCREG_MC7_STATUS;
392 break;
393 case 0x402:
394 regNum = MISCREG_MC0_ADDR;
395 break;
396 case 0x406:
397 regNum = MISCREG_MC1_ADDR;
398 break;
399 case 0x40A:
400 regNum = MISCREG_MC2_ADDR;
401 break;
402 case 0x40E:
403 regNum = MISCREG_MC3_ADDR;
404 break;
405 case 0x412:
406 regNum = MISCREG_MC4_ADDR;
407 break;
408 case 0x416:
409 regNum = MISCREG_MC5_ADDR;
410 break;
411 case 0x41A:
412 regNum = MISCREG_MC6_ADDR;
413 break;
414 case 0x41E:
415 regNum = MISCREG_MC7_ADDR;
416 break;
417 case 0x403:
418 regNum = MISCREG_MC0_MISC;
419 break;
420 case 0x407:
421 regNum = MISCREG_MC1_MISC;
422 break;
423 case 0x40B:
424 regNum = MISCREG_MC2_MISC;
425 break;
426 case 0x40F:
427 regNum = MISCREG_MC3_MISC;
428 break;
429 case 0x413:
430 regNum = MISCREG_MC4_MISC;
431 break;
432 case 0x417:
433 regNum = MISCREG_MC5_MISC;
434 break;
435 case 0x41B:
436 regNum = MISCREG_MC6_MISC;
437 break;
438 case 0x41F:
439 regNum = MISCREG_MC7_MISC;
440 break;
441 case 0xC0000080:
442 regNum = MISCREG_EFER;
443 break;
444 case 0xC0000081:
445 regNum = MISCREG_STAR;
446 break;
447 case 0xC0000082:
448 regNum = MISCREG_LSTAR;
449 break;
450 case 0xC0000083:
451 regNum = MISCREG_CSTAR;
452 break;
453 case 0xC0000084:
454 regNum = MISCREG_SF_MASK;
455 break;
456 case 0xC0000100:
457 regNum = MISCREG_FS_BASE;
458 break;
459 case 0xC0000101:
460 regNum = MISCREG_GS_BASE;
461 break;
462 case 0xC0000102:
463 regNum = MISCREG_KERNEL_GS_BASE;
464 break;
465 case 0xC0000103:
466 regNum = MISCREG_TSC_AUX;
467 break;
468 case 0xC0010000:
469 regNum = MISCREG_PERF_EVT_SEL0;
470 break;
471 case 0xC0010001:
472 regNum = MISCREG_PERF_EVT_SEL1;
473 break;
474 case 0xC0010002:
475 regNum = MISCREG_PERF_EVT_SEL2;
476 break;
477 case 0xC0010003:
478 regNum = MISCREG_PERF_EVT_SEL3;
479 break;
480 case 0xC0010004:
481 regNum = MISCREG_PERF_EVT_CTR0;
482 break;
483 case 0xC0010005:
484 regNum = MISCREG_PERF_EVT_CTR1;
485 break;
486 case 0xC0010006:
487 regNum = MISCREG_PERF_EVT_CTR2;
488 break;
489 case 0xC0010007:
490 regNum = MISCREG_PERF_EVT_CTR3;
491 break;
492 case 0xC0010010:
493 regNum = MISCREG_SYSCFG;
494 break;
495 case 0xC0010016:
496 regNum = MISCREG_IORR_BASE0;
497 break;
498 case 0xC0010017:
499 regNum = MISCREG_IORR_BASE1;
500 break;
501 case 0xC0010018:
502 regNum = MISCREG_IORR_MASK0;
503 break;
504 case 0xC0010019:
505 regNum = MISCREG_IORR_MASK1;
506 break;
507 case 0xC001001A:
508 regNum = MISCREG_TOP_MEM;
509 break;
510 case 0xC001001D:
511 regNum = MISCREG_TOP_MEM2;
512 break;
513 case 0xC0010114:
514 regNum = MISCREG_VM_CR;
515 break;
516 case 0xC0010115:
517 regNum = MISCREG_IGNNE;
518 break;
519 case 0xC0010116:
520 regNum = MISCREG_SMM_CTL;
521 break;
522 case 0xC0010117:
523 regNum = MISCREG_VM_HSAVE_PA;
524 break;
525 default:
526 return new GeneralProtection(0);
527 }
528 //The index is multiplied by the size of a MiscReg so that
529 //any memory dependence calculations will not see these as
530 //overlapping.
531 req->setPaddr(regNum * sizeof(MiscReg));
532 return NoFault;
533 } else if (prefix == IntAddrPrefixIO) {
534 // TODO If CPL > IOPL or in virtual mode, check the I/O permission
535 // bitmap in the TSS.
536
537 Addr IOPort = vaddr & ~IntAddrPrefixMask;
538 // Make sure the address fits in the expected 16 bit IO address
539 // space.
540 assert(!(IOPort & ~0xFFFF));
541 if (IOPort == 0xCF8 && req->getSize() == 4) {
542 req->setMmapedIpr(true);
543 req->setPaddr(MISCREG_PCI_CONFIG_ADDRESS * sizeof(MiscReg));
544 } else if ((IOPort & ~mask(2)) == 0xCFC) {
545 Addr configAddress =
546 tc->readMiscRegNoEffect(MISCREG_PCI_CONFIG_ADDRESS);
547 if (bits(configAddress, 31, 31)) {
548 req->setPaddr(PhysAddrPrefixPciConfig |
549 mbits(configAddress, 30, 2) |
550 (IOPort & mask(2)));
551 }
552 } else {
553 req->setPaddr(PhysAddrPrefixIO | IOPort);
554 }
555 return NoFault;
556 } else {
557 panic("Access to unrecognized internal address space %#x.\n",
558 prefix);
559 }
560 }
561
562 // Get cr0. This will tell us how to do translation. We'll assume it was
563 // verified to be correct and consistent when set.
564 CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0);
565
566 // If protected mode has been enabled...
567 if (cr0.pe) {
568 DPRINTF(TLB, "In protected mode.\n");
569 Efer efer = tc->readMiscRegNoEffect(MISCREG_EFER);
570 SegAttr csAttr = tc->readMiscRegNoEffect(MISCREG_CS_ATTR);
571 // If we're not in 64-bit mode, do protection/limit checks
572 if (!efer.lma || !csAttr.longMode) {
573 DPRINTF(TLB, "Not in long mode. Checking segment protection.\n");
574 // Check for a NULL segment selector.
575 if (!tc->readMiscRegNoEffect(MISCREG_SEG_SEL(seg)))
576 return new GeneralProtection(0);
577 bool expandDown = false;
578 if (seg >= SEGMENT_REG_ES && seg <= SEGMENT_REG_HS) {
579 SegAttr attr = tc->readMiscRegNoEffect(MISCREG_SEG_ATTR(seg));
580 if (!attr.writable && write)
581 return new GeneralProtection(0);
582 if (!attr.readable && !write && !execute)
583 return new GeneralProtection(0);
584 expandDown = attr.expandDown;
585 }
586 Addr base = tc->readMiscRegNoEffect(MISCREG_SEG_BASE(seg));
587 Addr limit = tc->readMiscRegNoEffect(MISCREG_SEG_LIMIT(seg));
588 if (expandDown) {
589 DPRINTF(TLB, "Checking an expand down segment.\n");
590 // We don't have to worry about the access going around the
591 // end of memory because accesses will be broken up into
592 // pieces at boundaries aligned on sizes smaller than an
593 // entire address space. We do have to worry about the limit
594 // being less than the base.
595 if (limit < base) {
596 if (limit < vaddr + req->getSize() && vaddr < base)
597 return new GeneralProtection(0);
598 } else {
599 if (limit < vaddr + req->getSize())
600 return new GeneralProtection(0);
601 }
602 } else {
603 if (limit < base) {
604 if (vaddr <= limit || vaddr + req->getSize() >= base)
605 return new GeneralProtection(0);
606 } else {
607 if (vaddr <= limit && vaddr + req->getSize() >= base)
608 return new GeneralProtection(0);
609 }
610 }
611 }
612 // If paging is enabled, do the translation.
613 if (cr0.pg) {
614 DPRINTF(TLB, "Paging enabled.\n");
615 // The vaddr already has the segment base applied.
616 TlbEntry *entry = lookup(vaddr);
617 if (!entry) {
618#if FULL_SYSTEM
619 Fault fault = walker->start(tc, translation, req,
620 write, execute);
621 if (timing || fault != NoFault) {
622 // This gets ignored in atomic mode.
623 delayedResponse = true;
624 return fault;
625 }
626 entry = lookup(vaddr);
627 assert(entry);
628#else
629 DPRINTF(TLB, "Handling a TLB miss for "
630 "address %#x at pc %#x.\n",
631 vaddr, tc->readPC());
632
633 Process *p = tc->getProcessPtr();
634 TlbEntry newEntry;
635 bool success = p->pTable->lookup(vaddr, newEntry);
636 if(!success && !execute) {
637 p->checkAndAllocNextPage(vaddr);
638 success = p->pTable->lookup(vaddr, newEntry);
639 }
640 if(!success) {
641 panic("Tried to execute unmapped address %#x.\n", vaddr);
642 } else {
643 Addr alignedVaddr = p->pTable->pageAlign(vaddr);
644 DPRINTF(TLB, "Mapping %#x to %#x\n", alignedVaddr,
645 newEntry.pageStart());
646 entry = insert(alignedVaddr, newEntry);
647 }
648 DPRINTF(TLB, "Miss was serviced.\n");
649#endif
650 }
651 // Do paging protection checks.
652 DPRINTF(TLB, "Entry found with paddr %#x, "
653 "doing protection checks.\n", entry->paddr);
654 Addr paddr = entry->paddr | (vaddr & (entry->size-1));
655 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, paddr);
656 req->setPaddr(paddr);
657 } else {
658 //Use the address which already has segmentation applied.
659 DPRINTF(TLB, "Paging disabled.\n");
660 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr);
661 req->setPaddr(vaddr);
662 }
663 } else {
664 // Real mode
665 DPRINTF(TLB, "In real mode.\n");
666 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr);
667 req->setPaddr(vaddr);
668 }
669 // Check for an access to the local APIC
670#if FULL_SYSTEM
671 LocalApicBase localApicBase = tc->readMiscRegNoEffect(MISCREG_APIC_BASE);
672 Addr baseAddr = localApicBase.base * PageBytes;
673 Addr paddr = req->getPaddr();
674 if (baseAddr <= paddr && baseAddr + PageBytes > paddr) {
675 // The Intel developer's manuals say the below restrictions apply,
676 // but the linux kernel, because of a compiler optimization, breaks
677 // them.
678 /*
679 // Check alignment
680 if (paddr & ((32/8) - 1))
681 return new GeneralProtection(0);
682 // Check access size
683 if (req->getSize() != (32/8))
684 return new GeneralProtection(0);
685 */
686 // Force the access to be uncacheable.
687 req->setFlags(Request::UNCACHEABLE);
688 req->setPaddr(x86LocalAPICAddress(tc->contextId(), paddr - baseAddr));
689 }
690#endif
691 return NoFault;
692};
693
694Fault
695DTB::translateAtomic(RequestPtr req, ThreadContext *tc, bool write)
696{
697 bool delayedResponse;
698 return TLB::translate(req, tc, NULL, write,
699 false, delayedResponse, false);
700}
701
702void
703DTB::translateTiming(RequestPtr req, ThreadContext *tc,
704 Translation *translation, bool write)
705{
706 bool delayedResponse;
707 assert(translation);
708 Fault fault = TLB::translate(req, tc, translation,
709 write, false, delayedResponse, true);
710 if (!delayedResponse)
711 translation->finish(fault, req, tc, write);
712}
713
714Fault
715ITB::translateAtomic(RequestPtr req, ThreadContext *tc)
716{
717 bool delayedResponse;
718 return TLB::translate(req, tc, NULL, false,
719 true, delayedResponse, false);
720}
721
722void
723ITB::translateTiming(RequestPtr req, ThreadContext *tc,
724 Translation *translation)
725{
726 bool delayedResponse;
727 assert(translation);
728 Fault fault = TLB::translate(req, tc, translation,
729 false, true, delayedResponse, true);
730 if (!delayedResponse)
731 translation->finish(fault, req, tc, false);
732}
733
734#if FULL_SYSTEM
735
736Tick
737DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
738{
739 return tc->getCpuPtr()->ticks(1);
740}
741
742Tick
743DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
744{
745 return tc->getCpuPtr()->ticks(1);
746}
747
748#endif
749
750void
751TLB::serialize(std::ostream &os)
752{
753}
754
755void
756TLB::unserialize(Checkpoint *cp, const std::string §ion)
757{
758}
759
760void
761DTB::serialize(std::ostream &os)
762{
763 TLB::serialize(os);
764}
765
766void
767DTB::unserialize(Checkpoint *cp, const std::string §ion)
768{
769 TLB::unserialize(cp, section);
770}
771
772/* end namespace X86ISA */ }
773
774X86ISA::ITB *
775X86ITBParams::create()
776{
777 return new X86ISA::ITB(this);
778}
779
780X86ISA::DTB *
781X86DTBParams::create()
782{
783 return new X86ISA::DTB(this);
784}
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