1/*
2 * Copyright (c) 2007-2008 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * Redistribution and use of this software in source and binary forms,
6 * with or without modification, are permitted provided that the
7 * following conditions are met:
8 *
9 * The software must be used only for Non-Commercial Use which means any
10 * use which is NOT directed to receiving any direct monetary
11 * compensation for, or commercial advantage from such use. Illustrative
12 * examples of non-commercial use are academic research, personal study,
13 * teaching, education and corporate research & development.
14 * Illustrative examples of commercial use are distributing products for
15 * commercial advantage and providing services using the software for
16 * commercial advantage.
17 *
18 * If you wish to use this software or functionality therein that may be
19 * covered by patents for commercial use, please contact:
20 * Director of Intellectual Property Licensing
21 * Office of Strategy and Technology
22 * Hewlett-Packard Company
23 * 1501 Page Mill Road
24 * Palo Alto, California 94304
25 *
26 * Redistributions of source code must retain the above copyright notice,
27 * this list of conditions and the following disclaimer. Redistributions
28 * in binary form must reproduce the above copyright notice, this list of
29 * conditions and the following disclaimer in the documentation and/or
30 * other materials provided with the distribution. Neither the name of
31 * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
32 * contributors may be used to endorse or promote products derived from
33 * this software without specific prior written permission. No right of
34 * sublicense is granted herewith. Derivatives of the software and
35 * output created using the software may be prepared, but only for
36 * Non-Commercial Uses. Derivatives of the software may be shared with
37 * others provided: (i) the others agree to abide by the list of
38 * conditions herein which includes the Non-Commercial Use restrictions;
39 * and (ii) such Derivatives of the software include the above copyright
40 * notice to acknowledge the contribution from this software where
41 * applicable, this list of conditions and the disclaimer below.
42 *
43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
46 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
47 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
49 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 *
55 * Authors: Gabe Black
56 */
57
58#include <cstring>
59
60#include "config/full_system.hh"
61
62#include "arch/x86/pagetable.hh"
63#include "arch/x86/tlb.hh"
64#include "arch/x86/x86_traits.hh"
65#include "base/bitfield.hh"
66#include "base/trace.hh"
67#include "config/full_system.hh"
68#include "cpu/thread_context.hh"
69#include "cpu/base.hh"
70#include "mem/packet_access.hh"
71#include "mem/request.hh"
72
73#if FULL_SYSTEM
74#include "arch/x86/pagetable_walker.hh"
75#endif
76
77namespace X86ISA {
78
79TLB::TLB(const Params *p) : BaseTLB(p), configAddress(0), size(p->size)
80{
81 tlb = new TlbEntry[size];
82 std::memset(tlb, 0, sizeof(TlbEntry) * size);
83
84 for (int x = 0; x < size; x++)
85 freeList.push_back(&tlb[x]);
86
87#if FULL_SYSTEM
88 walker = p->walker;
89 walker->setTLB(this);
90#endif
91}
92
93void
94TLB::insert(Addr vpn, TlbEntry &entry)
95{
96 //TODO Deal with conflicting entries
97
98 TlbEntry *newEntry = NULL;
99 if (!freeList.empty()) {
100 newEntry = freeList.front();
101 freeList.pop_front();
102 } else {
103 newEntry = entryList.back();
104 entryList.pop_back();
105 }
106 *newEntry = entry;
107 newEntry->vaddr = vpn;
108 entryList.push_front(newEntry);
109}
110
111TLB::EntryList::iterator
112TLB::lookupIt(Addr va, bool update_lru)
113{
114 //TODO make this smarter at some point
115 EntryList::iterator entry;
116 for (entry = entryList.begin(); entry != entryList.end(); entry++) {
117 if ((*entry)->vaddr <= va && (*entry)->vaddr + (*entry)->size > va) {
118 DPRINTF(TLB, "Matched vaddr %#x to entry starting at %#x "
119 "with size %#x.\n", va, (*entry)->vaddr, (*entry)->size);
120 if (update_lru) {
121 entryList.push_front(*entry);
122 entryList.erase(entry);
123 entry = entryList.begin();
124 }
125 break;
126 }
127 }
128 return entry;
129}
130
131TlbEntry *
132TLB::lookup(Addr va, bool update_lru)
133{
134 EntryList::iterator entry = lookupIt(va, update_lru);
135 if (entry == entryList.end())
136 return NULL;
137 else
138 return *entry;
139}
140
141#if FULL_SYSTEM
142void
143TLB::walk(ThreadContext * _tc, Addr vaddr, bool write, bool execute)
144{
145 walker->start(_tc, vaddr, write, execute);
146}
147#endif
148
149void
150TLB::invalidateAll()
151{
152 DPRINTF(TLB, "Invalidating all entries.\n");
153 while (!entryList.empty()) {
154 TlbEntry *entry = entryList.front();
155 entryList.pop_front();
156 freeList.push_back(entry);
157 }
158}
159
160void
161TLB::setConfigAddress(uint32_t addr)
162{
163 configAddress = addr;
164}
165
166void
167TLB::invalidateNonGlobal()
168{
169 DPRINTF(TLB, "Invalidating all non global entries.\n");
170 EntryList::iterator entryIt;
171 for (entryIt = entryList.begin(); entryIt != entryList.end();) {
172 if (!(*entryIt)->global) {
173 freeList.push_back(*entryIt);
174 entryList.erase(entryIt++);
175 } else {
176 entryIt++;
177 }
178 }
179}
180
181void
182TLB::demapPage(Addr va, uint64_t asn)
183{
184 EntryList::iterator entry = lookupIt(va, false);
185 if (entry != entryList.end()) {
186 freeList.push_back(*entry);
187 entryList.erase(entry);
188 }
189}
190
191template<class TlbFault>
192Fault
| 1/*
2 * Copyright (c) 2007-2008 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * Redistribution and use of this software in source and binary forms,
6 * with or without modification, are permitted provided that the
7 * following conditions are met:
8 *
9 * The software must be used only for Non-Commercial Use which means any
10 * use which is NOT directed to receiving any direct monetary
11 * compensation for, or commercial advantage from such use. Illustrative
12 * examples of non-commercial use are academic research, personal study,
13 * teaching, education and corporate research & development.
14 * Illustrative examples of commercial use are distributing products for
15 * commercial advantage and providing services using the software for
16 * commercial advantage.
17 *
18 * If you wish to use this software or functionality therein that may be
19 * covered by patents for commercial use, please contact:
20 * Director of Intellectual Property Licensing
21 * Office of Strategy and Technology
22 * Hewlett-Packard Company
23 * 1501 Page Mill Road
24 * Palo Alto, California 94304
25 *
26 * Redistributions of source code must retain the above copyright notice,
27 * this list of conditions and the following disclaimer. Redistributions
28 * in binary form must reproduce the above copyright notice, this list of
29 * conditions and the following disclaimer in the documentation and/or
30 * other materials provided with the distribution. Neither the name of
31 * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
32 * contributors may be used to endorse or promote products derived from
33 * this software without specific prior written permission. No right of
34 * sublicense is granted herewith. Derivatives of the software and
35 * output created using the software may be prepared, but only for
36 * Non-Commercial Uses. Derivatives of the software may be shared with
37 * others provided: (i) the others agree to abide by the list of
38 * conditions herein which includes the Non-Commercial Use restrictions;
39 * and (ii) such Derivatives of the software include the above copyright
40 * notice to acknowledge the contribution from this software where
41 * applicable, this list of conditions and the disclaimer below.
42 *
43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
46 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
47 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
49 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 *
55 * Authors: Gabe Black
56 */
57
58#include <cstring>
59
60#include "config/full_system.hh"
61
62#include "arch/x86/pagetable.hh"
63#include "arch/x86/tlb.hh"
64#include "arch/x86/x86_traits.hh"
65#include "base/bitfield.hh"
66#include "base/trace.hh"
67#include "config/full_system.hh"
68#include "cpu/thread_context.hh"
69#include "cpu/base.hh"
70#include "mem/packet_access.hh"
71#include "mem/request.hh"
72
73#if FULL_SYSTEM
74#include "arch/x86/pagetable_walker.hh"
75#endif
76
77namespace X86ISA {
78
79TLB::TLB(const Params *p) : BaseTLB(p), configAddress(0), size(p->size)
80{
81 tlb = new TlbEntry[size];
82 std::memset(tlb, 0, sizeof(TlbEntry) * size);
83
84 for (int x = 0; x < size; x++)
85 freeList.push_back(&tlb[x]);
86
87#if FULL_SYSTEM
88 walker = p->walker;
89 walker->setTLB(this);
90#endif
91}
92
93void
94TLB::insert(Addr vpn, TlbEntry &entry)
95{
96 //TODO Deal with conflicting entries
97
98 TlbEntry *newEntry = NULL;
99 if (!freeList.empty()) {
100 newEntry = freeList.front();
101 freeList.pop_front();
102 } else {
103 newEntry = entryList.back();
104 entryList.pop_back();
105 }
106 *newEntry = entry;
107 newEntry->vaddr = vpn;
108 entryList.push_front(newEntry);
109}
110
111TLB::EntryList::iterator
112TLB::lookupIt(Addr va, bool update_lru)
113{
114 //TODO make this smarter at some point
115 EntryList::iterator entry;
116 for (entry = entryList.begin(); entry != entryList.end(); entry++) {
117 if ((*entry)->vaddr <= va && (*entry)->vaddr + (*entry)->size > va) {
118 DPRINTF(TLB, "Matched vaddr %#x to entry starting at %#x "
119 "with size %#x.\n", va, (*entry)->vaddr, (*entry)->size);
120 if (update_lru) {
121 entryList.push_front(*entry);
122 entryList.erase(entry);
123 entry = entryList.begin();
124 }
125 break;
126 }
127 }
128 return entry;
129}
130
131TlbEntry *
132TLB::lookup(Addr va, bool update_lru)
133{
134 EntryList::iterator entry = lookupIt(va, update_lru);
135 if (entry == entryList.end())
136 return NULL;
137 else
138 return *entry;
139}
140
141#if FULL_SYSTEM
142void
143TLB::walk(ThreadContext * _tc, Addr vaddr, bool write, bool execute)
144{
145 walker->start(_tc, vaddr, write, execute);
146}
147#endif
148
149void
150TLB::invalidateAll()
151{
152 DPRINTF(TLB, "Invalidating all entries.\n");
153 while (!entryList.empty()) {
154 TlbEntry *entry = entryList.front();
155 entryList.pop_front();
156 freeList.push_back(entry);
157 }
158}
159
160void
161TLB::setConfigAddress(uint32_t addr)
162{
163 configAddress = addr;
164}
165
166void
167TLB::invalidateNonGlobal()
168{
169 DPRINTF(TLB, "Invalidating all non global entries.\n");
170 EntryList::iterator entryIt;
171 for (entryIt = entryList.begin(); entryIt != entryList.end();) {
172 if (!(*entryIt)->global) {
173 freeList.push_back(*entryIt);
174 entryList.erase(entryIt++);
175 } else {
176 entryIt++;
177 }
178 }
179}
180
181void
182TLB::demapPage(Addr va, uint64_t asn)
183{
184 EntryList::iterator entry = lookupIt(va, false);
185 if (entry != entryList.end()) {
186 freeList.push_back(*entry);
187 entryList.erase(entry);
188 }
189}
190
191template<class TlbFault>
192Fault
|
193TLB::translateAtomic(RequestPtr &req, ThreadContext *tc,
| 193TLB::translateAtomic(RequestPtr req, ThreadContext *tc,
|
194 bool write, bool execute)
195{
196 Addr vaddr = req->getVaddr();
197 DPRINTF(TLB, "Translating vaddr %#x.\n", vaddr);
198 uint32_t flags = req->getFlags();
199 bool storeCheck = flags & StoreCheck;
200
201 int seg = flags & mask(4);
202
203 //XXX Junk code to surpress the warning
204 if (storeCheck);
205
206 // If this is true, we're dealing with a request to read an internal
207 // value.
208 if (seg == SEGMENT_REG_MS) {
209 DPRINTF(TLB, "Addresses references internal memory.\n");
210 Addr prefix = (vaddr >> 3) & IntAddrPrefixMask;
211 if (prefix == IntAddrPrefixCPUID) {
212 panic("CPUID memory space not yet implemented!\n");
213 } else if (prefix == IntAddrPrefixMSR) {
214 vaddr = vaddr >> 3;
215 req->setMmapedIpr(true);
216 Addr regNum = 0;
217 switch (vaddr & ~IntAddrPrefixMask) {
218 case 0x10:
219 regNum = MISCREG_TSC;
220 break;
221 case 0x1B:
222 regNum = MISCREG_APIC_BASE;
223 break;
224 case 0xFE:
225 regNum = MISCREG_MTRRCAP;
226 break;
227 case 0x174:
228 regNum = MISCREG_SYSENTER_CS;
229 break;
230 case 0x175:
231 regNum = MISCREG_SYSENTER_ESP;
232 break;
233 case 0x176:
234 regNum = MISCREG_SYSENTER_EIP;
235 break;
236 case 0x179:
237 regNum = MISCREG_MCG_CAP;
238 break;
239 case 0x17A:
240 regNum = MISCREG_MCG_STATUS;
241 break;
242 case 0x17B:
243 regNum = MISCREG_MCG_CTL;
244 break;
245 case 0x1D9:
246 regNum = MISCREG_DEBUG_CTL_MSR;
247 break;
248 case 0x1DB:
249 regNum = MISCREG_LAST_BRANCH_FROM_IP;
250 break;
251 case 0x1DC:
252 regNum = MISCREG_LAST_BRANCH_TO_IP;
253 break;
254 case 0x1DD:
255 regNum = MISCREG_LAST_EXCEPTION_FROM_IP;
256 break;
257 case 0x1DE:
258 regNum = MISCREG_LAST_EXCEPTION_TO_IP;
259 break;
260 case 0x200:
261 regNum = MISCREG_MTRR_PHYS_BASE_0;
262 break;
263 case 0x201:
264 regNum = MISCREG_MTRR_PHYS_MASK_0;
265 break;
266 case 0x202:
267 regNum = MISCREG_MTRR_PHYS_BASE_1;
268 break;
269 case 0x203:
270 regNum = MISCREG_MTRR_PHYS_MASK_1;
271 break;
272 case 0x204:
273 regNum = MISCREG_MTRR_PHYS_BASE_2;
274 break;
275 case 0x205:
276 regNum = MISCREG_MTRR_PHYS_MASK_2;
277 break;
278 case 0x206:
279 regNum = MISCREG_MTRR_PHYS_BASE_3;
280 break;
281 case 0x207:
282 regNum = MISCREG_MTRR_PHYS_MASK_3;
283 break;
284 case 0x208:
285 regNum = MISCREG_MTRR_PHYS_BASE_4;
286 break;
287 case 0x209:
288 regNum = MISCREG_MTRR_PHYS_MASK_4;
289 break;
290 case 0x20A:
291 regNum = MISCREG_MTRR_PHYS_BASE_5;
292 break;
293 case 0x20B:
294 regNum = MISCREG_MTRR_PHYS_MASK_5;
295 break;
296 case 0x20C:
297 regNum = MISCREG_MTRR_PHYS_BASE_6;
298 break;
299 case 0x20D:
300 regNum = MISCREG_MTRR_PHYS_MASK_6;
301 break;
302 case 0x20E:
303 regNum = MISCREG_MTRR_PHYS_BASE_7;
304 break;
305 case 0x20F:
306 regNum = MISCREG_MTRR_PHYS_MASK_7;
307 break;
308 case 0x250:
309 regNum = MISCREG_MTRR_FIX_64K_00000;
310 break;
311 case 0x258:
312 regNum = MISCREG_MTRR_FIX_16K_80000;
313 break;
314 case 0x259:
315 regNum = MISCREG_MTRR_FIX_16K_A0000;
316 break;
317 case 0x268:
318 regNum = MISCREG_MTRR_FIX_4K_C0000;
319 break;
320 case 0x269:
321 regNum = MISCREG_MTRR_FIX_4K_C8000;
322 break;
323 case 0x26A:
324 regNum = MISCREG_MTRR_FIX_4K_D0000;
325 break;
326 case 0x26B:
327 regNum = MISCREG_MTRR_FIX_4K_D8000;
328 break;
329 case 0x26C:
330 regNum = MISCREG_MTRR_FIX_4K_E0000;
331 break;
332 case 0x26D:
333 regNum = MISCREG_MTRR_FIX_4K_E8000;
334 break;
335 case 0x26E:
336 regNum = MISCREG_MTRR_FIX_4K_F0000;
337 break;
338 case 0x26F:
339 regNum = MISCREG_MTRR_FIX_4K_F8000;
340 break;
341 case 0x277:
342 regNum = MISCREG_PAT;
343 break;
344 case 0x2FF:
345 regNum = MISCREG_DEF_TYPE;
346 break;
347 case 0x400:
348 regNum = MISCREG_MC0_CTL;
349 break;
350 case 0x404:
351 regNum = MISCREG_MC1_CTL;
352 break;
353 case 0x408:
354 regNum = MISCREG_MC2_CTL;
355 break;
356 case 0x40C:
357 regNum = MISCREG_MC3_CTL;
358 break;
359 case 0x410:
360 regNum = MISCREG_MC4_CTL;
361 break;
362 case 0x414:
363 regNum = MISCREG_MC5_CTL;
364 break;
365 case 0x418:
366 regNum = MISCREG_MC6_CTL;
367 break;
368 case 0x41C:
369 regNum = MISCREG_MC7_CTL;
370 break;
371 case 0x401:
372 regNum = MISCREG_MC0_STATUS;
373 break;
374 case 0x405:
375 regNum = MISCREG_MC1_STATUS;
376 break;
377 case 0x409:
378 regNum = MISCREG_MC2_STATUS;
379 break;
380 case 0x40D:
381 regNum = MISCREG_MC3_STATUS;
382 break;
383 case 0x411:
384 regNum = MISCREG_MC4_STATUS;
385 break;
386 case 0x415:
387 regNum = MISCREG_MC5_STATUS;
388 break;
389 case 0x419:
390 regNum = MISCREG_MC6_STATUS;
391 break;
392 case 0x41D:
393 regNum = MISCREG_MC7_STATUS;
394 break;
395 case 0x402:
396 regNum = MISCREG_MC0_ADDR;
397 break;
398 case 0x406:
399 regNum = MISCREG_MC1_ADDR;
400 break;
401 case 0x40A:
402 regNum = MISCREG_MC2_ADDR;
403 break;
404 case 0x40E:
405 regNum = MISCREG_MC3_ADDR;
406 break;
407 case 0x412:
408 regNum = MISCREG_MC4_ADDR;
409 break;
410 case 0x416:
411 regNum = MISCREG_MC5_ADDR;
412 break;
413 case 0x41A:
414 regNum = MISCREG_MC6_ADDR;
415 break;
416 case 0x41E:
417 regNum = MISCREG_MC7_ADDR;
418 break;
419 case 0x403:
420 regNum = MISCREG_MC0_MISC;
421 break;
422 case 0x407:
423 regNum = MISCREG_MC1_MISC;
424 break;
425 case 0x40B:
426 regNum = MISCREG_MC2_MISC;
427 break;
428 case 0x40F:
429 regNum = MISCREG_MC3_MISC;
430 break;
431 case 0x413:
432 regNum = MISCREG_MC4_MISC;
433 break;
434 case 0x417:
435 regNum = MISCREG_MC5_MISC;
436 break;
437 case 0x41B:
438 regNum = MISCREG_MC6_MISC;
439 break;
440 case 0x41F:
441 regNum = MISCREG_MC7_MISC;
442 break;
443 case 0xC0000080:
444 regNum = MISCREG_EFER;
445 break;
446 case 0xC0000081:
447 regNum = MISCREG_STAR;
448 break;
449 case 0xC0000082:
450 regNum = MISCREG_LSTAR;
451 break;
452 case 0xC0000083:
453 regNum = MISCREG_CSTAR;
454 break;
455 case 0xC0000084:
456 regNum = MISCREG_SF_MASK;
457 break;
458 case 0xC0000100:
459 regNum = MISCREG_FS_BASE;
460 break;
461 case 0xC0000101:
462 regNum = MISCREG_GS_BASE;
463 break;
464 case 0xC0000102:
465 regNum = MISCREG_KERNEL_GS_BASE;
466 break;
467 case 0xC0000103:
468 regNum = MISCREG_TSC_AUX;
469 break;
470 case 0xC0010000:
471 regNum = MISCREG_PERF_EVT_SEL0;
472 break;
473 case 0xC0010001:
474 regNum = MISCREG_PERF_EVT_SEL1;
475 break;
476 case 0xC0010002:
477 regNum = MISCREG_PERF_EVT_SEL2;
478 break;
479 case 0xC0010003:
480 regNum = MISCREG_PERF_EVT_SEL3;
481 break;
482 case 0xC0010004:
483 regNum = MISCREG_PERF_EVT_CTR0;
484 break;
485 case 0xC0010005:
486 regNum = MISCREG_PERF_EVT_CTR1;
487 break;
488 case 0xC0010006:
489 regNum = MISCREG_PERF_EVT_CTR2;
490 break;
491 case 0xC0010007:
492 regNum = MISCREG_PERF_EVT_CTR3;
493 break;
494 case 0xC0010010:
495 regNum = MISCREG_SYSCFG;
496 break;
497 case 0xC0010016:
498 regNum = MISCREG_IORR_BASE0;
499 break;
500 case 0xC0010017:
501 regNum = MISCREG_IORR_BASE1;
502 break;
503 case 0xC0010018:
504 regNum = MISCREG_IORR_MASK0;
505 break;
506 case 0xC0010019:
507 regNum = MISCREG_IORR_MASK1;
508 break;
509 case 0xC001001A:
510 regNum = MISCREG_TOP_MEM;
511 break;
512 case 0xC001001D:
513 regNum = MISCREG_TOP_MEM2;
514 break;
515 case 0xC0010114:
516 regNum = MISCREG_VM_CR;
517 break;
518 case 0xC0010115:
519 regNum = MISCREG_IGNNE;
520 break;
521 case 0xC0010116:
522 regNum = MISCREG_SMM_CTL;
523 break;
524 case 0xC0010117:
525 regNum = MISCREG_VM_HSAVE_PA;
526 break;
527 default:
528 return new GeneralProtection(0);
529 }
530 //The index is multiplied by the size of a MiscReg so that
531 //any memory dependence calculations will not see these as
532 //overlapping.
533 req->setPaddr(regNum * sizeof(MiscReg));
534 return NoFault;
535 } else if (prefix == IntAddrPrefixIO) {
536 // TODO If CPL > IOPL or in virtual mode, check the I/O permission
537 // bitmap in the TSS.
538
539 Addr IOPort = vaddr & ~IntAddrPrefixMask;
540 // Make sure the address fits in the expected 16 bit IO address
541 // space.
542 assert(!(IOPort & ~0xFFFF));
543 if (IOPort == 0xCF8 && req->getSize() == 4) {
544 req->setMmapedIpr(true);
545 req->setPaddr(MISCREG_PCI_CONFIG_ADDRESS * sizeof(MiscReg));
546 } else if ((IOPort & ~mask(2)) == 0xCFC) {
547 Addr configAddress =
548 tc->readMiscRegNoEffect(MISCREG_PCI_CONFIG_ADDRESS);
549 if (bits(configAddress, 31, 31)) {
550 req->setPaddr(PhysAddrPrefixPciConfig |
551 mbits(configAddress, 30, 2) |
552 (IOPort & mask(2)));
553 }
554 } else {
555 req->setPaddr(PhysAddrPrefixIO | IOPort);
556 }
557 return NoFault;
558 } else {
559 panic("Access to unrecognized internal address space %#x.\n",
560 prefix);
561 }
562 }
563
564 // Get cr0. This will tell us how to do translation. We'll assume it was
565 // verified to be correct and consistent when set.
566 CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0);
567
568 // If protected mode has been enabled...
569 if (cr0.pe) {
570 DPRINTF(TLB, "In protected mode.\n");
571 Efer efer = tc->readMiscRegNoEffect(MISCREG_EFER);
572 SegAttr csAttr = tc->readMiscRegNoEffect(MISCREG_CS_ATTR);
573 // If we're not in 64-bit mode, do protection/limit checks
574 if (!efer.lma || !csAttr.longMode) {
575 DPRINTF(TLB, "Not in long mode. Checking segment protection.\n");
576 // Check for a NULL segment selector.
577 if (!tc->readMiscRegNoEffect(MISCREG_SEG_SEL(seg)))
578 return new GeneralProtection(0);
579 bool expandDown = false;
580 if (seg >= SEGMENT_REG_ES && seg <= SEGMENT_REG_HS) {
581 SegAttr attr = tc->readMiscRegNoEffect(MISCREG_SEG_ATTR(seg));
582 if (!attr.writable && write)
583 return new GeneralProtection(0);
584 if (!attr.readable && !write && !execute)
585 return new GeneralProtection(0);
586 expandDown = attr.expandDown;
587 }
588 Addr base = tc->readMiscRegNoEffect(MISCREG_SEG_BASE(seg));
589 Addr limit = tc->readMiscRegNoEffect(MISCREG_SEG_LIMIT(seg));
590 if (expandDown) {
591 DPRINTF(TLB, "Checking an expand down segment.\n");
592 // We don't have to worry about the access going around the
593 // end of memory because accesses will be broken up into
594 // pieces at boundaries aligned on sizes smaller than an
595 // entire address space. We do have to worry about the limit
596 // being less than the base.
597 if (limit < base) {
598 if (limit < vaddr + req->getSize() && vaddr < base)
599 return new GeneralProtection(0);
600 } else {
601 if (limit < vaddr + req->getSize())
602 return new GeneralProtection(0);
603 }
604 } else {
605 if (limit < base) {
606 if (vaddr <= limit || vaddr + req->getSize() >= base)
607 return new GeneralProtection(0);
608 } else {
609 if (vaddr <= limit && vaddr + req->getSize() >= base)
610 return new GeneralProtection(0);
611 }
612 }
613 }
614 // If paging is enabled, do the translation.
615 if (cr0.pg) {
616 DPRINTF(TLB, "Paging enabled.\n");
617 // The vaddr already has the segment base applied.
618 TlbEntry *entry = lookup(vaddr);
619 if (!entry) {
620 return new TlbFault(vaddr, write, execute);
621 } else {
622 // Do paging protection checks.
623 DPRINTF(TLB, "Entry found with paddr %#x, doing protection checks.\n", entry->paddr);
624 Addr paddr = entry->paddr | (vaddr & (entry->size-1));
625 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, paddr);
626 req->setPaddr(paddr);
627 }
628 } else {
629 //Use the address which already has segmentation applied.
630 DPRINTF(TLB, "Paging disabled.\n");
631 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr);
632 req->setPaddr(vaddr);
633 }
634 } else {
635 // Real mode
636 DPRINTF(TLB, "In real mode.\n");
637 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr);
638 req->setPaddr(vaddr);
639 }
640 // Check for an access to the local APIC
641#if FULL_SYSTEM
642 LocalApicBase localApicBase = tc->readMiscRegNoEffect(MISCREG_APIC_BASE);
643 Addr baseAddr = localApicBase.base * PageBytes;
644 Addr paddr = req->getPaddr();
645 if (baseAddr <= paddr && baseAddr + PageBytes > paddr) {
646 // The Intel developer's manuals say the below restrictions apply,
647 // but the linux kernel, because of a compiler optimization, breaks
648 // them.
649 /*
650 // Check alignment
651 if (paddr & ((32/8) - 1))
652 return new GeneralProtection(0);
653 // Check access size
654 if (req->getSize() != (32/8))
655 return new GeneralProtection(0);
656 */
657 // Force the access to be uncacheable.
658 req->setFlags(Request::UNCACHEABLE);
659 req->setPaddr(x86LocalAPICAddress(tc->contextId(), paddr - baseAddr));
660 }
661#endif
662 return NoFault;
663};
664
665Fault
| 194 bool write, bool execute)
195{
196 Addr vaddr = req->getVaddr();
197 DPRINTF(TLB, "Translating vaddr %#x.\n", vaddr);
198 uint32_t flags = req->getFlags();
199 bool storeCheck = flags & StoreCheck;
200
201 int seg = flags & mask(4);
202
203 //XXX Junk code to surpress the warning
204 if (storeCheck);
205
206 // If this is true, we're dealing with a request to read an internal
207 // value.
208 if (seg == SEGMENT_REG_MS) {
209 DPRINTF(TLB, "Addresses references internal memory.\n");
210 Addr prefix = (vaddr >> 3) & IntAddrPrefixMask;
211 if (prefix == IntAddrPrefixCPUID) {
212 panic("CPUID memory space not yet implemented!\n");
213 } else if (prefix == IntAddrPrefixMSR) {
214 vaddr = vaddr >> 3;
215 req->setMmapedIpr(true);
216 Addr regNum = 0;
217 switch (vaddr & ~IntAddrPrefixMask) {
218 case 0x10:
219 regNum = MISCREG_TSC;
220 break;
221 case 0x1B:
222 regNum = MISCREG_APIC_BASE;
223 break;
224 case 0xFE:
225 regNum = MISCREG_MTRRCAP;
226 break;
227 case 0x174:
228 regNum = MISCREG_SYSENTER_CS;
229 break;
230 case 0x175:
231 regNum = MISCREG_SYSENTER_ESP;
232 break;
233 case 0x176:
234 regNum = MISCREG_SYSENTER_EIP;
235 break;
236 case 0x179:
237 regNum = MISCREG_MCG_CAP;
238 break;
239 case 0x17A:
240 regNum = MISCREG_MCG_STATUS;
241 break;
242 case 0x17B:
243 regNum = MISCREG_MCG_CTL;
244 break;
245 case 0x1D9:
246 regNum = MISCREG_DEBUG_CTL_MSR;
247 break;
248 case 0x1DB:
249 regNum = MISCREG_LAST_BRANCH_FROM_IP;
250 break;
251 case 0x1DC:
252 regNum = MISCREG_LAST_BRANCH_TO_IP;
253 break;
254 case 0x1DD:
255 regNum = MISCREG_LAST_EXCEPTION_FROM_IP;
256 break;
257 case 0x1DE:
258 regNum = MISCREG_LAST_EXCEPTION_TO_IP;
259 break;
260 case 0x200:
261 regNum = MISCREG_MTRR_PHYS_BASE_0;
262 break;
263 case 0x201:
264 regNum = MISCREG_MTRR_PHYS_MASK_0;
265 break;
266 case 0x202:
267 regNum = MISCREG_MTRR_PHYS_BASE_1;
268 break;
269 case 0x203:
270 regNum = MISCREG_MTRR_PHYS_MASK_1;
271 break;
272 case 0x204:
273 regNum = MISCREG_MTRR_PHYS_BASE_2;
274 break;
275 case 0x205:
276 regNum = MISCREG_MTRR_PHYS_MASK_2;
277 break;
278 case 0x206:
279 regNum = MISCREG_MTRR_PHYS_BASE_3;
280 break;
281 case 0x207:
282 regNum = MISCREG_MTRR_PHYS_MASK_3;
283 break;
284 case 0x208:
285 regNum = MISCREG_MTRR_PHYS_BASE_4;
286 break;
287 case 0x209:
288 regNum = MISCREG_MTRR_PHYS_MASK_4;
289 break;
290 case 0x20A:
291 regNum = MISCREG_MTRR_PHYS_BASE_5;
292 break;
293 case 0x20B:
294 regNum = MISCREG_MTRR_PHYS_MASK_5;
295 break;
296 case 0x20C:
297 regNum = MISCREG_MTRR_PHYS_BASE_6;
298 break;
299 case 0x20D:
300 regNum = MISCREG_MTRR_PHYS_MASK_6;
301 break;
302 case 0x20E:
303 regNum = MISCREG_MTRR_PHYS_BASE_7;
304 break;
305 case 0x20F:
306 regNum = MISCREG_MTRR_PHYS_MASK_7;
307 break;
308 case 0x250:
309 regNum = MISCREG_MTRR_FIX_64K_00000;
310 break;
311 case 0x258:
312 regNum = MISCREG_MTRR_FIX_16K_80000;
313 break;
314 case 0x259:
315 regNum = MISCREG_MTRR_FIX_16K_A0000;
316 break;
317 case 0x268:
318 regNum = MISCREG_MTRR_FIX_4K_C0000;
319 break;
320 case 0x269:
321 regNum = MISCREG_MTRR_FIX_4K_C8000;
322 break;
323 case 0x26A:
324 regNum = MISCREG_MTRR_FIX_4K_D0000;
325 break;
326 case 0x26B:
327 regNum = MISCREG_MTRR_FIX_4K_D8000;
328 break;
329 case 0x26C:
330 regNum = MISCREG_MTRR_FIX_4K_E0000;
331 break;
332 case 0x26D:
333 regNum = MISCREG_MTRR_FIX_4K_E8000;
334 break;
335 case 0x26E:
336 regNum = MISCREG_MTRR_FIX_4K_F0000;
337 break;
338 case 0x26F:
339 regNum = MISCREG_MTRR_FIX_4K_F8000;
340 break;
341 case 0x277:
342 regNum = MISCREG_PAT;
343 break;
344 case 0x2FF:
345 regNum = MISCREG_DEF_TYPE;
346 break;
347 case 0x400:
348 regNum = MISCREG_MC0_CTL;
349 break;
350 case 0x404:
351 regNum = MISCREG_MC1_CTL;
352 break;
353 case 0x408:
354 regNum = MISCREG_MC2_CTL;
355 break;
356 case 0x40C:
357 regNum = MISCREG_MC3_CTL;
358 break;
359 case 0x410:
360 regNum = MISCREG_MC4_CTL;
361 break;
362 case 0x414:
363 regNum = MISCREG_MC5_CTL;
364 break;
365 case 0x418:
366 regNum = MISCREG_MC6_CTL;
367 break;
368 case 0x41C:
369 regNum = MISCREG_MC7_CTL;
370 break;
371 case 0x401:
372 regNum = MISCREG_MC0_STATUS;
373 break;
374 case 0x405:
375 regNum = MISCREG_MC1_STATUS;
376 break;
377 case 0x409:
378 regNum = MISCREG_MC2_STATUS;
379 break;
380 case 0x40D:
381 regNum = MISCREG_MC3_STATUS;
382 break;
383 case 0x411:
384 regNum = MISCREG_MC4_STATUS;
385 break;
386 case 0x415:
387 regNum = MISCREG_MC5_STATUS;
388 break;
389 case 0x419:
390 regNum = MISCREG_MC6_STATUS;
391 break;
392 case 0x41D:
393 regNum = MISCREG_MC7_STATUS;
394 break;
395 case 0x402:
396 regNum = MISCREG_MC0_ADDR;
397 break;
398 case 0x406:
399 regNum = MISCREG_MC1_ADDR;
400 break;
401 case 0x40A:
402 regNum = MISCREG_MC2_ADDR;
403 break;
404 case 0x40E:
405 regNum = MISCREG_MC3_ADDR;
406 break;
407 case 0x412:
408 regNum = MISCREG_MC4_ADDR;
409 break;
410 case 0x416:
411 regNum = MISCREG_MC5_ADDR;
412 break;
413 case 0x41A:
414 regNum = MISCREG_MC6_ADDR;
415 break;
416 case 0x41E:
417 regNum = MISCREG_MC7_ADDR;
418 break;
419 case 0x403:
420 regNum = MISCREG_MC0_MISC;
421 break;
422 case 0x407:
423 regNum = MISCREG_MC1_MISC;
424 break;
425 case 0x40B:
426 regNum = MISCREG_MC2_MISC;
427 break;
428 case 0x40F:
429 regNum = MISCREG_MC3_MISC;
430 break;
431 case 0x413:
432 regNum = MISCREG_MC4_MISC;
433 break;
434 case 0x417:
435 regNum = MISCREG_MC5_MISC;
436 break;
437 case 0x41B:
438 regNum = MISCREG_MC6_MISC;
439 break;
440 case 0x41F:
441 regNum = MISCREG_MC7_MISC;
442 break;
443 case 0xC0000080:
444 regNum = MISCREG_EFER;
445 break;
446 case 0xC0000081:
447 regNum = MISCREG_STAR;
448 break;
449 case 0xC0000082:
450 regNum = MISCREG_LSTAR;
451 break;
452 case 0xC0000083:
453 regNum = MISCREG_CSTAR;
454 break;
455 case 0xC0000084:
456 regNum = MISCREG_SF_MASK;
457 break;
458 case 0xC0000100:
459 regNum = MISCREG_FS_BASE;
460 break;
461 case 0xC0000101:
462 regNum = MISCREG_GS_BASE;
463 break;
464 case 0xC0000102:
465 regNum = MISCREG_KERNEL_GS_BASE;
466 break;
467 case 0xC0000103:
468 regNum = MISCREG_TSC_AUX;
469 break;
470 case 0xC0010000:
471 regNum = MISCREG_PERF_EVT_SEL0;
472 break;
473 case 0xC0010001:
474 regNum = MISCREG_PERF_EVT_SEL1;
475 break;
476 case 0xC0010002:
477 regNum = MISCREG_PERF_EVT_SEL2;
478 break;
479 case 0xC0010003:
480 regNum = MISCREG_PERF_EVT_SEL3;
481 break;
482 case 0xC0010004:
483 regNum = MISCREG_PERF_EVT_CTR0;
484 break;
485 case 0xC0010005:
486 regNum = MISCREG_PERF_EVT_CTR1;
487 break;
488 case 0xC0010006:
489 regNum = MISCREG_PERF_EVT_CTR2;
490 break;
491 case 0xC0010007:
492 regNum = MISCREG_PERF_EVT_CTR3;
493 break;
494 case 0xC0010010:
495 regNum = MISCREG_SYSCFG;
496 break;
497 case 0xC0010016:
498 regNum = MISCREG_IORR_BASE0;
499 break;
500 case 0xC0010017:
501 regNum = MISCREG_IORR_BASE1;
502 break;
503 case 0xC0010018:
504 regNum = MISCREG_IORR_MASK0;
505 break;
506 case 0xC0010019:
507 regNum = MISCREG_IORR_MASK1;
508 break;
509 case 0xC001001A:
510 regNum = MISCREG_TOP_MEM;
511 break;
512 case 0xC001001D:
513 regNum = MISCREG_TOP_MEM2;
514 break;
515 case 0xC0010114:
516 regNum = MISCREG_VM_CR;
517 break;
518 case 0xC0010115:
519 regNum = MISCREG_IGNNE;
520 break;
521 case 0xC0010116:
522 regNum = MISCREG_SMM_CTL;
523 break;
524 case 0xC0010117:
525 regNum = MISCREG_VM_HSAVE_PA;
526 break;
527 default:
528 return new GeneralProtection(0);
529 }
530 //The index is multiplied by the size of a MiscReg so that
531 //any memory dependence calculations will not see these as
532 //overlapping.
533 req->setPaddr(regNum * sizeof(MiscReg));
534 return NoFault;
535 } else if (prefix == IntAddrPrefixIO) {
536 // TODO If CPL > IOPL or in virtual mode, check the I/O permission
537 // bitmap in the TSS.
538
539 Addr IOPort = vaddr & ~IntAddrPrefixMask;
540 // Make sure the address fits in the expected 16 bit IO address
541 // space.
542 assert(!(IOPort & ~0xFFFF));
543 if (IOPort == 0xCF8 && req->getSize() == 4) {
544 req->setMmapedIpr(true);
545 req->setPaddr(MISCREG_PCI_CONFIG_ADDRESS * sizeof(MiscReg));
546 } else if ((IOPort & ~mask(2)) == 0xCFC) {
547 Addr configAddress =
548 tc->readMiscRegNoEffect(MISCREG_PCI_CONFIG_ADDRESS);
549 if (bits(configAddress, 31, 31)) {
550 req->setPaddr(PhysAddrPrefixPciConfig |
551 mbits(configAddress, 30, 2) |
552 (IOPort & mask(2)));
553 }
554 } else {
555 req->setPaddr(PhysAddrPrefixIO | IOPort);
556 }
557 return NoFault;
558 } else {
559 panic("Access to unrecognized internal address space %#x.\n",
560 prefix);
561 }
562 }
563
564 // Get cr0. This will tell us how to do translation. We'll assume it was
565 // verified to be correct and consistent when set.
566 CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0);
567
568 // If protected mode has been enabled...
569 if (cr0.pe) {
570 DPRINTF(TLB, "In protected mode.\n");
571 Efer efer = tc->readMiscRegNoEffect(MISCREG_EFER);
572 SegAttr csAttr = tc->readMiscRegNoEffect(MISCREG_CS_ATTR);
573 // If we're not in 64-bit mode, do protection/limit checks
574 if (!efer.lma || !csAttr.longMode) {
575 DPRINTF(TLB, "Not in long mode. Checking segment protection.\n");
576 // Check for a NULL segment selector.
577 if (!tc->readMiscRegNoEffect(MISCREG_SEG_SEL(seg)))
578 return new GeneralProtection(0);
579 bool expandDown = false;
580 if (seg >= SEGMENT_REG_ES && seg <= SEGMENT_REG_HS) {
581 SegAttr attr = tc->readMiscRegNoEffect(MISCREG_SEG_ATTR(seg));
582 if (!attr.writable && write)
583 return new GeneralProtection(0);
584 if (!attr.readable && !write && !execute)
585 return new GeneralProtection(0);
586 expandDown = attr.expandDown;
587 }
588 Addr base = tc->readMiscRegNoEffect(MISCREG_SEG_BASE(seg));
589 Addr limit = tc->readMiscRegNoEffect(MISCREG_SEG_LIMIT(seg));
590 if (expandDown) {
591 DPRINTF(TLB, "Checking an expand down segment.\n");
592 // We don't have to worry about the access going around the
593 // end of memory because accesses will be broken up into
594 // pieces at boundaries aligned on sizes smaller than an
595 // entire address space. We do have to worry about the limit
596 // being less than the base.
597 if (limit < base) {
598 if (limit < vaddr + req->getSize() && vaddr < base)
599 return new GeneralProtection(0);
600 } else {
601 if (limit < vaddr + req->getSize())
602 return new GeneralProtection(0);
603 }
604 } else {
605 if (limit < base) {
606 if (vaddr <= limit || vaddr + req->getSize() >= base)
607 return new GeneralProtection(0);
608 } else {
609 if (vaddr <= limit && vaddr + req->getSize() >= base)
610 return new GeneralProtection(0);
611 }
612 }
613 }
614 // If paging is enabled, do the translation.
615 if (cr0.pg) {
616 DPRINTF(TLB, "Paging enabled.\n");
617 // The vaddr already has the segment base applied.
618 TlbEntry *entry = lookup(vaddr);
619 if (!entry) {
620 return new TlbFault(vaddr, write, execute);
621 } else {
622 // Do paging protection checks.
623 DPRINTF(TLB, "Entry found with paddr %#x, doing protection checks.\n", entry->paddr);
624 Addr paddr = entry->paddr | (vaddr & (entry->size-1));
625 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, paddr);
626 req->setPaddr(paddr);
627 }
628 } else {
629 //Use the address which already has segmentation applied.
630 DPRINTF(TLB, "Paging disabled.\n");
631 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr);
632 req->setPaddr(vaddr);
633 }
634 } else {
635 // Real mode
636 DPRINTF(TLB, "In real mode.\n");
637 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr);
638 req->setPaddr(vaddr);
639 }
640 // Check for an access to the local APIC
641#if FULL_SYSTEM
642 LocalApicBase localApicBase = tc->readMiscRegNoEffect(MISCREG_APIC_BASE);
643 Addr baseAddr = localApicBase.base * PageBytes;
644 Addr paddr = req->getPaddr();
645 if (baseAddr <= paddr && baseAddr + PageBytes > paddr) {
646 // The Intel developer's manuals say the below restrictions apply,
647 // but the linux kernel, because of a compiler optimization, breaks
648 // them.
649 /*
650 // Check alignment
651 if (paddr & ((32/8) - 1))
652 return new GeneralProtection(0);
653 // Check access size
654 if (req->getSize() != (32/8))
655 return new GeneralProtection(0);
656 */
657 // Force the access to be uncacheable.
658 req->setFlags(Request::UNCACHEABLE);
659 req->setPaddr(x86LocalAPICAddress(tc->contextId(), paddr - baseAddr));
660 }
661#endif
662 return NoFault;
663};
664
665Fault
|
666DTB::translateAtomic(RequestPtr &req, ThreadContext *tc, bool write)
| 666DTB::translateAtomic(RequestPtr req, ThreadContext *tc, bool write)
|
667{
668 return TLB::translateAtomic<FakeDTLBFault>(req, tc, write, false);
669}
670
| 667{
668 return TLB::translateAtomic<FakeDTLBFault>(req, tc, write, false);
669}
670
|
| 671void
672DTB::translateTiming(RequestPtr req, ThreadContext *tc,
673 Translation *translation, bool write)
674{
675 assert(translation);
676 translation->finish(translateAtomic(req, tc, write), req, tc, write);
677}
678
|
671Fault
| 679Fault
|
672ITB::translateAtomic(RequestPtr &req, ThreadContext *tc)
| 680ITB::translateAtomic(RequestPtr req, ThreadContext *tc)
|
673{
674 return TLB::translateAtomic<FakeITLBFault>(req, tc, false, true);
675}
676
| 681{
682 return TLB::translateAtomic<FakeITLBFault>(req, tc, false, true);
683}
684
|
| 685void
686ITB::translateTiming(RequestPtr req, ThreadContext *tc,
687 Translation *translation)
688{
689 assert(translation);
690 translation->finish(translateAtomic(req, tc), req, tc, false);
691}
692
|
677#if FULL_SYSTEM
678
679Tick
680DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
681{
682 return tc->getCpuPtr()->ticks(1);
683}
684
685Tick
686DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
687{
688 return tc->getCpuPtr()->ticks(1);
689}
690
691#endif
692
693void
694TLB::serialize(std::ostream &os)
695{
696}
697
698void
699TLB::unserialize(Checkpoint *cp, const std::string §ion)
700{
701}
702
703void
704DTB::serialize(std::ostream &os)
705{
706 TLB::serialize(os);
707}
708
709void
710DTB::unserialize(Checkpoint *cp, const std::string §ion)
711{
712 TLB::unserialize(cp, section);
713}
714
715/* end namespace X86ISA */ }
716
717X86ISA::ITB *
718X86ITBParams::create()
719{
720 return new X86ISA::ITB(this);
721}
722
723X86ISA::DTB *
724X86DTBParams::create()
725{
726 return new X86ISA::DTB(this);
727}
| 693#if FULL_SYSTEM
694
695Tick
696DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
697{
698 return tc->getCpuPtr()->ticks(1);
699}
700
701Tick
702DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
703{
704 return tc->getCpuPtr()->ticks(1);
705}
706
707#endif
708
709void
710TLB::serialize(std::ostream &os)
711{
712}
713
714void
715TLB::unserialize(Checkpoint *cp, const std::string §ion)
716{
717}
718
719void
720DTB::serialize(std::ostream &os)
721{
722 TLB::serialize(os);
723}
724
725void
726DTB::unserialize(Checkpoint *cp, const std::string §ion)
727{
728 TLB::unserialize(cp, section);
729}
730
731/* end namespace X86ISA */ }
732
733X86ISA::ITB *
734X86ITBParams::create()
735{
736 return new X86ISA::ITB(this);
737}
738
739X86ISA::DTB *
740X86DTBParams::create()
741{
742 return new X86ISA::DTB(this);
743}
|