1/*
2 * Copyright (c) 2007-2008 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * Redistribution and use of this software in source and binary forms,
6 * with or without modification, are permitted provided that the
7 * following conditions are met:
8 *
9 * The software must be used only for Non-Commercial Use which means any
10 * use which is NOT directed to receiving any direct monetary
11 * compensation for, or commercial advantage from such use. Illustrative
12 * examples of non-commercial use are academic research, personal study,
13 * teaching, education and corporate research & development.
14 * Illustrative examples of commercial use are distributing products for
15 * commercial advantage and providing services using the software for
16 * commercial advantage.
17 *
18 * If you wish to use this software or functionality therein that may be
19 * covered by patents for commercial use, please contact:
20 * Director of Intellectual Property Licensing
21 * Office of Strategy and Technology
22 * Hewlett-Packard Company
23 * 1501 Page Mill Road
24 * Palo Alto, California 94304
25 *
26 * Redistributions of source code must retain the above copyright notice,
27 * this list of conditions and the following disclaimer. Redistributions
28 * in binary form must reproduce the above copyright notice, this list of
29 * conditions and the following disclaimer in the documentation and/or
30 * other materials provided with the distribution. Neither the name of
31 * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
32 * contributors may be used to endorse or promote products derived from
33 * this software without specific prior written permission. No right of
34 * sublicense is granted herewith. Derivatives of the software and
35 * output created using the software may be prepared, but only for
36 * Non-Commercial Uses. Derivatives of the software may be shared with
37 * others provided: (i) the others agree to abide by the list of
38 * conditions herein which includes the Non-Commercial Use restrictions;
39 * and (ii) such Derivatives of the software include the above copyright
40 * notice to acknowledge the contribution from this software where
41 * applicable, this list of conditions and the disclaimer below.
42 *
43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
46 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
47 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
49 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 *
55 * Authors: Gabe Black
56 */
57
58#include <cstring>
59
60#include "config/full_system.hh"
61
62#include "arch/x86/pagetable.hh"
63#include "arch/x86/tlb.hh"
64#include "arch/x86/x86_traits.hh"
65#include "base/bitfield.hh"
66#include "base/trace.hh"
67#include "config/full_system.hh"
68#include "cpu/thread_context.hh"
69#include "cpu/base.hh"
70#include "mem/packet_access.hh"
71#include "mem/request.hh"
72
73#if FULL_SYSTEM
74#include "arch/x86/pagetable_walker.hh"
75#endif
76
77namespace X86ISA {
78
79TLB::TLB(const Params *p) : BaseTLB(p), configAddress(0), size(p->size)
80{
81 tlb = new TlbEntry[size];
82 std::memset(tlb, 0, sizeof(TlbEntry) * size);
83
84 for (int x = 0; x < size; x++)
85 freeList.push_back(&tlb[x]);
86
87#if FULL_SYSTEM
88 walker = p->walker;
89 walker->setTLB(this);
90#endif
91}
92
93void
94TLB::insert(Addr vpn, TlbEntry &entry)
95{
96 //TODO Deal with conflicting entries
97
98 TlbEntry *newEntry = NULL;
99 if (!freeList.empty()) {
100 newEntry = freeList.front();
101 freeList.pop_front();
102 } else {
103 newEntry = entryList.back();
104 entryList.pop_back();
105 }
106 *newEntry = entry;
107 newEntry->vaddr = vpn;
108 entryList.push_front(newEntry);
109}
110
111TLB::EntryList::iterator
112TLB::lookupIt(Addr va, bool update_lru)
113{
114 //TODO make this smarter at some point
115 EntryList::iterator entry;
116 for (entry = entryList.begin(); entry != entryList.end(); entry++) {
117 if ((*entry)->vaddr <= va && (*entry)->vaddr + (*entry)->size > va) {
118 DPRINTF(TLB, "Matched vaddr %#x to entry starting at %#x "
119 "with size %#x.\n", va, (*entry)->vaddr, (*entry)->size);
120 if (update_lru) {
121 entryList.push_front(*entry);
122 entryList.erase(entry);
123 entry = entryList.begin();
124 }
125 break;
126 }
127 }
128 return entry;
129}
130
131TlbEntry *
132TLB::lookup(Addr va, bool update_lru)
133{
134 EntryList::iterator entry = lookupIt(va, update_lru);
135 if (entry == entryList.end())
136 return NULL;
137 else
138 return *entry;
139}
140
141#if FULL_SYSTEM
142void
143TLB::walk(ThreadContext * _tc, Addr vaddr)
144{
145 walker->start(_tc, vaddr);
146}
147#endif
148
149void
150TLB::invalidateAll()
151{
152 DPRINTF(TLB, "Invalidating all entries.\n");
153 while (!entryList.empty()) {
154 TlbEntry *entry = entryList.front();
155 entryList.pop_front();
156 freeList.push_back(entry);
157 }
158}
159
160void
161TLB::setConfigAddress(uint32_t addr)
162{
163 configAddress = addr;
164}
165
166void
167TLB::invalidateNonGlobal()
168{
169 DPRINTF(TLB, "Invalidating all non global entries.\n");
170 EntryList::iterator entryIt;
171 for (entryIt = entryList.begin(); entryIt != entryList.end();) {
172 if (!(*entryIt)->global) {
173 freeList.push_back(*entryIt);
174 entryList.erase(entryIt++);
175 } else {
176 entryIt++;
177 }
178 }
179}
180
181void
182TLB::demapPage(Addr va, uint64_t asn)
183{
184 EntryList::iterator entry = lookupIt(va, false);
185 if (entry != entryList.end()) {
186 freeList.push_back(*entry);
187 entryList.erase(entry);
188 }
189}
190
191template<class TlbFault>
192Fault
193TLB::translate(RequestPtr &req, ThreadContext *tc, bool write, bool execute)
194{
195 Addr vaddr = req->getVaddr();
196 DPRINTF(TLB, "Translating vaddr %#x.\n", vaddr);
197 uint32_t flags = req->getFlags();
198 bool storeCheck = flags & StoreCheck;
199
200 int seg = flags & mask(4);
201
202 //XXX Junk code to surpress the warning
203 if (storeCheck);
204
205 // If this is true, we're dealing with a request to read an internal
206 // value.
207 if (seg == SEGMENT_REG_MS) {
208 DPRINTF(TLB, "Addresses references internal memory.\n");
209 Addr prefix = (vaddr >> 3) & IntAddrPrefixMask;
210 if (prefix == IntAddrPrefixCPUID) {
211 panic("CPUID memory space not yet implemented!\n");
212 } else if (prefix == IntAddrPrefixMSR) {
213 vaddr = vaddr >> 3;
214 req->setMmapedIpr(true);
215 Addr regNum = 0;
216 switch (vaddr & ~IntAddrPrefixMask) {
217 case 0x10:
218 regNum = MISCREG_TSC;
219 break;
220 case 0x1B:
221 regNum = MISCREG_APIC_BASE;
222 break;
223 case 0xFE:
224 regNum = MISCREG_MTRRCAP;
225 break;
226 case 0x174:
227 regNum = MISCREG_SYSENTER_CS;
228 break;
229 case 0x175:
230 regNum = MISCREG_SYSENTER_ESP;
231 break;
232 case 0x176:
233 regNum = MISCREG_SYSENTER_EIP;
234 break;
235 case 0x179:
236 regNum = MISCREG_MCG_CAP;
237 break;
238 case 0x17A:
239 regNum = MISCREG_MCG_STATUS;
240 break;
241 case 0x17B:
242 regNum = MISCREG_MCG_CTL;
243 break;
244 case 0x1D9:
245 regNum = MISCREG_DEBUG_CTL_MSR;
246 break;
247 case 0x1DB:
248 regNum = MISCREG_LAST_BRANCH_FROM_IP;
249 break;
250 case 0x1DC:
251 regNum = MISCREG_LAST_BRANCH_TO_IP;
252 break;
253 case 0x1DD:
254 regNum = MISCREG_LAST_EXCEPTION_FROM_IP;
255 break;
256 case 0x1DE:
257 regNum = MISCREG_LAST_EXCEPTION_TO_IP;
258 break;
259 case 0x200:
260 regNum = MISCREG_MTRR_PHYS_BASE_0;
261 break;
262 case 0x201:
263 regNum = MISCREG_MTRR_PHYS_MASK_0;
264 break;
265 case 0x202:
266 regNum = MISCREG_MTRR_PHYS_BASE_1;
267 break;
268 case 0x203:
269 regNum = MISCREG_MTRR_PHYS_MASK_1;
270 break;
271 case 0x204:
272 regNum = MISCREG_MTRR_PHYS_BASE_2;
273 break;
274 case 0x205:
275 regNum = MISCREG_MTRR_PHYS_MASK_2;
276 break;
277 case 0x206:
278 regNum = MISCREG_MTRR_PHYS_BASE_3;
279 break;
280 case 0x207:
281 regNum = MISCREG_MTRR_PHYS_MASK_3;
282 break;
283 case 0x208:
284 regNum = MISCREG_MTRR_PHYS_BASE_4;
285 break;
286 case 0x209:
287 regNum = MISCREG_MTRR_PHYS_MASK_4;
288 break;
289 case 0x20A:
290 regNum = MISCREG_MTRR_PHYS_BASE_5;
291 break;
292 case 0x20B:
293 regNum = MISCREG_MTRR_PHYS_MASK_5;
294 break;
295 case 0x20C:
296 regNum = MISCREG_MTRR_PHYS_BASE_6;
297 break;
298 case 0x20D:
299 regNum = MISCREG_MTRR_PHYS_MASK_6;
300 break;
301 case 0x20E:
302 regNum = MISCREG_MTRR_PHYS_BASE_7;
303 break;
304 case 0x20F:
305 regNum = MISCREG_MTRR_PHYS_MASK_7;
306 break;
307 case 0x250:
308 regNum = MISCREG_MTRR_FIX_64K_00000;
309 break;
310 case 0x258:
311 regNum = MISCREG_MTRR_FIX_16K_80000;
312 break;
313 case 0x259:
314 regNum = MISCREG_MTRR_FIX_16K_A0000;
315 break;
316 case 0x268:
317 regNum = MISCREG_MTRR_FIX_4K_C0000;
318 break;
319 case 0x269:
320 regNum = MISCREG_MTRR_FIX_4K_C8000;
321 break;
322 case 0x26A:
323 regNum = MISCREG_MTRR_FIX_4K_D0000;
324 break;
325 case 0x26B:
326 regNum = MISCREG_MTRR_FIX_4K_D8000;
327 break;
328 case 0x26C:
329 regNum = MISCREG_MTRR_FIX_4K_E0000;
330 break;
331 case 0x26D:
332 regNum = MISCREG_MTRR_FIX_4K_E8000;
333 break;
334 case 0x26E:
335 regNum = MISCREG_MTRR_FIX_4K_F0000;
336 break;
337 case 0x26F:
338 regNum = MISCREG_MTRR_FIX_4K_F8000;
339 break;
340 case 0x277:
341 regNum = MISCREG_PAT;
342 break;
343 case 0x2FF:
344 regNum = MISCREG_DEF_TYPE;
345 break;
346 case 0x400:
347 regNum = MISCREG_MC0_CTL;
348 break;
349 case 0x404:
350 regNum = MISCREG_MC1_CTL;
351 break;
352 case 0x408:
353 regNum = MISCREG_MC2_CTL;
354 break;
355 case 0x40C:
356 regNum = MISCREG_MC3_CTL;
357 break;
358 case 0x410:
359 regNum = MISCREG_MC4_CTL;
360 break;
361 case 0x414:
362 regNum = MISCREG_MC5_CTL;
363 break;
364 case 0x418:
365 regNum = MISCREG_MC6_CTL;
366 break;
367 case 0x41C:
368 regNum = MISCREG_MC7_CTL;
369 break;
370 case 0x401:
371 regNum = MISCREG_MC0_STATUS;
372 break;
373 case 0x405:
374 regNum = MISCREG_MC1_STATUS;
375 break;
376 case 0x409:
377 regNum = MISCREG_MC2_STATUS;
378 break;
379 case 0x40D:
380 regNum = MISCREG_MC3_STATUS;
381 break;
382 case 0x411:
383 regNum = MISCREG_MC4_STATUS;
384 break;
385 case 0x415:
386 regNum = MISCREG_MC5_STATUS;
387 break;
388 case 0x419:
389 regNum = MISCREG_MC6_STATUS;
390 break;
391 case 0x41D:
392 regNum = MISCREG_MC7_STATUS;
393 break;
394 case 0x402:
395 regNum = MISCREG_MC0_ADDR;
396 break;
397 case 0x406:
398 regNum = MISCREG_MC1_ADDR;
399 break;
400 case 0x40A:
401 regNum = MISCREG_MC2_ADDR;
402 break;
403 case 0x40E:
404 regNum = MISCREG_MC3_ADDR;
405 break;
406 case 0x412:
407 regNum = MISCREG_MC4_ADDR;
408 break;
409 case 0x416:
410 regNum = MISCREG_MC5_ADDR;
411 break;
412 case 0x41A:
413 regNum = MISCREG_MC6_ADDR;
414 break;
415 case 0x41E:
416 regNum = MISCREG_MC7_ADDR;
417 break;
418 case 0x403:
419 regNum = MISCREG_MC0_MISC;
420 break;
421 case 0x407:
422 regNum = MISCREG_MC1_MISC;
423 break;
424 case 0x40B:
425 regNum = MISCREG_MC2_MISC;
426 break;
427 case 0x40F:
428 regNum = MISCREG_MC3_MISC;
429 break;
430 case 0x413:
431 regNum = MISCREG_MC4_MISC;
432 break;
433 case 0x417:
434 regNum = MISCREG_MC5_MISC;
435 break;
436 case 0x41B:
437 regNum = MISCREG_MC6_MISC;
438 break;
439 case 0x41F:
440 regNum = MISCREG_MC7_MISC;
441 break;
442 case 0xC0000080:
443 regNum = MISCREG_EFER;
444 break;
445 case 0xC0000081:
446 regNum = MISCREG_STAR;
447 break;
448 case 0xC0000082:
449 regNum = MISCREG_LSTAR;
450 break;
451 case 0xC0000083:
452 regNum = MISCREG_CSTAR;
453 break;
454 case 0xC0000084:
455 regNum = MISCREG_SF_MASK;
456 break;
457 case 0xC0000100:
458 regNum = MISCREG_FS_BASE;
459 break;
460 case 0xC0000101:
461 regNum = MISCREG_GS_BASE;
462 break;
463 case 0xC0000102:
464 regNum = MISCREG_KERNEL_GS_BASE;
465 break;
466 case 0xC0000103:
467 regNum = MISCREG_TSC_AUX;
468 break;
469 case 0xC0010000:
470 regNum = MISCREG_PERF_EVT_SEL0;
471 break;
472 case 0xC0010001:
473 regNum = MISCREG_PERF_EVT_SEL1;
474 break;
475 case 0xC0010002:
476 regNum = MISCREG_PERF_EVT_SEL2;
477 break;
478 case 0xC0010003:
479 regNum = MISCREG_PERF_EVT_SEL3;
480 break;
481 case 0xC0010004:
482 regNum = MISCREG_PERF_EVT_CTR0;
483 break;
484 case 0xC0010005:
485 regNum = MISCREG_PERF_EVT_CTR1;
486 break;
487 case 0xC0010006:
488 regNum = MISCREG_PERF_EVT_CTR2;
489 break;
490 case 0xC0010007:
491 regNum = MISCREG_PERF_EVT_CTR3;
492 break;
493 case 0xC0010010:
494 regNum = MISCREG_SYSCFG;
495 break;
496 case 0xC0010016:
497 regNum = MISCREG_IORR_BASE0;
498 break;
499 case 0xC0010017:
500 regNum = MISCREG_IORR_BASE1;
501 break;
502 case 0xC0010018:
503 regNum = MISCREG_IORR_MASK0;
504 break;
505 case 0xC0010019:
506 regNum = MISCREG_IORR_MASK1;
507 break;
508 case 0xC001001A:
509 regNum = MISCREG_TOP_MEM;
510 break;
511 case 0xC001001D:
512 regNum = MISCREG_TOP_MEM2;
513 break;
514 case 0xC0010114:
515 regNum = MISCREG_VM_CR;
516 break;
517 case 0xC0010115:
518 regNum = MISCREG_IGNNE;
519 break;
520 case 0xC0010116:
521 regNum = MISCREG_SMM_CTL;
522 break;
523 case 0xC0010117:
524 regNum = MISCREG_VM_HSAVE_PA;
525 break;
526 default:
527 return new GeneralProtection(0);
528 }
529 //The index is multiplied by the size of a MiscReg so that
530 //any memory dependence calculations will not see these as
531 //overlapping.
532 req->setPaddr(regNum * sizeof(MiscReg));
533 return NoFault;
534 } else if (prefix == IntAddrPrefixIO) {
535 // TODO If CPL > IOPL or in virtual mode, check the I/O permission
536 // bitmap in the TSS.
537
538 Addr IOPort = vaddr & ~IntAddrPrefixMask;
539 // Make sure the address fits in the expected 16 bit IO address
540 // space.
541 assert(!(IOPort & ~0xFFFF));
542 if (IOPort == 0xCF8 && req->getSize() == 4) {
543 req->setMmapedIpr(true);
544 req->setPaddr(MISCREG_PCI_CONFIG_ADDRESS * sizeof(MiscReg));
545 } else if ((IOPort & ~mask(2)) == 0xCFC) {
546 Addr configAddress =
547 tc->readMiscRegNoEffect(MISCREG_PCI_CONFIG_ADDRESS);
548 if (bits(configAddress, 31, 31)) {
549 req->setPaddr(PhysAddrPrefixPciConfig |
550 bits(configAddress, 30, 0));
551 }
552 } else {
553 req->setPaddr(PhysAddrPrefixIO | IOPort);
554 }
555 return NoFault;
556 } else {
557 panic("Access to unrecognized internal address space %#x.\n",
558 prefix);
559 }
560 }
561
562 // Get cr0. This will tell us how to do translation. We'll assume it was
563 // verified to be correct and consistent when set.
564 CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0);
565
566 // If protected mode has been enabled...
567 if (cr0.pe) {
568 DPRINTF(TLB, "In protected mode.\n");
569 Efer efer = tc->readMiscRegNoEffect(MISCREG_EFER);
570 SegAttr csAttr = tc->readMiscRegNoEffect(MISCREG_CS_ATTR);
571 // If we're not in 64-bit mode, do protection/limit checks
572 if (!efer.lma || !csAttr.longMode) {
573 DPRINTF(TLB, "Not in long mode. Checking segment protection.\n");
574 // Check for a NULL segment selector.
575 if (!tc->readMiscRegNoEffect(MISCREG_SEG_SEL(seg)))
576 return new GeneralProtection(0);
| 1/*
2 * Copyright (c) 2007-2008 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * Redistribution and use of this software in source and binary forms,
6 * with or without modification, are permitted provided that the
7 * following conditions are met:
8 *
9 * The software must be used only for Non-Commercial Use which means any
10 * use which is NOT directed to receiving any direct monetary
11 * compensation for, or commercial advantage from such use. Illustrative
12 * examples of non-commercial use are academic research, personal study,
13 * teaching, education and corporate research & development.
14 * Illustrative examples of commercial use are distributing products for
15 * commercial advantage and providing services using the software for
16 * commercial advantage.
17 *
18 * If you wish to use this software or functionality therein that may be
19 * covered by patents for commercial use, please contact:
20 * Director of Intellectual Property Licensing
21 * Office of Strategy and Technology
22 * Hewlett-Packard Company
23 * 1501 Page Mill Road
24 * Palo Alto, California 94304
25 *
26 * Redistributions of source code must retain the above copyright notice,
27 * this list of conditions and the following disclaimer. Redistributions
28 * in binary form must reproduce the above copyright notice, this list of
29 * conditions and the following disclaimer in the documentation and/or
30 * other materials provided with the distribution. Neither the name of
31 * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
32 * contributors may be used to endorse or promote products derived from
33 * this software without specific prior written permission. No right of
34 * sublicense is granted herewith. Derivatives of the software and
35 * output created using the software may be prepared, but only for
36 * Non-Commercial Uses. Derivatives of the software may be shared with
37 * others provided: (i) the others agree to abide by the list of
38 * conditions herein which includes the Non-Commercial Use restrictions;
39 * and (ii) such Derivatives of the software include the above copyright
40 * notice to acknowledge the contribution from this software where
41 * applicable, this list of conditions and the disclaimer below.
42 *
43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
46 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
47 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
49 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 *
55 * Authors: Gabe Black
56 */
57
58#include <cstring>
59
60#include "config/full_system.hh"
61
62#include "arch/x86/pagetable.hh"
63#include "arch/x86/tlb.hh"
64#include "arch/x86/x86_traits.hh"
65#include "base/bitfield.hh"
66#include "base/trace.hh"
67#include "config/full_system.hh"
68#include "cpu/thread_context.hh"
69#include "cpu/base.hh"
70#include "mem/packet_access.hh"
71#include "mem/request.hh"
72
73#if FULL_SYSTEM
74#include "arch/x86/pagetable_walker.hh"
75#endif
76
77namespace X86ISA {
78
79TLB::TLB(const Params *p) : BaseTLB(p), configAddress(0), size(p->size)
80{
81 tlb = new TlbEntry[size];
82 std::memset(tlb, 0, sizeof(TlbEntry) * size);
83
84 for (int x = 0; x < size; x++)
85 freeList.push_back(&tlb[x]);
86
87#if FULL_SYSTEM
88 walker = p->walker;
89 walker->setTLB(this);
90#endif
91}
92
93void
94TLB::insert(Addr vpn, TlbEntry &entry)
95{
96 //TODO Deal with conflicting entries
97
98 TlbEntry *newEntry = NULL;
99 if (!freeList.empty()) {
100 newEntry = freeList.front();
101 freeList.pop_front();
102 } else {
103 newEntry = entryList.back();
104 entryList.pop_back();
105 }
106 *newEntry = entry;
107 newEntry->vaddr = vpn;
108 entryList.push_front(newEntry);
109}
110
111TLB::EntryList::iterator
112TLB::lookupIt(Addr va, bool update_lru)
113{
114 //TODO make this smarter at some point
115 EntryList::iterator entry;
116 for (entry = entryList.begin(); entry != entryList.end(); entry++) {
117 if ((*entry)->vaddr <= va && (*entry)->vaddr + (*entry)->size > va) {
118 DPRINTF(TLB, "Matched vaddr %#x to entry starting at %#x "
119 "with size %#x.\n", va, (*entry)->vaddr, (*entry)->size);
120 if (update_lru) {
121 entryList.push_front(*entry);
122 entryList.erase(entry);
123 entry = entryList.begin();
124 }
125 break;
126 }
127 }
128 return entry;
129}
130
131TlbEntry *
132TLB::lookup(Addr va, bool update_lru)
133{
134 EntryList::iterator entry = lookupIt(va, update_lru);
135 if (entry == entryList.end())
136 return NULL;
137 else
138 return *entry;
139}
140
141#if FULL_SYSTEM
142void
143TLB::walk(ThreadContext * _tc, Addr vaddr)
144{
145 walker->start(_tc, vaddr);
146}
147#endif
148
149void
150TLB::invalidateAll()
151{
152 DPRINTF(TLB, "Invalidating all entries.\n");
153 while (!entryList.empty()) {
154 TlbEntry *entry = entryList.front();
155 entryList.pop_front();
156 freeList.push_back(entry);
157 }
158}
159
160void
161TLB::setConfigAddress(uint32_t addr)
162{
163 configAddress = addr;
164}
165
166void
167TLB::invalidateNonGlobal()
168{
169 DPRINTF(TLB, "Invalidating all non global entries.\n");
170 EntryList::iterator entryIt;
171 for (entryIt = entryList.begin(); entryIt != entryList.end();) {
172 if (!(*entryIt)->global) {
173 freeList.push_back(*entryIt);
174 entryList.erase(entryIt++);
175 } else {
176 entryIt++;
177 }
178 }
179}
180
181void
182TLB::demapPage(Addr va, uint64_t asn)
183{
184 EntryList::iterator entry = lookupIt(va, false);
185 if (entry != entryList.end()) {
186 freeList.push_back(*entry);
187 entryList.erase(entry);
188 }
189}
190
191template<class TlbFault>
192Fault
193TLB::translate(RequestPtr &req, ThreadContext *tc, bool write, bool execute)
194{
195 Addr vaddr = req->getVaddr();
196 DPRINTF(TLB, "Translating vaddr %#x.\n", vaddr);
197 uint32_t flags = req->getFlags();
198 bool storeCheck = flags & StoreCheck;
199
200 int seg = flags & mask(4);
201
202 //XXX Junk code to surpress the warning
203 if (storeCheck);
204
205 // If this is true, we're dealing with a request to read an internal
206 // value.
207 if (seg == SEGMENT_REG_MS) {
208 DPRINTF(TLB, "Addresses references internal memory.\n");
209 Addr prefix = (vaddr >> 3) & IntAddrPrefixMask;
210 if (prefix == IntAddrPrefixCPUID) {
211 panic("CPUID memory space not yet implemented!\n");
212 } else if (prefix == IntAddrPrefixMSR) {
213 vaddr = vaddr >> 3;
214 req->setMmapedIpr(true);
215 Addr regNum = 0;
216 switch (vaddr & ~IntAddrPrefixMask) {
217 case 0x10:
218 regNum = MISCREG_TSC;
219 break;
220 case 0x1B:
221 regNum = MISCREG_APIC_BASE;
222 break;
223 case 0xFE:
224 regNum = MISCREG_MTRRCAP;
225 break;
226 case 0x174:
227 regNum = MISCREG_SYSENTER_CS;
228 break;
229 case 0x175:
230 regNum = MISCREG_SYSENTER_ESP;
231 break;
232 case 0x176:
233 regNum = MISCREG_SYSENTER_EIP;
234 break;
235 case 0x179:
236 regNum = MISCREG_MCG_CAP;
237 break;
238 case 0x17A:
239 regNum = MISCREG_MCG_STATUS;
240 break;
241 case 0x17B:
242 regNum = MISCREG_MCG_CTL;
243 break;
244 case 0x1D9:
245 regNum = MISCREG_DEBUG_CTL_MSR;
246 break;
247 case 0x1DB:
248 regNum = MISCREG_LAST_BRANCH_FROM_IP;
249 break;
250 case 0x1DC:
251 regNum = MISCREG_LAST_BRANCH_TO_IP;
252 break;
253 case 0x1DD:
254 regNum = MISCREG_LAST_EXCEPTION_FROM_IP;
255 break;
256 case 0x1DE:
257 regNum = MISCREG_LAST_EXCEPTION_TO_IP;
258 break;
259 case 0x200:
260 regNum = MISCREG_MTRR_PHYS_BASE_0;
261 break;
262 case 0x201:
263 regNum = MISCREG_MTRR_PHYS_MASK_0;
264 break;
265 case 0x202:
266 regNum = MISCREG_MTRR_PHYS_BASE_1;
267 break;
268 case 0x203:
269 regNum = MISCREG_MTRR_PHYS_MASK_1;
270 break;
271 case 0x204:
272 regNum = MISCREG_MTRR_PHYS_BASE_2;
273 break;
274 case 0x205:
275 regNum = MISCREG_MTRR_PHYS_MASK_2;
276 break;
277 case 0x206:
278 regNum = MISCREG_MTRR_PHYS_BASE_3;
279 break;
280 case 0x207:
281 regNum = MISCREG_MTRR_PHYS_MASK_3;
282 break;
283 case 0x208:
284 regNum = MISCREG_MTRR_PHYS_BASE_4;
285 break;
286 case 0x209:
287 regNum = MISCREG_MTRR_PHYS_MASK_4;
288 break;
289 case 0x20A:
290 regNum = MISCREG_MTRR_PHYS_BASE_5;
291 break;
292 case 0x20B:
293 regNum = MISCREG_MTRR_PHYS_MASK_5;
294 break;
295 case 0x20C:
296 regNum = MISCREG_MTRR_PHYS_BASE_6;
297 break;
298 case 0x20D:
299 regNum = MISCREG_MTRR_PHYS_MASK_6;
300 break;
301 case 0x20E:
302 regNum = MISCREG_MTRR_PHYS_BASE_7;
303 break;
304 case 0x20F:
305 regNum = MISCREG_MTRR_PHYS_MASK_7;
306 break;
307 case 0x250:
308 regNum = MISCREG_MTRR_FIX_64K_00000;
309 break;
310 case 0x258:
311 regNum = MISCREG_MTRR_FIX_16K_80000;
312 break;
313 case 0x259:
314 regNum = MISCREG_MTRR_FIX_16K_A0000;
315 break;
316 case 0x268:
317 regNum = MISCREG_MTRR_FIX_4K_C0000;
318 break;
319 case 0x269:
320 regNum = MISCREG_MTRR_FIX_4K_C8000;
321 break;
322 case 0x26A:
323 regNum = MISCREG_MTRR_FIX_4K_D0000;
324 break;
325 case 0x26B:
326 regNum = MISCREG_MTRR_FIX_4K_D8000;
327 break;
328 case 0x26C:
329 regNum = MISCREG_MTRR_FIX_4K_E0000;
330 break;
331 case 0x26D:
332 regNum = MISCREG_MTRR_FIX_4K_E8000;
333 break;
334 case 0x26E:
335 regNum = MISCREG_MTRR_FIX_4K_F0000;
336 break;
337 case 0x26F:
338 regNum = MISCREG_MTRR_FIX_4K_F8000;
339 break;
340 case 0x277:
341 regNum = MISCREG_PAT;
342 break;
343 case 0x2FF:
344 regNum = MISCREG_DEF_TYPE;
345 break;
346 case 0x400:
347 regNum = MISCREG_MC0_CTL;
348 break;
349 case 0x404:
350 regNum = MISCREG_MC1_CTL;
351 break;
352 case 0x408:
353 regNum = MISCREG_MC2_CTL;
354 break;
355 case 0x40C:
356 regNum = MISCREG_MC3_CTL;
357 break;
358 case 0x410:
359 regNum = MISCREG_MC4_CTL;
360 break;
361 case 0x414:
362 regNum = MISCREG_MC5_CTL;
363 break;
364 case 0x418:
365 regNum = MISCREG_MC6_CTL;
366 break;
367 case 0x41C:
368 regNum = MISCREG_MC7_CTL;
369 break;
370 case 0x401:
371 regNum = MISCREG_MC0_STATUS;
372 break;
373 case 0x405:
374 regNum = MISCREG_MC1_STATUS;
375 break;
376 case 0x409:
377 regNum = MISCREG_MC2_STATUS;
378 break;
379 case 0x40D:
380 regNum = MISCREG_MC3_STATUS;
381 break;
382 case 0x411:
383 regNum = MISCREG_MC4_STATUS;
384 break;
385 case 0x415:
386 regNum = MISCREG_MC5_STATUS;
387 break;
388 case 0x419:
389 regNum = MISCREG_MC6_STATUS;
390 break;
391 case 0x41D:
392 regNum = MISCREG_MC7_STATUS;
393 break;
394 case 0x402:
395 regNum = MISCREG_MC0_ADDR;
396 break;
397 case 0x406:
398 regNum = MISCREG_MC1_ADDR;
399 break;
400 case 0x40A:
401 regNum = MISCREG_MC2_ADDR;
402 break;
403 case 0x40E:
404 regNum = MISCREG_MC3_ADDR;
405 break;
406 case 0x412:
407 regNum = MISCREG_MC4_ADDR;
408 break;
409 case 0x416:
410 regNum = MISCREG_MC5_ADDR;
411 break;
412 case 0x41A:
413 regNum = MISCREG_MC6_ADDR;
414 break;
415 case 0x41E:
416 regNum = MISCREG_MC7_ADDR;
417 break;
418 case 0x403:
419 regNum = MISCREG_MC0_MISC;
420 break;
421 case 0x407:
422 regNum = MISCREG_MC1_MISC;
423 break;
424 case 0x40B:
425 regNum = MISCREG_MC2_MISC;
426 break;
427 case 0x40F:
428 regNum = MISCREG_MC3_MISC;
429 break;
430 case 0x413:
431 regNum = MISCREG_MC4_MISC;
432 break;
433 case 0x417:
434 regNum = MISCREG_MC5_MISC;
435 break;
436 case 0x41B:
437 regNum = MISCREG_MC6_MISC;
438 break;
439 case 0x41F:
440 regNum = MISCREG_MC7_MISC;
441 break;
442 case 0xC0000080:
443 regNum = MISCREG_EFER;
444 break;
445 case 0xC0000081:
446 regNum = MISCREG_STAR;
447 break;
448 case 0xC0000082:
449 regNum = MISCREG_LSTAR;
450 break;
451 case 0xC0000083:
452 regNum = MISCREG_CSTAR;
453 break;
454 case 0xC0000084:
455 regNum = MISCREG_SF_MASK;
456 break;
457 case 0xC0000100:
458 regNum = MISCREG_FS_BASE;
459 break;
460 case 0xC0000101:
461 regNum = MISCREG_GS_BASE;
462 break;
463 case 0xC0000102:
464 regNum = MISCREG_KERNEL_GS_BASE;
465 break;
466 case 0xC0000103:
467 regNum = MISCREG_TSC_AUX;
468 break;
469 case 0xC0010000:
470 regNum = MISCREG_PERF_EVT_SEL0;
471 break;
472 case 0xC0010001:
473 regNum = MISCREG_PERF_EVT_SEL1;
474 break;
475 case 0xC0010002:
476 regNum = MISCREG_PERF_EVT_SEL2;
477 break;
478 case 0xC0010003:
479 regNum = MISCREG_PERF_EVT_SEL3;
480 break;
481 case 0xC0010004:
482 regNum = MISCREG_PERF_EVT_CTR0;
483 break;
484 case 0xC0010005:
485 regNum = MISCREG_PERF_EVT_CTR1;
486 break;
487 case 0xC0010006:
488 regNum = MISCREG_PERF_EVT_CTR2;
489 break;
490 case 0xC0010007:
491 regNum = MISCREG_PERF_EVT_CTR3;
492 break;
493 case 0xC0010010:
494 regNum = MISCREG_SYSCFG;
495 break;
496 case 0xC0010016:
497 regNum = MISCREG_IORR_BASE0;
498 break;
499 case 0xC0010017:
500 regNum = MISCREG_IORR_BASE1;
501 break;
502 case 0xC0010018:
503 regNum = MISCREG_IORR_MASK0;
504 break;
505 case 0xC0010019:
506 regNum = MISCREG_IORR_MASK1;
507 break;
508 case 0xC001001A:
509 regNum = MISCREG_TOP_MEM;
510 break;
511 case 0xC001001D:
512 regNum = MISCREG_TOP_MEM2;
513 break;
514 case 0xC0010114:
515 regNum = MISCREG_VM_CR;
516 break;
517 case 0xC0010115:
518 regNum = MISCREG_IGNNE;
519 break;
520 case 0xC0010116:
521 regNum = MISCREG_SMM_CTL;
522 break;
523 case 0xC0010117:
524 regNum = MISCREG_VM_HSAVE_PA;
525 break;
526 default:
527 return new GeneralProtection(0);
528 }
529 //The index is multiplied by the size of a MiscReg so that
530 //any memory dependence calculations will not see these as
531 //overlapping.
532 req->setPaddr(regNum * sizeof(MiscReg));
533 return NoFault;
534 } else if (prefix == IntAddrPrefixIO) {
535 // TODO If CPL > IOPL or in virtual mode, check the I/O permission
536 // bitmap in the TSS.
537
538 Addr IOPort = vaddr & ~IntAddrPrefixMask;
539 // Make sure the address fits in the expected 16 bit IO address
540 // space.
541 assert(!(IOPort & ~0xFFFF));
542 if (IOPort == 0xCF8 && req->getSize() == 4) {
543 req->setMmapedIpr(true);
544 req->setPaddr(MISCREG_PCI_CONFIG_ADDRESS * sizeof(MiscReg));
545 } else if ((IOPort & ~mask(2)) == 0xCFC) {
546 Addr configAddress =
547 tc->readMiscRegNoEffect(MISCREG_PCI_CONFIG_ADDRESS);
548 if (bits(configAddress, 31, 31)) {
549 req->setPaddr(PhysAddrPrefixPciConfig |
550 bits(configAddress, 30, 0));
551 }
552 } else {
553 req->setPaddr(PhysAddrPrefixIO | IOPort);
554 }
555 return NoFault;
556 } else {
557 panic("Access to unrecognized internal address space %#x.\n",
558 prefix);
559 }
560 }
561
562 // Get cr0. This will tell us how to do translation. We'll assume it was
563 // verified to be correct and consistent when set.
564 CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0);
565
566 // If protected mode has been enabled...
567 if (cr0.pe) {
568 DPRINTF(TLB, "In protected mode.\n");
569 Efer efer = tc->readMiscRegNoEffect(MISCREG_EFER);
570 SegAttr csAttr = tc->readMiscRegNoEffect(MISCREG_CS_ATTR);
571 // If we're not in 64-bit mode, do protection/limit checks
572 if (!efer.lma || !csAttr.longMode) {
573 DPRINTF(TLB, "Not in long mode. Checking segment protection.\n");
574 // Check for a NULL segment selector.
575 if (!tc->readMiscRegNoEffect(MISCREG_SEG_SEL(seg)))
576 return new GeneralProtection(0);
|
585 DPRINTF(TLB, "Checking an expand down segment.\n");
586 // We don't have to worry about the access going around the
587 // end of memory because accesses will be broken up into
588 // pieces at boundaries aligned on sizes smaller than an
589 // entire address space. We do have to worry about the limit
590 // being less than the base.
591 if (limit < base) {
592 if (limit < vaddr + req->getSize() && vaddr < base)
593 return new GeneralProtection(0);
594 } else {
595 if (limit < vaddr + req->getSize())
596 return new GeneralProtection(0);
597 }
598 } else {
599 if (limit < base) {
600 if (vaddr <= limit || vaddr + req->getSize() >= base)
601 return new GeneralProtection(0);
602 } else {
603 if (vaddr <= limit && vaddr + req->getSize() >= base)
604 return new GeneralProtection(0);
605 }
606 }
607 }
608 // If paging is enabled, do the translation.
609 if (cr0.pg) {
610 DPRINTF(TLB, "Paging enabled.\n");
611 // The vaddr already has the segment base applied.
612 TlbEntry *entry = lookup(vaddr);
613 if (!entry) {
614 return new TlbFault(vaddr);
615 } else {
616 // Do paging protection checks.
617 DPRINTF(TLB, "Entry found with paddr %#x, doing protection checks.\n", entry->paddr);
618 Addr paddr = entry->paddr | (vaddr & (entry->size-1));
619 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, paddr);
620 req->setPaddr(paddr);
621 }
622 } else {
623 //Use the address which already has segmentation applied.
624 DPRINTF(TLB, "Paging disabled.\n");
625 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr);
626 req->setPaddr(vaddr);
627 }
628 } else {
629 // Real mode
630 DPRINTF(TLB, "In real mode.\n");
631 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr);
632 req->setPaddr(vaddr);
633 }
634 // Check for an access to the local APIC
635#if FULL_SYSTEM
636 LocalApicBase localApicBase = tc->readMiscRegNoEffect(MISCREG_APIC_BASE);
637 Addr baseAddr = localApicBase.base << 12;
638 Addr paddr = req->getPaddr();
639 if (baseAddr <= paddr && baseAddr + (1 << 12) > paddr) {
640 req->setMmapedIpr(true);
641 // The Intel developer's manuals say the below restrictions apply,
642 // but the linux kernel, because of a compiler optimization, breaks
643 // them.
644 /*
645 // Check alignment
646 if (paddr & ((32/8) - 1))
647 return new GeneralProtection(0);
648 // Check access size
649 if (req->getSize() != (32/8))
650 return new GeneralProtection(0);
651 */
652
653 //Make sure we're at least only accessing one register.
654 if ((paddr & ~mask(3)) != ((paddr + req->getSize()) & ~mask(3)))
655 panic("Accessed more than one register at a time in the APIC!\n");
656 MiscReg regNum;
657 Addr offset = paddr & mask(3);
658 paddr &= ~mask(3);
659 switch (paddr - baseAddr)
660 {
661 case 0x20:
662 regNum = MISCREG_APIC_ID;
663 break;
664 case 0x30:
665 regNum = MISCREG_APIC_VERSION;
666 break;
667 case 0x80:
668 regNum = MISCREG_APIC_TASK_PRIORITY;
669 break;
670 case 0x90:
671 regNum = MISCREG_APIC_ARBITRATION_PRIORITY;
672 break;
673 case 0xA0:
674 regNum = MISCREG_APIC_PROCESSOR_PRIORITY;
675 break;
676 case 0xB0:
677 regNum = MISCREG_APIC_EOI;
678 break;
679 case 0xD0:
680 regNum = MISCREG_APIC_LOGICAL_DESTINATION;
681 break;
682 case 0xE0:
683 regNum = MISCREG_APIC_DESTINATION_FORMAT;
684 break;
685 case 0xF0:
686 regNum = MISCREG_APIC_SPURIOUS_INTERRUPT_VECTOR;
687 break;
688 case 0x100:
689 case 0x108:
690 case 0x110:
691 case 0x118:
692 case 0x120:
693 case 0x128:
694 case 0x130:
695 case 0x138:
696 case 0x140:
697 case 0x148:
698 case 0x150:
699 case 0x158:
700 case 0x160:
701 case 0x168:
702 case 0x170:
703 case 0x178:
704 regNum = MISCREG_APIC_IN_SERVICE(
705 (paddr - baseAddr - 0x100) / 0x8);
706 break;
707 case 0x180:
708 case 0x188:
709 case 0x190:
710 case 0x198:
711 case 0x1A0:
712 case 0x1A8:
713 case 0x1B0:
714 case 0x1B8:
715 case 0x1C0:
716 case 0x1C8:
717 case 0x1D0:
718 case 0x1D8:
719 case 0x1E0:
720 case 0x1E8:
721 case 0x1F0:
722 case 0x1F8:
723 regNum = MISCREG_APIC_TRIGGER_MODE(
724 (paddr - baseAddr - 0x180) / 0x8);
725 break;
726 case 0x200:
727 case 0x208:
728 case 0x210:
729 case 0x218:
730 case 0x220:
731 case 0x228:
732 case 0x230:
733 case 0x238:
734 case 0x240:
735 case 0x248:
736 case 0x250:
737 case 0x258:
738 case 0x260:
739 case 0x268:
740 case 0x270:
741 case 0x278:
742 regNum = MISCREG_APIC_INTERRUPT_REQUEST(
743 (paddr - baseAddr - 0x200) / 0x8);
744 break;
745 case 0x280:
746 regNum = MISCREG_APIC_ERROR_STATUS;
747 break;
748 case 0x300:
749 regNum = MISCREG_APIC_INTERRUPT_COMMAND_LOW;
750 break;
751 case 0x310:
752 regNum = MISCREG_APIC_INTERRUPT_COMMAND_HIGH;
753 break;
754 case 0x320:
755 regNum = MISCREG_APIC_LVT_TIMER;
756 break;
757 case 0x330:
758 regNum = MISCREG_APIC_LVT_THERMAL_SENSOR;
759 break;
760 case 0x340:
761 regNum = MISCREG_APIC_LVT_PERFORMANCE_MONITORING_COUNTERS;
762 break;
763 case 0x350:
764 regNum = MISCREG_APIC_LVT_LINT0;
765 break;
766 case 0x360:
767 regNum = MISCREG_APIC_LVT_LINT1;
768 break;
769 case 0x370:
770 regNum = MISCREG_APIC_LVT_ERROR;
771 break;
772 case 0x380:
773 regNum = MISCREG_APIC_INITIAL_COUNT;
774 break;
775 case 0x390:
776 regNum = MISCREG_APIC_CURRENT_COUNT;
777 break;
778 case 0x3E0:
779 regNum = MISCREG_APIC_DIVIDE_COUNT;
780 break;
781 default:
782 // A reserved register field.
783 return new GeneralProtection(0);
784 break;
785 }
786 req->setPaddr(regNum * sizeof(MiscReg) + offset);
787 }
788#endif
789 return NoFault;
790};
791
792Fault
793DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
794{
795 return TLB::translate<FakeDTLBFault>(req, tc, write, false);
796}
797
798Fault
799ITB::translate(RequestPtr &req, ThreadContext *tc)
800{
801 return TLB::translate<FakeITLBFault>(req, tc, false, true);
802}
803
804#if FULL_SYSTEM
805
806Tick
807DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
808{
809 return tc->getCpuPtr()->ticks(1);
810}
811
812Tick
813DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
814{
815 return tc->getCpuPtr()->ticks(1);
816}
817
818#endif
819
820void
821TLB::serialize(std::ostream &os)
822{
823}
824
825void
826TLB::unserialize(Checkpoint *cp, const std::string §ion)
827{
828}
829
830void
831DTB::serialize(std::ostream &os)
832{
833 TLB::serialize(os);
834}
835
836void
837DTB::unserialize(Checkpoint *cp, const std::string §ion)
838{
839 TLB::unserialize(cp, section);
840}
841
842/* end namespace X86ISA */ }
843
844X86ISA::ITB *
845X86ITBParams::create()
846{
847 return new X86ISA::ITB(this);
848}
849
850X86ISA::DTB *
851X86DTBParams::create()
852{
853 return new X86ISA::DTB(this);
854}
| 589 DPRINTF(TLB, "Checking an expand down segment.\n");
590 // We don't have to worry about the access going around the
591 // end of memory because accesses will be broken up into
592 // pieces at boundaries aligned on sizes smaller than an
593 // entire address space. We do have to worry about the limit
594 // being less than the base.
595 if (limit < base) {
596 if (limit < vaddr + req->getSize() && vaddr < base)
597 return new GeneralProtection(0);
598 } else {
599 if (limit < vaddr + req->getSize())
600 return new GeneralProtection(0);
601 }
602 } else {
603 if (limit < base) {
604 if (vaddr <= limit || vaddr + req->getSize() >= base)
605 return new GeneralProtection(0);
606 } else {
607 if (vaddr <= limit && vaddr + req->getSize() >= base)
608 return new GeneralProtection(0);
609 }
610 }
611 }
612 // If paging is enabled, do the translation.
613 if (cr0.pg) {
614 DPRINTF(TLB, "Paging enabled.\n");
615 // The vaddr already has the segment base applied.
616 TlbEntry *entry = lookup(vaddr);
617 if (!entry) {
618 return new TlbFault(vaddr);
619 } else {
620 // Do paging protection checks.
621 DPRINTF(TLB, "Entry found with paddr %#x, doing protection checks.\n", entry->paddr);
622 Addr paddr = entry->paddr | (vaddr & (entry->size-1));
623 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, paddr);
624 req->setPaddr(paddr);
625 }
626 } else {
627 //Use the address which already has segmentation applied.
628 DPRINTF(TLB, "Paging disabled.\n");
629 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr);
630 req->setPaddr(vaddr);
631 }
632 } else {
633 // Real mode
634 DPRINTF(TLB, "In real mode.\n");
635 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr);
636 req->setPaddr(vaddr);
637 }
638 // Check for an access to the local APIC
639#if FULL_SYSTEM
640 LocalApicBase localApicBase = tc->readMiscRegNoEffect(MISCREG_APIC_BASE);
641 Addr baseAddr = localApicBase.base << 12;
642 Addr paddr = req->getPaddr();
643 if (baseAddr <= paddr && baseAddr + (1 << 12) > paddr) {
644 req->setMmapedIpr(true);
645 // The Intel developer's manuals say the below restrictions apply,
646 // but the linux kernel, because of a compiler optimization, breaks
647 // them.
648 /*
649 // Check alignment
650 if (paddr & ((32/8) - 1))
651 return new GeneralProtection(0);
652 // Check access size
653 if (req->getSize() != (32/8))
654 return new GeneralProtection(0);
655 */
656
657 //Make sure we're at least only accessing one register.
658 if ((paddr & ~mask(3)) != ((paddr + req->getSize()) & ~mask(3)))
659 panic("Accessed more than one register at a time in the APIC!\n");
660 MiscReg regNum;
661 Addr offset = paddr & mask(3);
662 paddr &= ~mask(3);
663 switch (paddr - baseAddr)
664 {
665 case 0x20:
666 regNum = MISCREG_APIC_ID;
667 break;
668 case 0x30:
669 regNum = MISCREG_APIC_VERSION;
670 break;
671 case 0x80:
672 regNum = MISCREG_APIC_TASK_PRIORITY;
673 break;
674 case 0x90:
675 regNum = MISCREG_APIC_ARBITRATION_PRIORITY;
676 break;
677 case 0xA0:
678 regNum = MISCREG_APIC_PROCESSOR_PRIORITY;
679 break;
680 case 0xB0:
681 regNum = MISCREG_APIC_EOI;
682 break;
683 case 0xD0:
684 regNum = MISCREG_APIC_LOGICAL_DESTINATION;
685 break;
686 case 0xE0:
687 regNum = MISCREG_APIC_DESTINATION_FORMAT;
688 break;
689 case 0xF0:
690 regNum = MISCREG_APIC_SPURIOUS_INTERRUPT_VECTOR;
691 break;
692 case 0x100:
693 case 0x108:
694 case 0x110:
695 case 0x118:
696 case 0x120:
697 case 0x128:
698 case 0x130:
699 case 0x138:
700 case 0x140:
701 case 0x148:
702 case 0x150:
703 case 0x158:
704 case 0x160:
705 case 0x168:
706 case 0x170:
707 case 0x178:
708 regNum = MISCREG_APIC_IN_SERVICE(
709 (paddr - baseAddr - 0x100) / 0x8);
710 break;
711 case 0x180:
712 case 0x188:
713 case 0x190:
714 case 0x198:
715 case 0x1A0:
716 case 0x1A8:
717 case 0x1B0:
718 case 0x1B8:
719 case 0x1C0:
720 case 0x1C8:
721 case 0x1D0:
722 case 0x1D8:
723 case 0x1E0:
724 case 0x1E8:
725 case 0x1F0:
726 case 0x1F8:
727 regNum = MISCREG_APIC_TRIGGER_MODE(
728 (paddr - baseAddr - 0x180) / 0x8);
729 break;
730 case 0x200:
731 case 0x208:
732 case 0x210:
733 case 0x218:
734 case 0x220:
735 case 0x228:
736 case 0x230:
737 case 0x238:
738 case 0x240:
739 case 0x248:
740 case 0x250:
741 case 0x258:
742 case 0x260:
743 case 0x268:
744 case 0x270:
745 case 0x278:
746 regNum = MISCREG_APIC_INTERRUPT_REQUEST(
747 (paddr - baseAddr - 0x200) / 0x8);
748 break;
749 case 0x280:
750 regNum = MISCREG_APIC_ERROR_STATUS;
751 break;
752 case 0x300:
753 regNum = MISCREG_APIC_INTERRUPT_COMMAND_LOW;
754 break;
755 case 0x310:
756 regNum = MISCREG_APIC_INTERRUPT_COMMAND_HIGH;
757 break;
758 case 0x320:
759 regNum = MISCREG_APIC_LVT_TIMER;
760 break;
761 case 0x330:
762 regNum = MISCREG_APIC_LVT_THERMAL_SENSOR;
763 break;
764 case 0x340:
765 regNum = MISCREG_APIC_LVT_PERFORMANCE_MONITORING_COUNTERS;
766 break;
767 case 0x350:
768 regNum = MISCREG_APIC_LVT_LINT0;
769 break;
770 case 0x360:
771 regNum = MISCREG_APIC_LVT_LINT1;
772 break;
773 case 0x370:
774 regNum = MISCREG_APIC_LVT_ERROR;
775 break;
776 case 0x380:
777 regNum = MISCREG_APIC_INITIAL_COUNT;
778 break;
779 case 0x390:
780 regNum = MISCREG_APIC_CURRENT_COUNT;
781 break;
782 case 0x3E0:
783 regNum = MISCREG_APIC_DIVIDE_COUNT;
784 break;
785 default:
786 // A reserved register field.
787 return new GeneralProtection(0);
788 break;
789 }
790 req->setPaddr(regNum * sizeof(MiscReg) + offset);
791 }
792#endif
793 return NoFault;
794};
795
796Fault
797DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
798{
799 return TLB::translate<FakeDTLBFault>(req, tc, write, false);
800}
801
802Fault
803ITB::translate(RequestPtr &req, ThreadContext *tc)
804{
805 return TLB::translate<FakeITLBFault>(req, tc, false, true);
806}
807
808#if FULL_SYSTEM
809
810Tick
811DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
812{
813 return tc->getCpuPtr()->ticks(1);
814}
815
816Tick
817DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
818{
819 return tc->getCpuPtr()->ticks(1);
820}
821
822#endif
823
824void
825TLB::serialize(std::ostream &os)
826{
827}
828
829void
830TLB::unserialize(Checkpoint *cp, const std::string §ion)
831{
832}
833
834void
835DTB::serialize(std::ostream &os)
836{
837 TLB::serialize(os);
838}
839
840void
841DTB::unserialize(Checkpoint *cp, const std::string §ion)
842{
843 TLB::unserialize(cp, section);
844}
845
846/* end namespace X86ISA */ }
847
848X86ISA::ITB *
849X86ITBParams::create()
850{
851 return new X86ISA::ITB(this);
852}
853
854X86ISA::DTB *
855X86DTBParams::create()
856{
857 return new X86ISA::DTB(this);
858}
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