1/*
2 * Copyright (c) 2007-2008 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 */
39
40#include "arch/x86/tlb.hh"
41
42#include <cstring>
43#include <memory>
44
45#include "arch/generic/mmapped_ipr.hh"
46#include "arch/x86/faults.hh"
47#include "arch/x86/insts/microldstop.hh"
48#include "arch/x86/pagetable_walker.hh"
49#include "arch/x86/regs/misc.hh"
50#include "arch/x86/regs/msr.hh"
51#include "arch/x86/x86_traits.hh"
52#include "base/trace.hh"
53#include "cpu/thread_context.hh"
54#include "debug/TLB.hh"
55#include "mem/page_table.hh"
56#include "mem/request.hh"
57#include "sim/full_system.hh"
58#include "sim/process.hh"
59
60namespace X86ISA {
61
62TLB::TLB(const Params *p)
63 : BaseTLB(p), configAddress(0), size(p->size),
64 tlb(size), lruSeq(0)
65{
66 if (!size)
67 fatal("TLBs must have a non-zero size.\n");
68
69 for (int x = 0; x < size; x++) {
70 tlb[x].trieHandle = NULL;
71 freeList.push_back(&tlb[x]);
72 }
73
74 walker = p->walker;
75 walker->setTLB(this);
76}
77
78void
79TLB::evictLRU()
80{
81 // Find the entry with the lowest (and hence least recently updated)
82 // sequence number.
83
84 unsigned lru = 0;
85 for (unsigned i = 1; i < size; i++) {
86 if (tlb[i].lruSeq < tlb[lru].lruSeq)
87 lru = i;
88 }
89
90 assert(tlb[lru].trieHandle);
91 trie.remove(tlb[lru].trieHandle);
92 tlb[lru].trieHandle = NULL;
93 freeList.push_back(&tlb[lru]);
94}
95
96TlbEntry *
| 1/*
2 * Copyright (c) 2007-2008 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 */
39
40#include "arch/x86/tlb.hh"
41
42#include <cstring>
43#include <memory>
44
45#include "arch/generic/mmapped_ipr.hh"
46#include "arch/x86/faults.hh"
47#include "arch/x86/insts/microldstop.hh"
48#include "arch/x86/pagetable_walker.hh"
49#include "arch/x86/regs/misc.hh"
50#include "arch/x86/regs/msr.hh"
51#include "arch/x86/x86_traits.hh"
52#include "base/trace.hh"
53#include "cpu/thread_context.hh"
54#include "debug/TLB.hh"
55#include "mem/page_table.hh"
56#include "mem/request.hh"
57#include "sim/full_system.hh"
58#include "sim/process.hh"
59
60namespace X86ISA {
61
62TLB::TLB(const Params *p)
63 : BaseTLB(p), configAddress(0), size(p->size),
64 tlb(size), lruSeq(0)
65{
66 if (!size)
67 fatal("TLBs must have a non-zero size.\n");
68
69 for (int x = 0; x < size; x++) {
70 tlb[x].trieHandle = NULL;
71 freeList.push_back(&tlb[x]);
72 }
73
74 walker = p->walker;
75 walker->setTLB(this);
76}
77
78void
79TLB::evictLRU()
80{
81 // Find the entry with the lowest (and hence least recently updated)
82 // sequence number.
83
84 unsigned lru = 0;
85 for (unsigned i = 1; i < size; i++) {
86 if (tlb[i].lruSeq < tlb[lru].lruSeq)
87 lru = i;
88 }
89
90 assert(tlb[lru].trieHandle);
91 trie.remove(tlb[lru].trieHandle);
92 tlb[lru].trieHandle = NULL;
93 freeList.push_back(&tlb[lru]);
94}
95
96TlbEntry *
|
97TLB::insert(Addr vpn, TlbEntry &entry)
| 97TLB::insert(Addr vpn, const TlbEntry &entry)
|
98{
99 // If somebody beat us to it, just use that existing entry.
100 TlbEntry *newEntry = trie.lookup(vpn);
101 if (newEntry) {
102 assert(newEntry->vaddr == vpn);
103 return newEntry;
104 }
105
106 if (freeList.empty())
107 evictLRU();
108
109 newEntry = freeList.front();
110 freeList.pop_front();
111
112 *newEntry = entry;
113 newEntry->lruSeq = nextSeq();
114 newEntry->vaddr = vpn;
115 newEntry->trieHandle =
116 trie.insert(vpn, TlbEntryTrie::MaxBits - entry.logBytes, newEntry);
117 return newEntry;
118}
119
120TlbEntry *
121TLB::lookup(Addr va, bool update_lru)
122{
123 TlbEntry *entry = trie.lookup(va);
124 if (entry && update_lru)
125 entry->lruSeq = nextSeq();
126 return entry;
127}
128
129void
130TLB::flushAll()
131{
132 DPRINTF(TLB, "Invalidating all entries.\n");
133 for (unsigned i = 0; i < size; i++) {
134 if (tlb[i].trieHandle) {
135 trie.remove(tlb[i].trieHandle);
136 tlb[i].trieHandle = NULL;
137 freeList.push_back(&tlb[i]);
138 }
139 }
140}
141
142void
143TLB::setConfigAddress(uint32_t addr)
144{
145 configAddress = addr;
146}
147
148void
149TLB::flushNonGlobal()
150{
151 DPRINTF(TLB, "Invalidating all non global entries.\n");
152 for (unsigned i = 0; i < size; i++) {
153 if (tlb[i].trieHandle && !tlb[i].global) {
154 trie.remove(tlb[i].trieHandle);
155 tlb[i].trieHandle = NULL;
156 freeList.push_back(&tlb[i]);
157 }
158 }
159}
160
161void
162TLB::demapPage(Addr va, uint64_t asn)
163{
164 TlbEntry *entry = trie.lookup(va);
165 if (entry) {
166 trie.remove(entry->trieHandle);
167 entry->trieHandle = NULL;
168 freeList.push_back(entry);
169 }
170}
171
172Fault
173TLB::translateInt(RequestPtr req, ThreadContext *tc)
174{
175 DPRINTF(TLB, "Addresses references internal memory.\n");
176 Addr vaddr = req->getVaddr();
177 Addr prefix = (vaddr >> 3) & IntAddrPrefixMask;
178 if (prefix == IntAddrPrefixCPUID) {
179 panic("CPUID memory space not yet implemented!\n");
180 } else if (prefix == IntAddrPrefixMSR) {
181 vaddr = (vaddr >> 3) & ~IntAddrPrefixMask;
182 req->setFlags(Request::MMAPPED_IPR);
183
184 MiscRegIndex regNum;
185 if (!msrAddrToIndex(regNum, vaddr))
186 return std::make_shared<GeneralProtection>(0);
187
188 //The index is multiplied by the size of a MiscReg so that
189 //any memory dependence calculations will not see these as
190 //overlapping.
191 req->setPaddr((Addr)regNum * sizeof(MiscReg));
192 return NoFault;
193 } else if (prefix == IntAddrPrefixIO) {
194 // TODO If CPL > IOPL or in virtual mode, check the I/O permission
195 // bitmap in the TSS.
196
197 Addr IOPort = vaddr & ~IntAddrPrefixMask;
198 // Make sure the address fits in the expected 16 bit IO address
199 // space.
200 assert(!(IOPort & ~0xFFFF));
201 if (IOPort == 0xCF8 && req->getSize() == 4) {
202 req->setFlags(Request::MMAPPED_IPR);
203 req->setPaddr(MISCREG_PCI_CONFIG_ADDRESS * sizeof(MiscReg));
204 } else if ((IOPort & ~mask(2)) == 0xCFC) {
205 req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER);
206 Addr configAddress =
207 tc->readMiscRegNoEffect(MISCREG_PCI_CONFIG_ADDRESS);
208 if (bits(configAddress, 31, 31)) {
209 req->setPaddr(PhysAddrPrefixPciConfig |
210 mbits(configAddress, 30, 2) |
211 (IOPort & mask(2)));
212 } else {
213 req->setPaddr(PhysAddrPrefixIO | IOPort);
214 }
215 } else {
216 req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER);
217 req->setPaddr(PhysAddrPrefixIO | IOPort);
218 }
219 return NoFault;
220 } else {
221 panic("Access to unrecognized internal address space %#x.\n",
222 prefix);
223 }
224}
225
226Fault
227TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const
228{
229 Addr paddr = req->getPaddr();
230
231 AddrRange m5opRange(0xFFFF0000, 0xFFFFFFFF);
232
233 if (m5opRange.contains(paddr)) {
234 req->setFlags(Request::MMAPPED_IPR | Request::GENERIC_IPR |
235 Request::STRICT_ORDER);
236 req->setPaddr(GenericISA::iprAddressPseudoInst((paddr >> 8) & 0xFF,
237 paddr & 0xFF));
238 } else if (FullSystem) {
239 // Check for an access to the local APIC
240 LocalApicBase localApicBase =
241 tc->readMiscRegNoEffect(MISCREG_APIC_BASE);
242 AddrRange apicRange(localApicBase.base * PageBytes,
243 (localApicBase.base + 1) * PageBytes - 1);
244
245 if (apicRange.contains(paddr)) {
246 // The Intel developer's manuals say the below restrictions apply,
247 // but the linux kernel, because of a compiler optimization, breaks
248 // them.
249 /*
250 // Check alignment
251 if (paddr & ((32/8) - 1))
252 return new GeneralProtection(0);
253 // Check access size
254 if (req->getSize() != (32/8))
255 return new GeneralProtection(0);
256 */
257 // Force the access to be uncacheable.
258 req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER);
259 req->setPaddr(x86LocalAPICAddress(tc->contextId(),
260 paddr - apicRange.start()));
261 }
262 }
263
264 return NoFault;
265}
266
267Fault
268TLB::translate(RequestPtr req, ThreadContext *tc, Translation *translation,
269 Mode mode, bool &delayedResponse, bool timing)
270{
271 Request::Flags flags = req->getFlags();
272 int seg = flags & SegmentFlagMask;
273 bool storeCheck = flags & (StoreCheck << FlagShift);
274
275 delayedResponse = false;
276
277 // If this is true, we're dealing with a request to a non-memory address
278 // space.
279 if (seg == SEGMENT_REG_MS) {
280 return translateInt(req, tc);
281 }
282
283 Addr vaddr = req->getVaddr();
284 DPRINTF(TLB, "Translating vaddr %#x.\n", vaddr);
285
286 HandyM5Reg m5Reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
287
288 // If protected mode has been enabled...
289 if (m5Reg.prot) {
290 DPRINTF(TLB, "In protected mode.\n");
291 // If we're not in 64-bit mode, do protection/limit checks
292 if (m5Reg.mode != LongMode) {
293 DPRINTF(TLB, "Not in long mode. Checking segment protection.\n");
294 // Check for a NULL segment selector.
295 if (!(seg == SEGMENT_REG_TSG || seg == SYS_SEGMENT_REG_IDTR ||
296 seg == SEGMENT_REG_HS || seg == SEGMENT_REG_LS)
297 && !tc->readMiscRegNoEffect(MISCREG_SEG_SEL(seg)))
298 return std::make_shared<GeneralProtection>(0);
299 bool expandDown = false;
300 SegAttr attr = tc->readMiscRegNoEffect(MISCREG_SEG_ATTR(seg));
301 if (seg >= SEGMENT_REG_ES && seg <= SEGMENT_REG_HS) {
302 if (!attr.writable && (mode == Write || storeCheck))
303 return std::make_shared<GeneralProtection>(0);
304 if (!attr.readable && mode == Read)
305 return std::make_shared<GeneralProtection>(0);
306 expandDown = attr.expandDown;
307
308 }
309 Addr base = tc->readMiscRegNoEffect(MISCREG_SEG_BASE(seg));
310 Addr limit = tc->readMiscRegNoEffect(MISCREG_SEG_LIMIT(seg));
311 bool sizeOverride = (flags & (AddrSizeFlagBit << FlagShift));
312 unsigned logSize = sizeOverride ? (unsigned)m5Reg.altAddr
313 : (unsigned)m5Reg.defAddr;
314 int size = (1 << logSize) * 8;
315 Addr offset = bits(vaddr - base, size - 1, 0);
316 Addr endOffset = offset + req->getSize() - 1;
317 if (expandDown) {
318 DPRINTF(TLB, "Checking an expand down segment.\n");
319 warn_once("Expand down segments are untested.\n");
320 if (offset <= limit || endOffset <= limit)
321 return std::make_shared<GeneralProtection>(0);
322 } else {
323 if (offset > limit || endOffset > limit)
324 return std::make_shared<GeneralProtection>(0);
325 }
326 }
327 if (m5Reg.submode != SixtyFourBitMode ||
328 (flags & (AddrSizeFlagBit << FlagShift)))
329 vaddr &= mask(32);
330 // If paging is enabled, do the translation.
331 if (m5Reg.paging) {
332 DPRINTF(TLB, "Paging enabled.\n");
333 // The vaddr already has the segment base applied.
334 TlbEntry *entry = lookup(vaddr);
335 if (mode == Read) {
336 rdAccesses++;
337 } else {
338 wrAccesses++;
339 }
340 if (!entry) {
341 DPRINTF(TLB, "Handling a TLB miss for "
342 "address %#x at pc %#x.\n",
343 vaddr, tc->instAddr());
344 if (mode == Read) {
345 rdMisses++;
346 } else {
347 wrMisses++;
348 }
349 if (FullSystem) {
350 Fault fault = walker->start(tc, translation, req, mode);
351 if (timing || fault != NoFault) {
352 // This gets ignored in atomic mode.
353 delayedResponse = true;
354 return fault;
355 }
356 entry = lookup(vaddr);
357 assert(entry);
358 } else {
359 Process *p = tc->getProcessPtr();
| 98{
99 // If somebody beat us to it, just use that existing entry.
100 TlbEntry *newEntry = trie.lookup(vpn);
101 if (newEntry) {
102 assert(newEntry->vaddr == vpn);
103 return newEntry;
104 }
105
106 if (freeList.empty())
107 evictLRU();
108
109 newEntry = freeList.front();
110 freeList.pop_front();
111
112 *newEntry = entry;
113 newEntry->lruSeq = nextSeq();
114 newEntry->vaddr = vpn;
115 newEntry->trieHandle =
116 trie.insert(vpn, TlbEntryTrie::MaxBits - entry.logBytes, newEntry);
117 return newEntry;
118}
119
120TlbEntry *
121TLB::lookup(Addr va, bool update_lru)
122{
123 TlbEntry *entry = trie.lookup(va);
124 if (entry && update_lru)
125 entry->lruSeq = nextSeq();
126 return entry;
127}
128
129void
130TLB::flushAll()
131{
132 DPRINTF(TLB, "Invalidating all entries.\n");
133 for (unsigned i = 0; i < size; i++) {
134 if (tlb[i].trieHandle) {
135 trie.remove(tlb[i].trieHandle);
136 tlb[i].trieHandle = NULL;
137 freeList.push_back(&tlb[i]);
138 }
139 }
140}
141
142void
143TLB::setConfigAddress(uint32_t addr)
144{
145 configAddress = addr;
146}
147
148void
149TLB::flushNonGlobal()
150{
151 DPRINTF(TLB, "Invalidating all non global entries.\n");
152 for (unsigned i = 0; i < size; i++) {
153 if (tlb[i].trieHandle && !tlb[i].global) {
154 trie.remove(tlb[i].trieHandle);
155 tlb[i].trieHandle = NULL;
156 freeList.push_back(&tlb[i]);
157 }
158 }
159}
160
161void
162TLB::demapPage(Addr va, uint64_t asn)
163{
164 TlbEntry *entry = trie.lookup(va);
165 if (entry) {
166 trie.remove(entry->trieHandle);
167 entry->trieHandle = NULL;
168 freeList.push_back(entry);
169 }
170}
171
172Fault
173TLB::translateInt(RequestPtr req, ThreadContext *tc)
174{
175 DPRINTF(TLB, "Addresses references internal memory.\n");
176 Addr vaddr = req->getVaddr();
177 Addr prefix = (vaddr >> 3) & IntAddrPrefixMask;
178 if (prefix == IntAddrPrefixCPUID) {
179 panic("CPUID memory space not yet implemented!\n");
180 } else if (prefix == IntAddrPrefixMSR) {
181 vaddr = (vaddr >> 3) & ~IntAddrPrefixMask;
182 req->setFlags(Request::MMAPPED_IPR);
183
184 MiscRegIndex regNum;
185 if (!msrAddrToIndex(regNum, vaddr))
186 return std::make_shared<GeneralProtection>(0);
187
188 //The index is multiplied by the size of a MiscReg so that
189 //any memory dependence calculations will not see these as
190 //overlapping.
191 req->setPaddr((Addr)regNum * sizeof(MiscReg));
192 return NoFault;
193 } else if (prefix == IntAddrPrefixIO) {
194 // TODO If CPL > IOPL or in virtual mode, check the I/O permission
195 // bitmap in the TSS.
196
197 Addr IOPort = vaddr & ~IntAddrPrefixMask;
198 // Make sure the address fits in the expected 16 bit IO address
199 // space.
200 assert(!(IOPort & ~0xFFFF));
201 if (IOPort == 0xCF8 && req->getSize() == 4) {
202 req->setFlags(Request::MMAPPED_IPR);
203 req->setPaddr(MISCREG_PCI_CONFIG_ADDRESS * sizeof(MiscReg));
204 } else if ((IOPort & ~mask(2)) == 0xCFC) {
205 req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER);
206 Addr configAddress =
207 tc->readMiscRegNoEffect(MISCREG_PCI_CONFIG_ADDRESS);
208 if (bits(configAddress, 31, 31)) {
209 req->setPaddr(PhysAddrPrefixPciConfig |
210 mbits(configAddress, 30, 2) |
211 (IOPort & mask(2)));
212 } else {
213 req->setPaddr(PhysAddrPrefixIO | IOPort);
214 }
215 } else {
216 req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER);
217 req->setPaddr(PhysAddrPrefixIO | IOPort);
218 }
219 return NoFault;
220 } else {
221 panic("Access to unrecognized internal address space %#x.\n",
222 prefix);
223 }
224}
225
226Fault
227TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const
228{
229 Addr paddr = req->getPaddr();
230
231 AddrRange m5opRange(0xFFFF0000, 0xFFFFFFFF);
232
233 if (m5opRange.contains(paddr)) {
234 req->setFlags(Request::MMAPPED_IPR | Request::GENERIC_IPR |
235 Request::STRICT_ORDER);
236 req->setPaddr(GenericISA::iprAddressPseudoInst((paddr >> 8) & 0xFF,
237 paddr & 0xFF));
238 } else if (FullSystem) {
239 // Check for an access to the local APIC
240 LocalApicBase localApicBase =
241 tc->readMiscRegNoEffect(MISCREG_APIC_BASE);
242 AddrRange apicRange(localApicBase.base * PageBytes,
243 (localApicBase.base + 1) * PageBytes - 1);
244
245 if (apicRange.contains(paddr)) {
246 // The Intel developer's manuals say the below restrictions apply,
247 // but the linux kernel, because of a compiler optimization, breaks
248 // them.
249 /*
250 // Check alignment
251 if (paddr & ((32/8) - 1))
252 return new GeneralProtection(0);
253 // Check access size
254 if (req->getSize() != (32/8))
255 return new GeneralProtection(0);
256 */
257 // Force the access to be uncacheable.
258 req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER);
259 req->setPaddr(x86LocalAPICAddress(tc->contextId(),
260 paddr - apicRange.start()));
261 }
262 }
263
264 return NoFault;
265}
266
267Fault
268TLB::translate(RequestPtr req, ThreadContext *tc, Translation *translation,
269 Mode mode, bool &delayedResponse, bool timing)
270{
271 Request::Flags flags = req->getFlags();
272 int seg = flags & SegmentFlagMask;
273 bool storeCheck = flags & (StoreCheck << FlagShift);
274
275 delayedResponse = false;
276
277 // If this is true, we're dealing with a request to a non-memory address
278 // space.
279 if (seg == SEGMENT_REG_MS) {
280 return translateInt(req, tc);
281 }
282
283 Addr vaddr = req->getVaddr();
284 DPRINTF(TLB, "Translating vaddr %#x.\n", vaddr);
285
286 HandyM5Reg m5Reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
287
288 // If protected mode has been enabled...
289 if (m5Reg.prot) {
290 DPRINTF(TLB, "In protected mode.\n");
291 // If we're not in 64-bit mode, do protection/limit checks
292 if (m5Reg.mode != LongMode) {
293 DPRINTF(TLB, "Not in long mode. Checking segment protection.\n");
294 // Check for a NULL segment selector.
295 if (!(seg == SEGMENT_REG_TSG || seg == SYS_SEGMENT_REG_IDTR ||
296 seg == SEGMENT_REG_HS || seg == SEGMENT_REG_LS)
297 && !tc->readMiscRegNoEffect(MISCREG_SEG_SEL(seg)))
298 return std::make_shared<GeneralProtection>(0);
299 bool expandDown = false;
300 SegAttr attr = tc->readMiscRegNoEffect(MISCREG_SEG_ATTR(seg));
301 if (seg >= SEGMENT_REG_ES && seg <= SEGMENT_REG_HS) {
302 if (!attr.writable && (mode == Write || storeCheck))
303 return std::make_shared<GeneralProtection>(0);
304 if (!attr.readable && mode == Read)
305 return std::make_shared<GeneralProtection>(0);
306 expandDown = attr.expandDown;
307
308 }
309 Addr base = tc->readMiscRegNoEffect(MISCREG_SEG_BASE(seg));
310 Addr limit = tc->readMiscRegNoEffect(MISCREG_SEG_LIMIT(seg));
311 bool sizeOverride = (flags & (AddrSizeFlagBit << FlagShift));
312 unsigned logSize = sizeOverride ? (unsigned)m5Reg.altAddr
313 : (unsigned)m5Reg.defAddr;
314 int size = (1 << logSize) * 8;
315 Addr offset = bits(vaddr - base, size - 1, 0);
316 Addr endOffset = offset + req->getSize() - 1;
317 if (expandDown) {
318 DPRINTF(TLB, "Checking an expand down segment.\n");
319 warn_once("Expand down segments are untested.\n");
320 if (offset <= limit || endOffset <= limit)
321 return std::make_shared<GeneralProtection>(0);
322 } else {
323 if (offset > limit || endOffset > limit)
324 return std::make_shared<GeneralProtection>(0);
325 }
326 }
327 if (m5Reg.submode != SixtyFourBitMode ||
328 (flags & (AddrSizeFlagBit << FlagShift)))
329 vaddr &= mask(32);
330 // If paging is enabled, do the translation.
331 if (m5Reg.paging) {
332 DPRINTF(TLB, "Paging enabled.\n");
333 // The vaddr already has the segment base applied.
334 TlbEntry *entry = lookup(vaddr);
335 if (mode == Read) {
336 rdAccesses++;
337 } else {
338 wrAccesses++;
339 }
340 if (!entry) {
341 DPRINTF(TLB, "Handling a TLB miss for "
342 "address %#x at pc %#x.\n",
343 vaddr, tc->instAddr());
344 if (mode == Read) {
345 rdMisses++;
346 } else {
347 wrMisses++;
348 }
349 if (FullSystem) {
350 Fault fault = walker->start(tc, translation, req, mode);
351 if (timing || fault != NoFault) {
352 // This gets ignored in atomic mode.
353 delayedResponse = true;
354 return fault;
355 }
356 entry = lookup(vaddr);
357 assert(entry);
358 } else {
359 Process *p = tc->getProcessPtr();
|
360 TlbEntry newEntry;
361 bool success = p->pTable->lookup(vaddr, newEntry);
362 if (!success && mode != Execute) {
| 360 TlbEntry *newEntry = p->pTable->lookup(vaddr);
361 if (!newEntry && mode != Execute) {
|
363 // Check if we just need to grow the stack.
364 if (p->fixupStackFault(vaddr)) {
365 // If we did, lookup the entry for the new page.
| 362 // Check if we just need to grow the stack.
363 if (p->fixupStackFault(vaddr)) {
364 // If we did, lookup the entry for the new page.
|
366 success = p->pTable->lookup(vaddr, newEntry);
| 365 newEntry = p->pTable->lookup(vaddr);
|
367 }
368 }
| 366 }
367 }
|
369 if (!success) {
| 368 if (!newEntry) {
|
370 return std::make_shared<PageFault>(vaddr, true, mode,
371 true, false);
372 } else {
373 Addr alignedVaddr = p->pTable->pageAlign(vaddr);
374 DPRINTF(TLB, "Mapping %#x to %#x\n", alignedVaddr,
| 369 return std::make_shared<PageFault>(vaddr, true, mode,
370 true, false);
371 } else {
372 Addr alignedVaddr = p->pTable->pageAlign(vaddr);
373 DPRINTF(TLB, "Mapping %#x to %#x\n", alignedVaddr,
|
375 newEntry.pageStart());
376 entry = insert(alignedVaddr, newEntry);
| 374 newEntry->pageStart());
375 entry = insert(alignedVaddr, *newEntry);
|
377 }
378 DPRINTF(TLB, "Miss was serviced.\n");
379 }
380 }
381
382 DPRINTF(TLB, "Entry found with paddr %#x, "
383 "doing protection checks.\n", entry->paddr);
384 // Do paging protection checks.
385 bool inUser = (m5Reg.cpl == 3 &&
386 !(flags & (CPL0FlagBit << FlagShift)));
387 CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0);
388 bool badWrite = (!entry->writable && (inUser || cr0.wp));
389 if ((inUser && !entry->user) || (mode == Write && badWrite)) {
390 // The page must have been present to get into the TLB in
391 // the first place. We'll assume the reserved bits are
392 // fine even though we're not checking them.
393 return std::make_shared<PageFault>(vaddr, true, mode, inUser,
394 false);
395 }
396 if (storeCheck && badWrite) {
397 // This would fault if this were a write, so return a page
398 // fault that reflects that happening.
399 return std::make_shared<PageFault>(vaddr, true, Write, inUser,
400 false);
401 }
402
403 Addr paddr = entry->paddr | (vaddr & mask(entry->logBytes));
404 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, paddr);
405 req->setPaddr(paddr);
406 if (entry->uncacheable)
407 req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER);
408 } else {
409 //Use the address which already has segmentation applied.
410 DPRINTF(TLB, "Paging disabled.\n");
411 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr);
412 req->setPaddr(vaddr);
413 }
414 } else {
415 // Real mode
416 DPRINTF(TLB, "In real mode.\n");
417 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr);
418 req->setPaddr(vaddr);
419 }
420
421 return finalizePhysical(req, tc, mode);
422}
423
424Fault
425TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
426{
427 bool delayedResponse;
428 return TLB::translate(req, tc, NULL, mode, delayedResponse, false);
429}
430
431void
432TLB::translateTiming(RequestPtr req, ThreadContext *tc,
433 Translation *translation, Mode mode)
434{
435 bool delayedResponse;
436 assert(translation);
437 Fault fault =
438 TLB::translate(req, tc, translation, mode, delayedResponse, true);
439 if (!delayedResponse)
440 translation->finish(fault, req, tc, mode);
441}
442
443Walker *
444TLB::getWalker()
445{
446 return walker;
447}
448
449void
450TLB::regStats()
451{
452 using namespace Stats;
453
454 rdAccesses
455 .name(name() + ".rdAccesses")
456 .desc("TLB accesses on read requests");
457
458 wrAccesses
459 .name(name() + ".wrAccesses")
460 .desc("TLB accesses on write requests");
461
462 rdMisses
463 .name(name() + ".rdMisses")
464 .desc("TLB misses on read requests");
465
466 wrMisses
467 .name(name() + ".wrMisses")
468 .desc("TLB misses on write requests");
469
470}
471
472void
473TLB::serialize(CheckpointOut &cp) const
474{
475 // Only store the entries in use.
476 uint32_t _size = size - freeList.size();
477 SERIALIZE_SCALAR(_size);
478 SERIALIZE_SCALAR(lruSeq);
479
480 uint32_t _count = 0;
481 for (uint32_t x = 0; x < size; x++) {
482 if (tlb[x].trieHandle != NULL)
483 tlb[x].serializeSection(cp, csprintf("Entry%d", _count++));
484 }
485}
486
487void
488TLB::unserialize(CheckpointIn &cp)
489{
490 // Do not allow to restore with a smaller tlb.
491 uint32_t _size;
492 UNSERIALIZE_SCALAR(_size);
493 if (_size > size) {
494 fatal("TLB size less than the one in checkpoint!");
495 }
496
497 UNSERIALIZE_SCALAR(lruSeq);
498
499 for (uint32_t x = 0; x < _size; x++) {
500 TlbEntry *newEntry = freeList.front();
501 freeList.pop_front();
502
503 newEntry->unserializeSection(cp, csprintf("Entry%d", x));
504 newEntry->trieHandle = trie.insert(newEntry->vaddr,
505 TlbEntryTrie::MaxBits - newEntry->logBytes, newEntry);
506 }
507}
508
509BaseMasterPort *
510TLB::getMasterPort()
511{
512 return &walker->getMasterPort("port");
513}
514
515} // namespace X86ISA
516
517X86ISA::TLB *
518X86TLBParams::create()
519{
520 return new X86ISA::TLB(this);
521}
| 376 }
377 DPRINTF(TLB, "Miss was serviced.\n");
378 }
379 }
380
381 DPRINTF(TLB, "Entry found with paddr %#x, "
382 "doing protection checks.\n", entry->paddr);
383 // Do paging protection checks.
384 bool inUser = (m5Reg.cpl == 3 &&
385 !(flags & (CPL0FlagBit << FlagShift)));
386 CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0);
387 bool badWrite = (!entry->writable && (inUser || cr0.wp));
388 if ((inUser && !entry->user) || (mode == Write && badWrite)) {
389 // The page must have been present to get into the TLB in
390 // the first place. We'll assume the reserved bits are
391 // fine even though we're not checking them.
392 return std::make_shared<PageFault>(vaddr, true, mode, inUser,
393 false);
394 }
395 if (storeCheck && badWrite) {
396 // This would fault if this were a write, so return a page
397 // fault that reflects that happening.
398 return std::make_shared<PageFault>(vaddr, true, Write, inUser,
399 false);
400 }
401
402 Addr paddr = entry->paddr | (vaddr & mask(entry->logBytes));
403 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, paddr);
404 req->setPaddr(paddr);
405 if (entry->uncacheable)
406 req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER);
407 } else {
408 //Use the address which already has segmentation applied.
409 DPRINTF(TLB, "Paging disabled.\n");
410 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr);
411 req->setPaddr(vaddr);
412 }
413 } else {
414 // Real mode
415 DPRINTF(TLB, "In real mode.\n");
416 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr);
417 req->setPaddr(vaddr);
418 }
419
420 return finalizePhysical(req, tc, mode);
421}
422
423Fault
424TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
425{
426 bool delayedResponse;
427 return TLB::translate(req, tc, NULL, mode, delayedResponse, false);
428}
429
430void
431TLB::translateTiming(RequestPtr req, ThreadContext *tc,
432 Translation *translation, Mode mode)
433{
434 bool delayedResponse;
435 assert(translation);
436 Fault fault =
437 TLB::translate(req, tc, translation, mode, delayedResponse, true);
438 if (!delayedResponse)
439 translation->finish(fault, req, tc, mode);
440}
441
442Walker *
443TLB::getWalker()
444{
445 return walker;
446}
447
448void
449TLB::regStats()
450{
451 using namespace Stats;
452
453 rdAccesses
454 .name(name() + ".rdAccesses")
455 .desc("TLB accesses on read requests");
456
457 wrAccesses
458 .name(name() + ".wrAccesses")
459 .desc("TLB accesses on write requests");
460
461 rdMisses
462 .name(name() + ".rdMisses")
463 .desc("TLB misses on read requests");
464
465 wrMisses
466 .name(name() + ".wrMisses")
467 .desc("TLB misses on write requests");
468
469}
470
471void
472TLB::serialize(CheckpointOut &cp) const
473{
474 // Only store the entries in use.
475 uint32_t _size = size - freeList.size();
476 SERIALIZE_SCALAR(_size);
477 SERIALIZE_SCALAR(lruSeq);
478
479 uint32_t _count = 0;
480 for (uint32_t x = 0; x < size; x++) {
481 if (tlb[x].trieHandle != NULL)
482 tlb[x].serializeSection(cp, csprintf("Entry%d", _count++));
483 }
484}
485
486void
487TLB::unserialize(CheckpointIn &cp)
488{
489 // Do not allow to restore with a smaller tlb.
490 uint32_t _size;
491 UNSERIALIZE_SCALAR(_size);
492 if (_size > size) {
493 fatal("TLB size less than the one in checkpoint!");
494 }
495
496 UNSERIALIZE_SCALAR(lruSeq);
497
498 for (uint32_t x = 0; x < _size; x++) {
499 TlbEntry *newEntry = freeList.front();
500 freeList.pop_front();
501
502 newEntry->unserializeSection(cp, csprintf("Entry%d", x));
503 newEntry->trieHandle = trie.insert(newEntry->vaddr,
504 TlbEntryTrie::MaxBits - newEntry->logBytes, newEntry);
505 }
506}
507
508BaseMasterPort *
509TLB::getMasterPort()
510{
511 return &walker->getMasterPort("port");
512}
513
514} // namespace X86ISA
515
516X86ISA::TLB *
517X86TLBParams::create()
518{
519 return new X86ISA::TLB(this);
520}
|