tlb.cc (5374:4773d53f88a0) | tlb.cc (5417:84755f1f32d3) |
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1/* | 1/* |
2 * Copyright (c) 2007 The Hewlett-Packard Development Company | 2 * Copyright (c) 2007-2008 The Hewlett-Packard Development Company |
3 * All rights reserved. 4 * 5 * Redistribution and use of this software in source and binary forms, 6 * with or without modification, are permitted provided that the 7 * following conditions are met: 8 * 9 * The software must be used only for Non-Commercial Use which means any 10 * use which is NOT directed to receiving any direct monetary --- 582 unchanged lines hidden (view full) --- 593 } 594 // Check for an access to the local APIC 595#if FULL_SYSTEM 596 LocalApicBase localApicBase = tc->readMiscRegNoEffect(MISCREG_APIC_BASE); 597 Addr baseAddr = localApicBase.base << 12; 598 Addr paddr = req->getPaddr(); 599 if (baseAddr <= paddr && baseAddr + (1 << 12) > paddr) { 600 req->setMmapedIpr(true); | 3 * All rights reserved. 4 * 5 * Redistribution and use of this software in source and binary forms, 6 * with or without modification, are permitted provided that the 7 * following conditions are met: 8 * 9 * The software must be used only for Non-Commercial Use which means any 10 * use which is NOT directed to receiving any direct monetary --- 582 unchanged lines hidden (view full) --- 593 } 594 // Check for an access to the local APIC 595#if FULL_SYSTEM 596 LocalApicBase localApicBase = tc->readMiscRegNoEffect(MISCREG_APIC_BASE); 597 Addr baseAddr = localApicBase.base << 12; 598 Addr paddr = req->getPaddr(); 599 if (baseAddr <= paddr && baseAddr + (1 << 12) > paddr) { 600 req->setMmapedIpr(true); |
601 // The Intel developer's manuals say the below restrictions apply, 602 // but the linux kernel, because of a compiler optimization, breaks 603 // them. 604 /* |
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601 // Check alignment 602 if (paddr & ((32/8) - 1)) 603 return new GeneralProtection(0); 604 // Check access size 605 if (req->getSize() != (32/8)) 606 return new GeneralProtection(0); | 605 // Check alignment 606 if (paddr & ((32/8) - 1)) 607 return new GeneralProtection(0); 608 // Check access size 609 if (req->getSize() != (32/8)) 610 return new GeneralProtection(0); |
611 */ 612 613 //Make sure we're at least only accessing one register. 614 if ((paddr & ~mask(3)) != ((paddr + req->getSize()) & ~mask(3))) 615 panic("Accessed more than one register at a time in the APIC!\n"); |
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607 MiscReg regNum; | 616 MiscReg regNum; |
617 Addr offset = paddr & mask(3); 618 paddr &= ~mask(3); |
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608 switch (paddr - baseAddr) 609 { 610 case 0x20: 611 regNum = MISCREG_APIC_ID; 612 break; 613 case 0x30: 614 regNum = MISCREG_APIC_VERSION; 615 break; --- 111 unchanged lines hidden (view full) --- 727 case 0x3E0: 728 regNum = MISCREG_APIC_DIVIDE_COUNT; 729 break; 730 default: 731 // A reserved register field. 732 return new GeneralProtection(0); 733 break; 734 } | 619 switch (paddr - baseAddr) 620 { 621 case 0x20: 622 regNum = MISCREG_APIC_ID; 623 break; 624 case 0x30: 625 regNum = MISCREG_APIC_VERSION; 626 break; --- 111 unchanged lines hidden (view full) --- 738 case 0x3E0: 739 regNum = MISCREG_APIC_DIVIDE_COUNT; 740 break; 741 default: 742 // A reserved register field. 743 return new GeneralProtection(0); 744 break; 745 } |
735 req->setPaddr(regNum * sizeof(MiscReg)); | 746 req->setPaddr(regNum * sizeof(MiscReg) + offset); |
736 } 737#endif 738 return NoFault; 739}; 740 741Fault 742DTB::translate(RequestPtr &req, ThreadContext *tc, bool write) 743{ --- 60 unchanged lines hidden --- | 747 } 748#endif 749 return NoFault; 750}; 751 752Fault 753DTB::translate(RequestPtr &req, ThreadContext *tc, bool write) 754{ --- 60 unchanged lines hidden --- |