1/*
2 * Copyright (c) 2007-2008 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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55#include "mem/packet_access.hh"
56#include "mem/page_table.hh"
57#include "mem/request.hh"
58#include "sim/full_system.hh"
59#include "sim/process.hh"
60
61namespace X86ISA {
62
63TLB::TLB(const Params *p) : BaseTLB(p), configAddress(0), size(p->size)
64{
65 tlb = new TlbEntry[size];
66 std::memset(tlb, 0, sizeof(TlbEntry) * size);
67
68 for (int x = 0; x < size; x++)
69 freeList.push_back(&tlb[x]);
70
71 walker = p->walker;
72 walker->setTLB(this);
73}
74
75TlbEntry *
76TLB::insert(Addr vpn, TlbEntry &entry)
77{
78 //TODO Deal with conflicting entries
79
80 TlbEntry *newEntry = NULL;
81 if (!freeList.empty()) {
82 newEntry = freeList.front();
83 freeList.pop_front();
84 } else {
85 newEntry = entryList.back();
86 entryList.pop_back();
87 }
88 *newEntry = entry;
89 newEntry->vaddr = vpn;
90 entryList.push_front(newEntry);
91 return newEntry;
92}
93
94TLB::EntryList::iterator
95TLB::lookupIt(Addr va, bool update_lru)
96{
97 //TODO make this smarter at some point
98 EntryList::iterator entry;
99 for (entry = entryList.begin(); entry != entryList.end(); entry++) {
100 if ((*entry)->vaddr <= va && (*entry)->vaddr + (*entry)->size > va) {
101 DPRINTF(TLB, "Matched vaddr %#x to entry starting at %#x "
102 "with size %#x.\n", va, (*entry)->vaddr, (*entry)->size);
103 if (update_lru) {
104 entryList.push_front(*entry);
105 entryList.erase(entry);
106 entry = entryList.begin();
107 }
108 break;
109 }
110 }
111 return entry;
112}
113
114TlbEntry *
115TLB::lookup(Addr va, bool update_lru)
116{
117 EntryList::iterator entry = lookupIt(va, update_lru);
118 if (entry == entryList.end())
119 return NULL;
120 else
121 return *entry;
122}
123
124void
125TLB::invalidateAll()
126{
127 DPRINTF(TLB, "Invalidating all entries.\n");
128 while (!entryList.empty()) {
129 TlbEntry *entry = entryList.front();
130 entryList.pop_front();
131 freeList.push_back(entry);
132 }
133}
134
135void
136TLB::setConfigAddress(uint32_t addr)
137{
138 configAddress = addr;
139}
140
141void
142TLB::invalidateNonGlobal()
143{
144 DPRINTF(TLB, "Invalidating all non global entries.\n");
145 EntryList::iterator entryIt;
146 for (entryIt = entryList.begin(); entryIt != entryList.end();) {
147 if (!(*entryIt)->global) {
148 freeList.push_back(*entryIt);
149 entryList.erase(entryIt++);
150 } else {
151 entryIt++;
152 }
153 }
154}
155
156void
157TLB::demapPage(Addr va, uint64_t asn)
158{
159 EntryList::iterator entry = lookupIt(va, false);
160 if (entry != entryList.end()) {
161 freeList.push_back(*entry);
162 entryList.erase(entry);
163 }
164}
165
166Fault
167TLB::translateInt(RequestPtr req, ThreadContext *tc)
168{
169 DPRINTF(TLB, "Addresses references internal memory.\n");
170 Addr vaddr = req->getVaddr();

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340 return new PageFault(vaddr, true, mode, inUser, false);
341 }
342 if (storeCheck && badWrite) {
343 // This would fault if this were a write, so return a page
344 // fault that reflects that happening.
345 return new PageFault(vaddr, true, Write, inUser, false);
346 }
347
348 Addr paddr = entry->paddr | (vaddr & (entry->size-1));
349 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, paddr);
350 req->setPaddr(paddr);
351 if (entry->uncacheable)
352 req->setFlags(Request::UNCACHEABLE);
353 } else {
354 //Use the address which already has segmentation applied.
355 DPRINTF(TLB, "Paging disabled.\n");
356 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr);

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