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1/*
2 * Copyright (c) 2007-2008 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 */
39
40#include <cstring>
41
42#include "arch/x86/insts/microldstop.hh"
43#include "arch/x86/regs/misc.hh"
44#include "arch/x86/regs/msr.hh"
45#include "arch/x86/faults.hh"
46#include "arch/x86/pagetable.hh"
47#include "arch/x86/pagetable_walker.hh"
48#include "arch/x86/tlb.hh"
49#include "arch/x86/x86_traits.hh"
50#include "base/bitfield.hh"
51#include "base/trace.hh"
52#include "cpu/base.hh"
53#include "cpu/thread_context.hh"
54#include "debug/TLB.hh"
55#include "mem/packet_access.hh"
56#include "mem/page_table.hh"
57#include "mem/request.hh"
58#include "sim/full_system.hh"
59#include "sim/process.hh"
60
61namespace X86ISA {
62
63TLB::TLB(const Params *p) : BaseTLB(p), configAddress(0), size(p->size),
64 lruSeq(0)
65{
66 if (!size)
67 fatal("TLBs must have a non-zero size.\n");
68 tlb = new TlbEntry[size];
69 std::memset(tlb, 0, sizeof(TlbEntry) * size);
70
71 for (int x = 0; x < size; x++) {
72 tlb[x].trieHandle = NULL;
73 freeList.push_back(&tlb[x]);
74 }
75
76 walker = p->walker;
77 walker->setTLB(this);
78}
79
80void
81TLB::evictLRU()
82{
83 // Find the entry with the lowest (and hence least recently updated)
84 // sequence number.
85
86 unsigned lru = 0;
87 for (unsigned i = 1; i < size; i++) {
88 if (tlb[i].lruSeq < tlb[lru].lruSeq)
89 lru = i;
90 }
91
92 assert(tlb[lru].trieHandle);
93 trie.remove(tlb[lru].trieHandle);
94 tlb[lru].trieHandle = NULL;
95 freeList.push_back(&tlb[lru]);
96}
97
98TlbEntry *
99TLB::insert(Addr vpn, TlbEntry &entry)
100{
101 //TODO Deal with conflicting entries
102
103 TlbEntry *newEntry = NULL;
104 if (freeList.empty())
105 evictLRU();
106 newEntry = freeList.front();
107 freeList.pop_front();
108
109 *newEntry = entry;
110 newEntry->lruSeq = nextSeq();
111 newEntry->vaddr = vpn;
112 newEntry->trieHandle =
113 trie.insert(vpn, TlbEntryTrie::MaxBits - entry.logBytes, newEntry);
114 return newEntry;
115}
116
117TlbEntry *
118TLB::lookup(Addr va, bool update_lru)
119{
120 TlbEntry *entry = trie.lookup(va);
121 if (entry && update_lru)
122 entry->lruSeq = nextSeq();
123 return entry;
124}
125
126void
127TLB::invalidateAll()
128{
129 DPRINTF(TLB, "Invalidating all entries.\n");
130 for (unsigned i = 0; i < size; i++) {
131 if (tlb[i].trieHandle) {
132 trie.remove(tlb[i].trieHandle);
133 tlb[i].trieHandle = NULL;
134 freeList.push_back(&tlb[i]);
135 }
136 }
137}
138
139void
140TLB::setConfigAddress(uint32_t addr)
141{
142 configAddress = addr;
143}
144
145void
146TLB::invalidateNonGlobal()
147{
148 DPRINTF(TLB, "Invalidating all non global entries.\n");
149 for (unsigned i = 0; i < size; i++) {
150 if (tlb[i].trieHandle && !tlb[i].global) {
151 trie.remove(tlb[i].trieHandle);
152 tlb[i].trieHandle = NULL;
153 freeList.push_back(&tlb[i]);
154 }
155 }
156}
157
158void
159TLB::demapPage(Addr va, uint64_t asn)
160{
161 TlbEntry *entry = trie.lookup(va);
162 if (entry) {
163 trie.remove(entry->trieHandle);
164 entry->trieHandle = NULL;
165 freeList.push_back(entry);
166 }
167}
168
169Fault
170TLB::translateInt(RequestPtr req, ThreadContext *tc)
171{
172 DPRINTF(TLB, "Addresses references internal memory.\n");
173 Addr vaddr = req->getVaddr();
174 Addr prefix = (vaddr >> 3) & IntAddrPrefixMask;
175 if (prefix == IntAddrPrefixCPUID) {
176 panic("CPUID memory space not yet implemented!\n");
177 } else if (prefix == IntAddrPrefixMSR) {
178 vaddr = (vaddr >> 3) & ~IntAddrPrefixMask;
179 req->setFlags(Request::MMAPPED_IPR);
180
181 MiscRegIndex regNum;
182 if (!msrAddrToIndex(regNum, vaddr))
183 return new GeneralProtection(0);
184
185 //The index is multiplied by the size of a MiscReg so that
186 //any memory dependence calculations will not see these as
187 //overlapping.
188 req->setPaddr((Addr)regNum * sizeof(MiscReg));
189 return NoFault;
190 } else if (prefix == IntAddrPrefixIO) {
191 // TODO If CPL > IOPL or in virtual mode, check the I/O permission
192 // bitmap in the TSS.
193
194 Addr IOPort = vaddr & ~IntAddrPrefixMask;
195 // Make sure the address fits in the expected 16 bit IO address
196 // space.
197 assert(!(IOPort & ~0xFFFF));
198 if (IOPort == 0xCF8 && req->getSize() == 4) {
199 req->setFlags(Request::MMAPPED_IPR);
200 req->setPaddr(MISCREG_PCI_CONFIG_ADDRESS * sizeof(MiscReg));
201 } else if ((IOPort & ~mask(2)) == 0xCFC) {
202 req->setFlags(Request::UNCACHEABLE);
203 Addr configAddress =
204 tc->readMiscRegNoEffect(MISCREG_PCI_CONFIG_ADDRESS);
205 if (bits(configAddress, 31, 31)) {
206 req->setPaddr(PhysAddrPrefixPciConfig |
207 mbits(configAddress, 30, 2) |
208 (IOPort & mask(2)));
209 } else {
210 req->setPaddr(PhysAddrPrefixIO | IOPort);
211 }
212 } else {
213 req->setFlags(Request::UNCACHEABLE);
214 req->setPaddr(PhysAddrPrefixIO | IOPort);
215 }
216 return NoFault;
217 } else {
218 panic("Access to unrecognized internal address space %#x.\n",
219 prefix);
220 }
221}
222
223Fault
224TLB::translate(RequestPtr req, ThreadContext *tc, Translation *translation,
225 Mode mode, bool &delayedResponse, bool timing)
226{
227 uint32_t flags = req->getFlags();
228 int seg = flags & SegmentFlagMask;
229 bool storeCheck = flags & (StoreCheck << FlagShift);
230
231 delayedResponse = false;
232
233 // If this is true, we're dealing with a request to a non-memory address
234 // space.
235 if (seg == SEGMENT_REG_MS) {
236 return translateInt(req, tc);
237 }
238
239 Addr vaddr = req->getVaddr();
240 DPRINTF(TLB, "Translating vaddr %#x.\n", vaddr);
241
242 HandyM5Reg m5Reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
243
244 // If protected mode has been enabled...
245 if (m5Reg.prot) {
246 DPRINTF(TLB, "In protected mode.\n");
247 // If we're not in 64-bit mode, do protection/limit checks
248 if (m5Reg.mode != LongMode) {
249 DPRINTF(TLB, "Not in long mode. Checking segment protection.\n");
250 // Check for a NULL segment selector.
251 if (!(seg == SEGMENT_REG_TSG || seg == SYS_SEGMENT_REG_IDTR ||
252 seg == SEGMENT_REG_HS || seg == SEGMENT_REG_LS)
253 && !tc->readMiscRegNoEffect(MISCREG_SEG_SEL(seg)))
254 return new GeneralProtection(0);
255 bool expandDown = false;
256 SegAttr attr = tc->readMiscRegNoEffect(MISCREG_SEG_ATTR(seg));
257 if (seg >= SEGMENT_REG_ES && seg <= SEGMENT_REG_HS) {
258 if (!attr.writable && (mode == Write || storeCheck))
259 return new GeneralProtection(0);
260 if (!attr.readable && mode == Read)
261 return new GeneralProtection(0);
262 expandDown = attr.expandDown;
263
264 }
265 Addr base = tc->readMiscRegNoEffect(MISCREG_SEG_BASE(seg));
266 Addr limit = tc->readMiscRegNoEffect(MISCREG_SEG_LIMIT(seg));
267 // This assumes we're not in 64 bit mode. If we were, the default
268 // address size is 64 bits, overridable to 32.
269 int size = 32;
270 bool sizeOverride = (flags & (AddrSizeFlagBit << FlagShift));
271 SegAttr csAttr = tc->readMiscRegNoEffect(MISCREG_CS_ATTR);
272 if ((csAttr.defaultSize && sizeOverride) ||
273 (!csAttr.defaultSize && !sizeOverride))
274 size = 16;
275 Addr offset = bits(vaddr - base, size-1, 0);
276 Addr endOffset = offset + req->getSize() - 1;
277 if (expandDown) {
278 DPRINTF(TLB, "Checking an expand down segment.\n");
279 warn_once("Expand down segments are untested.\n");
280 if (offset <= limit || endOffset <= limit)
281 return new GeneralProtection(0);
282 } else {
283 if (offset > limit || endOffset > limit)
284 return new GeneralProtection(0);
285 }
286 }
287 if (m5Reg.mode != LongMode ||
288 (flags & (AddrSizeFlagBit << FlagShift)))
289 vaddr &= mask(32);
290 // If paging is enabled, do the translation.
291 if (m5Reg.paging) {
292 DPRINTF(TLB, "Paging enabled.\n");
293 // The vaddr already has the segment base applied.
294 TlbEntry *entry = lookup(vaddr);
295 if (!entry) {
296 if (FullSystem) {
297 Fault fault = walker->start(tc, translation, req, mode);
298 if (timing || fault != NoFault) {
299 // This gets ignored in atomic mode.
300 delayedResponse = true;
301 return fault;
302 }
303 entry = lookup(vaddr);
304 assert(entry);
305 } else {
306 DPRINTF(TLB, "Handling a TLB miss for "
307 "address %#x at pc %#x.\n",
308 vaddr, tc->instAddr());
309
310 Process *p = tc->getProcessPtr();
311 TlbEntry newEntry;
312 bool success = p->pTable->lookup(vaddr, newEntry);
313 if (!success && mode != Execute) {
314 // Check if we just need to grow the stack.
315 if (p->fixupStackFault(vaddr)) {
316 // If we did, lookup the entry for the new page.
317 success = p->pTable->lookup(vaddr, newEntry);
318 }
319 }
320 if (!success) {
321 return new PageFault(vaddr, true, mode, true, false);
322 } else {
323 Addr alignedVaddr = p->pTable->pageAlign(vaddr);
324 DPRINTF(TLB, "Mapping %#x to %#x\n", alignedVaddr,
325 newEntry.pageStart());
326 entry = insert(alignedVaddr, newEntry);
327 }
328 DPRINTF(TLB, "Miss was serviced.\n");
329 }
330 }
331
332 DPRINTF(TLB, "Entry found with paddr %#x, "
333 "doing protection checks.\n", entry->paddr);
334 // Do paging protection checks.
335 bool inUser = (m5Reg.cpl == 3 &&
336 !(flags & (CPL0FlagBit << FlagShift)));
337 CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0);
338 bool badWrite = (!entry->writable && (inUser || cr0.wp));
339 if ((inUser && !entry->user) || (mode == Write && badWrite)) {
340 // The page must have been present to get into the TLB in
341 // the first place. We'll assume the reserved bits are
342 // fine even though we're not checking them.
343 return new PageFault(vaddr, true, mode, inUser, false);
344 }
345 if (storeCheck && badWrite) {
346 // This would fault if this were a write, so return a page
347 // fault that reflects that happening.
348 return new PageFault(vaddr, true, Write, inUser, false);
349 }
350
351 Addr paddr = entry->paddr | (vaddr & mask(entry->logBytes));
352 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, paddr);
353 req->setPaddr(paddr);
354 if (entry->uncacheable)
355 req->setFlags(Request::UNCACHEABLE);
356 } else {
357 //Use the address which already has segmentation applied.
358 DPRINTF(TLB, "Paging disabled.\n");
359 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr);
360 req->setPaddr(vaddr);
361 }
362 } else {
363 // Real mode
364 DPRINTF(TLB, "In real mode.\n");
365 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr);
366 req->setPaddr(vaddr);
367 }
368 // Check for an access to the local APIC
369 if (FullSystem) {
370 LocalApicBase localApicBase =
371 tc->readMiscRegNoEffect(MISCREG_APIC_BASE);
372 Addr baseAddr = localApicBase.base * PageBytes;
373 Addr paddr = req->getPaddr();
374 if (baseAddr <= paddr && baseAddr + PageBytes > paddr) {
375 // The Intel developer's manuals say the below restrictions apply,
376 // but the linux kernel, because of a compiler optimization, breaks
377 // them.
378 /*
379 // Check alignment
380 if (paddr & ((32/8) - 1))
381 return new GeneralProtection(0);
382 // Check access size
383 if (req->getSize() != (32/8))
384 return new GeneralProtection(0);
385 */
386 // Force the access to be uncacheable.
387 req->setFlags(Request::UNCACHEABLE);
388 req->setPaddr(x86LocalAPICAddress(tc->contextId(),
389 paddr - baseAddr));
390 }
391 }
392 return NoFault;
393}
394
395Fault
396TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
397{
398 bool delayedResponse;
399 return TLB::translate(req, tc, NULL, mode, delayedResponse, false);
400}
401
402void
403TLB::translateTiming(RequestPtr req, ThreadContext *tc,
404 Translation *translation, Mode mode)
405{
406 bool delayedResponse;
407 assert(translation);
408 Fault fault =
409 TLB::translate(req, tc, translation, mode, delayedResponse, true);
410 if (!delayedResponse)
411 translation->finish(fault, req, tc, mode);
412}
413
414Fault
415TLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode)
416{
417 panic("Not implemented\n");
418 return NoFault;
419}
420
421Walker *
422TLB::getWalker()
423{
424 return walker;
425}
426
427void
428TLB::serialize(std::ostream &os)
429{
430}
431
432void
433TLB::unserialize(Checkpoint *cp, const std::string &section)
434{
435}
436
437MasterPort *
438TLB::getMasterPort()
439{
440 return &walker->getMasterPort("port");
441}
442
443} // namespace X86ISA
444
445X86ISA::TLB *
446X86TLBParams::create()
447{
448 return new X86ISA::TLB(this);
449}