1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * Redistribution and use of this software in source and binary forms,
6 * with or without modification, are permitted provided that the
7 * following conditions are met:
8 *
9 * The software must be used only for Non-Commercial Use which means any
10 * use which is NOT directed to receiving any direct monetary
11 * compensation for, or commercial advantage from such use. Illustrative
12 * examples of non-commercial use are academic research, personal study,
13 * teaching, education and corporate research & development.
14 * Illustrative examples of commercial use are distributing products for
15 * commercial advantage and providing services using the software for
16 * commercial advantage.
17 *
18 * If you wish to use this software or functionality therein that may be
19 * covered by patents for commercial use, please contact:
20 * Director of Intellectual Property Licensing
21 * Office of Strategy and Technology
22 * Hewlett-Packard Company
23 * 1501 Page Mill Road
24 * Palo Alto, California 94304
25 *
26 * Redistributions of source code must retain the above copyright notice,
27 * this list of conditions and the following disclaimer. Redistributions
28 * in binary form must reproduce the above copyright notice, this list of
29 * conditions and the following disclaimer in the documentation and/or
30 * other materials provided with the distribution. Neither the name of
31 * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
32 * contributors may be used to endorse or promote products derived from
33 * this software without specific prior written permission. No right of
34 * sublicense is granted herewith. Derivatives of the software and
35 * output created using the software may be prepared, but only for
36 * Non-Commercial Uses. Derivatives of the software may be shared with
37 * others provided: (i) the others agree to abide by the list of
38 * conditions herein which includes the Non-Commercial Use restrictions;
39 * and (ii) such Derivatives of the software include the above copyright
40 * notice to acknowledge the contribution from this software where
41 * applicable, this list of conditions and the disclaimer below.
42 *
43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
46 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
47 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
49 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 *
55 * Authors: Gabe Black
56 */
57
58#include "arch/x86/bios/smbios.hh"
| 1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * Redistribution and use of this software in source and binary forms,
6 * with or without modification, are permitted provided that the
7 * following conditions are met:
8 *
9 * The software must be used only for Non-Commercial Use which means any
10 * use which is NOT directed to receiving any direct monetary
11 * compensation for, or commercial advantage from such use. Illustrative
12 * examples of non-commercial use are academic research, personal study,
13 * teaching, education and corporate research & development.
14 * Illustrative examples of commercial use are distributing products for
15 * commercial advantage and providing services using the software for
16 * commercial advantage.
17 *
18 * If you wish to use this software or functionality therein that may be
19 * covered by patents for commercial use, please contact:
20 * Director of Intellectual Property Licensing
21 * Office of Strategy and Technology
22 * Hewlett-Packard Company
23 * 1501 Page Mill Road
24 * Palo Alto, California 94304
25 *
26 * Redistributions of source code must retain the above copyright notice,
27 * this list of conditions and the following disclaimer. Redistributions
28 * in binary form must reproduce the above copyright notice, this list of
29 * conditions and the following disclaimer in the documentation and/or
30 * other materials provided with the distribution. Neither the name of
31 * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
32 * contributors may be used to endorse or promote products derived from
33 * this software without specific prior written permission. No right of
34 * sublicense is granted herewith. Derivatives of the software and
35 * output created using the software may be prepared, but only for
36 * Non-Commercial Uses. Derivatives of the software may be shared with
37 * others provided: (i) the others agree to abide by the list of
38 * conditions herein which includes the Non-Commercial Use restrictions;
39 * and (ii) such Derivatives of the software include the above copyright
40 * notice to acknowledge the contribution from this software where
41 * applicable, this list of conditions and the disclaimer below.
42 *
43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
46 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
47 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
49 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 *
55 * Authors: Gabe Black
56 */
57
58#include "arch/x86/bios/smbios.hh"
|
| 59#include "arch/x86/bios/intelmp.hh"
|
59#include "arch/x86/miscregs.hh"
60#include "arch/x86/system.hh"
61#include "arch/vtophys.hh"
| 60#include "arch/x86/miscregs.hh"
61#include "arch/x86/system.hh"
62#include "arch/vtophys.hh"
|
62#include "base/remote_gdb.hh"
| 63#include "base/intmath.hh"
|
63#include "base/loader/object_file.hh"
64#include "base/loader/symtab.hh"
| 64#include "base/loader/object_file.hh"
65#include "base/loader/symtab.hh"
|
| 66#include "base/remote_gdb.hh"
|
65#include "base/trace.hh"
66#include "cpu/thread_context.hh"
67#include "mem/physical.hh"
68#include "params/X86System.hh"
69#include "sim/byteswap.hh"
70
71
72using namespace LittleEndianGuest;
73using namespace X86ISA;
74
| 67#include "base/trace.hh"
68#include "cpu/thread_context.hh"
69#include "mem/physical.hh"
70#include "params/X86System.hh"
71#include "sim/byteswap.hh"
72
73
74using namespace LittleEndianGuest;
75using namespace X86ISA;
76
|
75X86System::X86System(Params *p)
76 : System(p), smbiosTable(p->smbios_table)
| 77X86System::X86System(Params *p) :
78 System(p), smbiosTable(p->smbios_table),
79 mpFloatingPointer(p->intel_mp_pointer),
80 mpConfigTable(p->intel_mp_table)
|
77{}
78
79void
80X86System::startup()
81{
82 System::startup();
83 // This is the boot strap processor (BSP). Initialize it to look like
84 // the boot loader has just turned control over to the 64 bit OS. We
85 // won't actually set up real mode or legacy protected mode descriptor
86 // tables because we aren't executing any code that would require
87 // them. We do, however toggle the control bits in the correct order
88 // while allowing consistency checks and the underlying mechansims
89 // just to be safe.
90
91 const int NumPDTs = 4;
92
93 const Addr PageMapLevel4 = 0x70000;
94 const Addr PageDirPtrTable = 0x71000;
95 const Addr PageDirTable[NumPDTs] =
96 {0x72000, 0x73000, 0x74000, 0x75000};
97 const Addr GDTBase = 0x76000;
98
99 const int PML4Bits = 9;
100 const int PDPTBits = 9;
101 const int PDTBits = 9;
102
103 // Get a port to write the page tables and descriptor tables.
104 FunctionalPort * physPort = threadContexts[0]->getPhysPort();
105
106 /*
107 * Set up the gdt.
108 */
109 // Place holder at selector 0
110 uint64_t nullDescriptor = 0;
111 physPort->writeBlob(GDTBase, (uint8_t *)(&nullDescriptor), 8);
112
113 //64 bit code segment
114 SegDescriptor csDesc = 0;
115 csDesc.type.c = 0; // Not conforming
116 csDesc.dpl = 0; // Privelege level 0
117 csDesc.p = 1; // Present
118 csDesc.l = 1; // 64 bit
119 csDesc.d = 0; // default operand size
120 //Because we're dealing with a pointer and I don't think it's
121 //guaranteed that there isn't anything in a nonvirtual class between
122 //it's beginning in memory and it's actual data, we'll use an
123 //intermediary.
124 uint64_t csDescVal = csDesc;
125 physPort->writeBlob(GDTBase, (uint8_t *)(&csDescVal), 8);
126
127 threadContexts[0]->setMiscReg(MISCREG_TSG_BASE, GDTBase);
128 threadContexts[0]->setMiscReg(MISCREG_TSG_LIMIT, 0xF);
129
130 /*
131 * Identity map the first 4GB of memory. In order to map this region
132 * of memory in long mode, there needs to be one actual page map level
133 * 4 entry which points to one page directory pointer table which
134 * points to 4 different page directory tables which are full of two
135 * megabyte pages. All of the other entries in valid tables are set
136 * to indicate that they don't pertain to anything valid and will
137 * cause a fault if used.
138 */
139
140 // Put valid values in all of the various table entries which indicate
141 // that those entries don't point to further tables or pages. Then
142 // set the values of those entries which are needed.
143
144 // Page Map Level 4
145
146 // read/write, user, not present
147 uint64_t pml4e = X86ISA::htog(0x6);
148 for (int offset = 0; offset < (1 << PML4Bits) * 8; offset += 8) {
149 physPort->writeBlob(PageMapLevel4 + offset, (uint8_t *)(&pml4e), 8);
150 }
151 // Point to the only PDPT
152 pml4e = X86ISA::htog(0x7 | PageDirPtrTable);
153 physPort->writeBlob(PageMapLevel4, (uint8_t *)(&pml4e), 8);
154
155 // Page Directory Pointer Table
156
157 // read/write, user, not present
158 uint64_t pdpe = X86ISA::htog(0x6);
159 for (int offset = 0; offset < (1 << PDPTBits) * 8; offset += 8) {
160 physPort->writeBlob(PageDirPtrTable + offset,
161 (uint8_t *)(&pdpe), 8);
162 }
163 // Point to the PDTs
164 for (int table = 0; table < NumPDTs; table++) {
165 pdpe = X86ISA::htog(0x7 | PageDirTable[table]);
166 physPort->writeBlob(PageDirPtrTable + table * 8,
167 (uint8_t *)(&pdpe), 8);
168 }
169
170 // Page Directory Tables
171
172 Addr base = 0;
173 const Addr pageSize = 2 << 20;
174 for (int table = 0; table < NumPDTs; table++) {
175 for (int offset = 0; offset < (1 << PDTBits) * 8; offset += 8) {
176 // read/write, user, present, 4MB
177 uint64_t pdte = X86ISA::htog(0x87 | base);
178 physPort->writeBlob(PageDirTable[table] + offset,
179 (uint8_t *)(&pdte), 8);
180 base += pageSize;
181 }
182 }
183
184 /*
185 * Transition from real mode all the way up to Long mode
186 */
187 CR0 cr0 = threadContexts[0]->readMiscRegNoEffect(MISCREG_CR0);
188 //Turn off paging.
189 cr0.pg = 0;
190 threadContexts[0]->setMiscReg(MISCREG_CR0, cr0);
191 //Turn on protected mode.
192 cr0.pe = 1;
193 threadContexts[0]->setMiscReg(MISCREG_CR0, cr0);
194
195 CR4 cr4 = threadContexts[0]->readMiscRegNoEffect(MISCREG_CR4);
196 //Turn on pae.
197 cr4.pae = 1;
198 threadContexts[0]->setMiscReg(MISCREG_CR4, cr4);
199
200 //Point to the page tables.
201 threadContexts[0]->setMiscReg(MISCREG_CR3, PageMapLevel4);
202
203 Efer efer = threadContexts[0]->readMiscRegNoEffect(MISCREG_EFER);
204 //Enable long mode.
205 efer.lme = 1;
206 threadContexts[0]->setMiscReg(MISCREG_EFER, efer);
207
208 //Activate long mode.
209 cr0.pg = 1;
210 threadContexts[0]->setMiscReg(MISCREG_CR0, cr0);
211
212 /*
213 * Far jump into 64 bit mode.
214 */
215 // Set the selector
216 threadContexts[0]->setMiscReg(MISCREG_CS, 1);
217 // Manually set up the segment attributes. In the future when there's
218 // other existing functionality to do this, that could be used
219 // instead.
220 SegAttr csAttr = 0;
221 csAttr.writable = 0;
222 csAttr.readable = 1;
223 csAttr.expandDown = 0;
224 csAttr.dpl = 0;
225 csAttr.defaultSize = 0;
226 csAttr.longMode = 1;
227 threadContexts[0]->setMiscReg(MISCREG_CS_ATTR, csAttr);
228
229 threadContexts[0]->setPC(threadContexts[0]->getSystemPtr()->kernelEntry);
230 threadContexts[0]->setNextPC(threadContexts[0]->readPC());
231
232 // We should now be in long mode. Yay!
233
234 Addr ebdaPos = 0xF0000;
| 81{}
82
83void
84X86System::startup()
85{
86 System::startup();
87 // This is the boot strap processor (BSP). Initialize it to look like
88 // the boot loader has just turned control over to the 64 bit OS. We
89 // won't actually set up real mode or legacy protected mode descriptor
90 // tables because we aren't executing any code that would require
91 // them. We do, however toggle the control bits in the correct order
92 // while allowing consistency checks and the underlying mechansims
93 // just to be safe.
94
95 const int NumPDTs = 4;
96
97 const Addr PageMapLevel4 = 0x70000;
98 const Addr PageDirPtrTable = 0x71000;
99 const Addr PageDirTable[NumPDTs] =
100 {0x72000, 0x73000, 0x74000, 0x75000};
101 const Addr GDTBase = 0x76000;
102
103 const int PML4Bits = 9;
104 const int PDPTBits = 9;
105 const int PDTBits = 9;
106
107 // Get a port to write the page tables and descriptor tables.
108 FunctionalPort * physPort = threadContexts[0]->getPhysPort();
109
110 /*
111 * Set up the gdt.
112 */
113 // Place holder at selector 0
114 uint64_t nullDescriptor = 0;
115 physPort->writeBlob(GDTBase, (uint8_t *)(&nullDescriptor), 8);
116
117 //64 bit code segment
118 SegDescriptor csDesc = 0;
119 csDesc.type.c = 0; // Not conforming
120 csDesc.dpl = 0; // Privelege level 0
121 csDesc.p = 1; // Present
122 csDesc.l = 1; // 64 bit
123 csDesc.d = 0; // default operand size
124 //Because we're dealing with a pointer and I don't think it's
125 //guaranteed that there isn't anything in a nonvirtual class between
126 //it's beginning in memory and it's actual data, we'll use an
127 //intermediary.
128 uint64_t csDescVal = csDesc;
129 physPort->writeBlob(GDTBase, (uint8_t *)(&csDescVal), 8);
130
131 threadContexts[0]->setMiscReg(MISCREG_TSG_BASE, GDTBase);
132 threadContexts[0]->setMiscReg(MISCREG_TSG_LIMIT, 0xF);
133
134 /*
135 * Identity map the first 4GB of memory. In order to map this region
136 * of memory in long mode, there needs to be one actual page map level
137 * 4 entry which points to one page directory pointer table which
138 * points to 4 different page directory tables which are full of two
139 * megabyte pages. All of the other entries in valid tables are set
140 * to indicate that they don't pertain to anything valid and will
141 * cause a fault if used.
142 */
143
144 // Put valid values in all of the various table entries which indicate
145 // that those entries don't point to further tables or pages. Then
146 // set the values of those entries which are needed.
147
148 // Page Map Level 4
149
150 // read/write, user, not present
151 uint64_t pml4e = X86ISA::htog(0x6);
152 for (int offset = 0; offset < (1 << PML4Bits) * 8; offset += 8) {
153 physPort->writeBlob(PageMapLevel4 + offset, (uint8_t *)(&pml4e), 8);
154 }
155 // Point to the only PDPT
156 pml4e = X86ISA::htog(0x7 | PageDirPtrTable);
157 physPort->writeBlob(PageMapLevel4, (uint8_t *)(&pml4e), 8);
158
159 // Page Directory Pointer Table
160
161 // read/write, user, not present
162 uint64_t pdpe = X86ISA::htog(0x6);
163 for (int offset = 0; offset < (1 << PDPTBits) * 8; offset += 8) {
164 physPort->writeBlob(PageDirPtrTable + offset,
165 (uint8_t *)(&pdpe), 8);
166 }
167 // Point to the PDTs
168 for (int table = 0; table < NumPDTs; table++) {
169 pdpe = X86ISA::htog(0x7 | PageDirTable[table]);
170 physPort->writeBlob(PageDirPtrTable + table * 8,
171 (uint8_t *)(&pdpe), 8);
172 }
173
174 // Page Directory Tables
175
176 Addr base = 0;
177 const Addr pageSize = 2 << 20;
178 for (int table = 0; table < NumPDTs; table++) {
179 for (int offset = 0; offset < (1 << PDTBits) * 8; offset += 8) {
180 // read/write, user, present, 4MB
181 uint64_t pdte = X86ISA::htog(0x87 | base);
182 physPort->writeBlob(PageDirTable[table] + offset,
183 (uint8_t *)(&pdte), 8);
184 base += pageSize;
185 }
186 }
187
188 /*
189 * Transition from real mode all the way up to Long mode
190 */
191 CR0 cr0 = threadContexts[0]->readMiscRegNoEffect(MISCREG_CR0);
192 //Turn off paging.
193 cr0.pg = 0;
194 threadContexts[0]->setMiscReg(MISCREG_CR0, cr0);
195 //Turn on protected mode.
196 cr0.pe = 1;
197 threadContexts[0]->setMiscReg(MISCREG_CR0, cr0);
198
199 CR4 cr4 = threadContexts[0]->readMiscRegNoEffect(MISCREG_CR4);
200 //Turn on pae.
201 cr4.pae = 1;
202 threadContexts[0]->setMiscReg(MISCREG_CR4, cr4);
203
204 //Point to the page tables.
205 threadContexts[0]->setMiscReg(MISCREG_CR3, PageMapLevel4);
206
207 Efer efer = threadContexts[0]->readMiscRegNoEffect(MISCREG_EFER);
208 //Enable long mode.
209 efer.lme = 1;
210 threadContexts[0]->setMiscReg(MISCREG_EFER, efer);
211
212 //Activate long mode.
213 cr0.pg = 1;
214 threadContexts[0]->setMiscReg(MISCREG_CR0, cr0);
215
216 /*
217 * Far jump into 64 bit mode.
218 */
219 // Set the selector
220 threadContexts[0]->setMiscReg(MISCREG_CS, 1);
221 // Manually set up the segment attributes. In the future when there's
222 // other existing functionality to do this, that could be used
223 // instead.
224 SegAttr csAttr = 0;
225 csAttr.writable = 0;
226 csAttr.readable = 1;
227 csAttr.expandDown = 0;
228 csAttr.dpl = 0;
229 csAttr.defaultSize = 0;
230 csAttr.longMode = 1;
231 threadContexts[0]->setMiscReg(MISCREG_CS_ATTR, csAttr);
232
233 threadContexts[0]->setPC(threadContexts[0]->getSystemPtr()->kernelEntry);
234 threadContexts[0]->setNextPC(threadContexts[0]->readPC());
235
236 // We should now be in long mode. Yay!
237
238 Addr ebdaPos = 0xF0000;
|
| 239 Addr fixed, table;
|
235
| 240
|
236 Addr headerSize, structSize;
| |
237 //Write out the SMBios/DMI table
| 241 //Write out the SMBios/DMI table
|
238 writeOutSMBiosTable(ebdaPos, headerSize, structSize);
239 ebdaPos += (headerSize + structSize);
| 242 writeOutSMBiosTable(ebdaPos, fixed, table);
243 ebdaPos += (fixed + table);
244 ebdaPos = roundUp(ebdaPos, 16);
245
246 //Write out the Intel MP Specification configuration table
247 writeOutMPTable(ebdaPos, fixed, table);
248 ebdaPos += (fixed + table);
|
240}
241
242void
243X86System::writeOutSMBiosTable(Addr header,
244 Addr &headerSize, Addr &structSize, Addr table)
245{
246 // Get a port to write the table and header to memory.
247 FunctionalPort * physPort = threadContexts[0]->getPhysPort();
248
249 // If the table location isn't specified, just put it after the header.
250 // The header size as of the 2.5 SMBios specification is 0x1F bytes
251 if (!table)
252 table = header + 0x1F;
253 smbiosTable->setTableAddr(table);
254
255 smbiosTable->writeOut(physPort, header, headerSize, structSize);
256
257 // Do some bounds checking to make sure we at least didn't step on
258 // ourselves.
259 assert(header > table || header + headerSize <= table);
260 assert(table > header || table + structSize <= header);
261}
262
| 249}
250
251void
252X86System::writeOutSMBiosTable(Addr header,
253 Addr &headerSize, Addr &structSize, Addr table)
254{
255 // Get a port to write the table and header to memory.
256 FunctionalPort * physPort = threadContexts[0]->getPhysPort();
257
258 // If the table location isn't specified, just put it after the header.
259 // The header size as of the 2.5 SMBios specification is 0x1F bytes
260 if (!table)
261 table = header + 0x1F;
262 smbiosTable->setTableAddr(table);
263
264 smbiosTable->writeOut(physPort, header, headerSize, structSize);
265
266 // Do some bounds checking to make sure we at least didn't step on
267 // ourselves.
268 assert(header > table || header + headerSize <= table);
269 assert(table > header || table + structSize <= header);
270}
271
|
| 272void
273X86System::writeOutMPTable(Addr fp,
274 Addr &fpSize, Addr &tableSize, Addr table)
275{
276 // Get a port to write the table and header to memory.
277 FunctionalPort * physPort = threadContexts[0]->getPhysPort();
|
263
| 278
|
| 279 // If the table location isn't specified and it exists, just put
280 // it after the floating pointer. The fp size as of the 1.4 Intel MP
281 // specification is 0x10 bytes.
282 if (mpConfigTable) {
283 if (!table)
284 table = fp + 0x10;
285 mpFloatingPointer->setTableAddr(table);
286 }
287
288 fpSize = mpFloatingPointer->writeOut(physPort, fp);
289 if (mpConfigTable)
290 tableSize = mpConfigTable->writeOut(physPort, table);
291 else
292 tableSize = 0;
293
294 // Do some bounds checking to make sure we at least didn't step on
295 // ourselves and the fp structure was the size we thought it was.
296 assert(fp > table || fp + fpSize <= table);
297 assert(table > fp || table + tableSize <= fp);
298 assert(fpSize == 0x10);
299}
300
301
|
264X86System::~X86System()
265{
266 delete smbiosTable;
267}
268
269void
270X86System::serialize(std::ostream &os)
271{
272 System::serialize(os);
273}
274
275
276void
277X86System::unserialize(Checkpoint *cp, const std::string §ion)
278{
279 System::unserialize(cp,section);
280}
281
282X86System *
283X86SystemParams::create()
284{
285 return new X86System(this);
286}
| 302X86System::~X86System()
303{
304 delete smbiosTable;
305}
306
307void
308X86System::serialize(std::ostream &os)
309{
310 System::serialize(os);
311}
312
313
314void
315X86System::unserialize(Checkpoint *cp, const std::string §ion)
316{
317 System::unserialize(cp,section);
318}
319
320X86System *
321X86SystemParams::create()
322{
323 return new X86System(this);
324}
|