1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * Redistribution and use of this software in source and binary forms,
6 * with or without modification, are permitted provided that the
7 * following conditions are met:
8 *
9 * The software must be used only for Non-Commercial Use which means any
10 * use which is NOT directed to receiving any direct monetary
11 * compensation for, or commercial advantage from such use. Illustrative
12 * examples of non-commercial use are academic research, personal study,
13 * teaching, education and corporate research & development.
14 * Illustrative examples of commercial use are distributing products for
15 * commercial advantage and providing services using the software for
16 * commercial advantage.
17 *
18 * If you wish to use this software or functionality therein that may be
19 * covered by patents for commercial use, please contact:
20 * Director of Intellectual Property Licensing
21 * Office of Strategy and Technology
22 * Hewlett-Packard Company
23 * 1501 Page Mill Road
24 * Palo Alto, California 94304
25 *
26 * Redistributions of source code must retain the above copyright notice,
27 * this list of conditions and the following disclaimer. Redistributions
28 * in binary form must reproduce the above copyright notice, this list of
29 * conditions and the following disclaimer in the documentation and/or
30 * other materials provided with the distribution. Neither the name of
31 * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
32 * contributors may be used to endorse or promote products derived from
33 * this software without specific prior written permission. No right of
34 * sublicense is granted herewith. Derivatives of the software and
35 * output created using the software may be prepared, but only for
36 * Non-Commercial Uses. Derivatives of the software may be shared with
37 * others provided: (i) the others agree to abide by the list of
38 * conditions herein which includes the Non-Commercial Use restrictions;
39 * and (ii) such Derivatives of the software include the above copyright
40 * notice to acknowledge the contribution from this software where
41 * applicable, this list of conditions and the disclaimer below.
42 *
43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
46 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
47 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
49 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 *
55 * Authors: Gabe Black
56 */
57
58#include "arch/x86/bios/smbios.hh"
59#include "arch/x86/miscregs.hh"
60#include "arch/x86/system.hh"
61#include "arch/vtophys.hh"
62#include "base/remote_gdb.hh"
63#include "base/loader/object_file.hh"
64#include "base/loader/symtab.hh"
65#include "base/trace.hh"
66#include "cpu/thread_context.hh"
67#include "mem/physical.hh"
68#include "params/X86System.hh"
69#include "sim/byteswap.hh"
70
71
72using namespace LittleEndianGuest;
73using namespace X86ISA;
74
75X86System::X86System(Params *p)
| 1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * Redistribution and use of this software in source and binary forms,
6 * with or without modification, are permitted provided that the
7 * following conditions are met:
8 *
9 * The software must be used only for Non-Commercial Use which means any
10 * use which is NOT directed to receiving any direct monetary
11 * compensation for, or commercial advantage from such use. Illustrative
12 * examples of non-commercial use are academic research, personal study,
13 * teaching, education and corporate research & development.
14 * Illustrative examples of commercial use are distributing products for
15 * commercial advantage and providing services using the software for
16 * commercial advantage.
17 *
18 * If you wish to use this software or functionality therein that may be
19 * covered by patents for commercial use, please contact:
20 * Director of Intellectual Property Licensing
21 * Office of Strategy and Technology
22 * Hewlett-Packard Company
23 * 1501 Page Mill Road
24 * Palo Alto, California 94304
25 *
26 * Redistributions of source code must retain the above copyright notice,
27 * this list of conditions and the following disclaimer. Redistributions
28 * in binary form must reproduce the above copyright notice, this list of
29 * conditions and the following disclaimer in the documentation and/or
30 * other materials provided with the distribution. Neither the name of
31 * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
32 * contributors may be used to endorse or promote products derived from
33 * this software without specific prior written permission. No right of
34 * sublicense is granted herewith. Derivatives of the software and
35 * output created using the software may be prepared, but only for
36 * Non-Commercial Uses. Derivatives of the software may be shared with
37 * others provided: (i) the others agree to abide by the list of
38 * conditions herein which includes the Non-Commercial Use restrictions;
39 * and (ii) such Derivatives of the software include the above copyright
40 * notice to acknowledge the contribution from this software where
41 * applicable, this list of conditions and the disclaimer below.
42 *
43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
46 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
47 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
49 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 *
55 * Authors: Gabe Black
56 */
57
58#include "arch/x86/bios/smbios.hh"
59#include "arch/x86/miscregs.hh"
60#include "arch/x86/system.hh"
61#include "arch/vtophys.hh"
62#include "base/remote_gdb.hh"
63#include "base/loader/object_file.hh"
64#include "base/loader/symtab.hh"
65#include "base/trace.hh"
66#include "cpu/thread_context.hh"
67#include "mem/physical.hh"
68#include "params/X86System.hh"
69#include "sim/byteswap.hh"
70
71
72using namespace LittleEndianGuest;
73using namespace X86ISA;
74
75X86System::X86System(Params *p)
|
76 : System(p)
77{
78 smbiosTable = new X86ISA::SMBios::SMBiosTable;
79 smbiosTable->smbiosHeader.majorVersion = 2;
80 smbiosTable->smbiosHeader.minorVersion = 5;
81 smbiosTable->smbiosHeader.intermediateHeader.smbiosBCDRevision = 0x25;
82}
| 76 : System(p), smbiosTable(p->smbios_table)
77{}
|
83
84void
85X86System::startup()
86{
87 System::startup();
88 // This is the boot strap processor (BSP). Initialize it to look like
89 // the boot loader has just turned control over to the 64 bit OS. We
90 // won't actually set up real mode or legacy protected mode descriptor
91 // tables because we aren't executing any code that would require
92 // them. We do, however toggle the control bits in the correct order
93 // while allowing consistency checks and the underlying mechansims
94 // just to be safe.
95
96 const int NumPDTs = 4;
97
98 const Addr PageMapLevel4 = 0x70000;
99 const Addr PageDirPtrTable = 0x71000;
100 const Addr PageDirTable[NumPDTs] =
101 {0x72000, 0x73000, 0x74000, 0x75000};
102 const Addr GDTBase = 0x76000;
103
104 const int PML4Bits = 9;
105 const int PDPTBits = 9;
106 const int PDTBits = 9;
107
108 // Get a port to write the page tables and descriptor tables.
109 FunctionalPort * physPort = threadContexts[0]->getPhysPort();
110
111 /*
112 * Set up the gdt.
113 */
114 // Place holder at selector 0
115 uint64_t nullDescriptor = 0;
116 physPort->writeBlob(GDTBase, (uint8_t *)(&nullDescriptor), 8);
117
118 //64 bit code segment
119 SegDescriptor csDesc = 0;
120 csDesc.type.c = 0; // Not conforming
121 csDesc.dpl = 0; // Privelege level 0
122 csDesc.p = 1; // Present
123 csDesc.l = 1; // 64 bit
124 csDesc.d = 0; // default operand size
125 //Because we're dealing with a pointer and I don't think it's
126 //guaranteed that there isn't anything in a nonvirtual class between
127 //it's beginning in memory and it's actual data, we'll use an
128 //intermediary.
129 uint64_t csDescVal = csDesc;
130 physPort->writeBlob(GDTBase, (uint8_t *)(&csDescVal), 8);
131
132 threadContexts[0]->setMiscReg(MISCREG_TSG_BASE, GDTBase);
133 threadContexts[0]->setMiscReg(MISCREG_TSG_LIMIT, 0xF);
134
135 /*
136 * Identity map the first 4GB of memory. In order to map this region
137 * of memory in long mode, there needs to be one actual page map level
138 * 4 entry which points to one page directory pointer table which
139 * points to 4 different page directory tables which are full of two
140 * megabyte pages. All of the other entries in valid tables are set
141 * to indicate that they don't pertain to anything valid and will
142 * cause a fault if used.
143 */
144
145 // Put valid values in all of the various table entries which indicate
146 // that those entries don't point to further tables or pages. Then
147 // set the values of those entries which are needed.
148
149 // Page Map Level 4
150
151 // read/write, user, not present
152 uint64_t pml4e = X86ISA::htog(0x6);
153 for (int offset = 0; offset < (1 << PML4Bits) * 8; offset += 8) {
154 physPort->writeBlob(PageMapLevel4 + offset, (uint8_t *)(&pml4e), 8);
155 }
156 // Point to the only PDPT
157 pml4e = X86ISA::htog(0x7 | PageDirPtrTable);
158 physPort->writeBlob(PageMapLevel4, (uint8_t *)(&pml4e), 8);
159
160 // Page Directory Pointer Table
161
162 // read/write, user, not present
163 uint64_t pdpe = X86ISA::htog(0x6);
164 for (int offset = 0; offset < (1 << PDPTBits) * 8; offset += 8) {
165 physPort->writeBlob(PageDirPtrTable + offset,
166 (uint8_t *)(&pdpe), 8);
167 }
168 // Point to the PDTs
169 for (int table = 0; table < NumPDTs; table++) {
170 pdpe = X86ISA::htog(0x7 | PageDirTable[table]);
171 physPort->writeBlob(PageDirPtrTable + table * 8,
172 (uint8_t *)(&pdpe), 8);
173 }
174
175 // Page Directory Tables
176
177 Addr base = 0;
178 const Addr pageSize = 2 << 20;
179 for (int table = 0; table < NumPDTs; table++) {
180 for (int offset = 0; offset < (1 << PDTBits) * 8; offset += 8) {
181 // read/write, user, present, 4MB
182 uint64_t pdte = X86ISA::htog(0x87 | base);
183 physPort->writeBlob(PageDirTable[table] + offset,
184 (uint8_t *)(&pdte), 8);
185 base += pageSize;
186 }
187 }
188
189 /*
190 * Transition from real mode all the way up to Long mode
191 */
192 CR0 cr0 = threadContexts[0]->readMiscRegNoEffect(MISCREG_CR0);
193 //Turn off paging.
194 cr0.pg = 0;
195 threadContexts[0]->setMiscReg(MISCREG_CR0, cr0);
196 //Turn on protected mode.
197 cr0.pe = 1;
198 threadContexts[0]->setMiscReg(MISCREG_CR0, cr0);
199
200 CR4 cr4 = threadContexts[0]->readMiscRegNoEffect(MISCREG_CR4);
201 //Turn on pae.
202 cr4.pae = 1;
203 threadContexts[0]->setMiscReg(MISCREG_CR4, cr4);
204
205 //Point to the page tables.
206 threadContexts[0]->setMiscReg(MISCREG_CR3, PageMapLevel4);
207
208 Efer efer = threadContexts[0]->readMiscRegNoEffect(MISCREG_EFER);
209 //Enable long mode.
210 efer.lme = 1;
211 threadContexts[0]->setMiscReg(MISCREG_EFER, efer);
212
213 //Activate long mode.
214 cr0.pg = 1;
215 threadContexts[0]->setMiscReg(MISCREG_CR0, cr0);
216
217 /*
218 * Far jump into 64 bit mode.
219 */
220 // Set the selector
221 threadContexts[0]->setMiscReg(MISCREG_CS, 1);
222 // Manually set up the segment attributes. In the future when there's
223 // other existing functionality to do this, that could be used
224 // instead.
225 SegAttr csAttr = 0;
226 csAttr.writable = 0;
227 csAttr.readable = 1;
228 csAttr.expandDown = 0;
229 csAttr.dpl = 0;
230 csAttr.defaultSize = 0;
231 csAttr.longMode = 1;
232 threadContexts[0]->setMiscReg(MISCREG_CS_ATTR, csAttr);
233
234 threadContexts[0]->setPC(threadContexts[0]->getSystemPtr()->kernelEntry);
235 threadContexts[0]->setNextPC(threadContexts[0]->readPC());
236
237 // We should now be in long mode. Yay!
238
| 78
79void
80X86System::startup()
81{
82 System::startup();
83 // This is the boot strap processor (BSP). Initialize it to look like
84 // the boot loader has just turned control over to the 64 bit OS. We
85 // won't actually set up real mode or legacy protected mode descriptor
86 // tables because we aren't executing any code that would require
87 // them. We do, however toggle the control bits in the correct order
88 // while allowing consistency checks and the underlying mechansims
89 // just to be safe.
90
91 const int NumPDTs = 4;
92
93 const Addr PageMapLevel4 = 0x70000;
94 const Addr PageDirPtrTable = 0x71000;
95 const Addr PageDirTable[NumPDTs] =
96 {0x72000, 0x73000, 0x74000, 0x75000};
97 const Addr GDTBase = 0x76000;
98
99 const int PML4Bits = 9;
100 const int PDPTBits = 9;
101 const int PDTBits = 9;
102
103 // Get a port to write the page tables and descriptor tables.
104 FunctionalPort * physPort = threadContexts[0]->getPhysPort();
105
106 /*
107 * Set up the gdt.
108 */
109 // Place holder at selector 0
110 uint64_t nullDescriptor = 0;
111 physPort->writeBlob(GDTBase, (uint8_t *)(&nullDescriptor), 8);
112
113 //64 bit code segment
114 SegDescriptor csDesc = 0;
115 csDesc.type.c = 0; // Not conforming
116 csDesc.dpl = 0; // Privelege level 0
117 csDesc.p = 1; // Present
118 csDesc.l = 1; // 64 bit
119 csDesc.d = 0; // default operand size
120 //Because we're dealing with a pointer and I don't think it's
121 //guaranteed that there isn't anything in a nonvirtual class between
122 //it's beginning in memory and it's actual data, we'll use an
123 //intermediary.
124 uint64_t csDescVal = csDesc;
125 physPort->writeBlob(GDTBase, (uint8_t *)(&csDescVal), 8);
126
127 threadContexts[0]->setMiscReg(MISCREG_TSG_BASE, GDTBase);
128 threadContexts[0]->setMiscReg(MISCREG_TSG_LIMIT, 0xF);
129
130 /*
131 * Identity map the first 4GB of memory. In order to map this region
132 * of memory in long mode, there needs to be one actual page map level
133 * 4 entry which points to one page directory pointer table which
134 * points to 4 different page directory tables which are full of two
135 * megabyte pages. All of the other entries in valid tables are set
136 * to indicate that they don't pertain to anything valid and will
137 * cause a fault if used.
138 */
139
140 // Put valid values in all of the various table entries which indicate
141 // that those entries don't point to further tables or pages. Then
142 // set the values of those entries which are needed.
143
144 // Page Map Level 4
145
146 // read/write, user, not present
147 uint64_t pml4e = X86ISA::htog(0x6);
148 for (int offset = 0; offset < (1 << PML4Bits) * 8; offset += 8) {
149 physPort->writeBlob(PageMapLevel4 + offset, (uint8_t *)(&pml4e), 8);
150 }
151 // Point to the only PDPT
152 pml4e = X86ISA::htog(0x7 | PageDirPtrTable);
153 physPort->writeBlob(PageMapLevel4, (uint8_t *)(&pml4e), 8);
154
155 // Page Directory Pointer Table
156
157 // read/write, user, not present
158 uint64_t pdpe = X86ISA::htog(0x6);
159 for (int offset = 0; offset < (1 << PDPTBits) * 8; offset += 8) {
160 physPort->writeBlob(PageDirPtrTable + offset,
161 (uint8_t *)(&pdpe), 8);
162 }
163 // Point to the PDTs
164 for (int table = 0; table < NumPDTs; table++) {
165 pdpe = X86ISA::htog(0x7 | PageDirTable[table]);
166 physPort->writeBlob(PageDirPtrTable + table * 8,
167 (uint8_t *)(&pdpe), 8);
168 }
169
170 // Page Directory Tables
171
172 Addr base = 0;
173 const Addr pageSize = 2 << 20;
174 for (int table = 0; table < NumPDTs; table++) {
175 for (int offset = 0; offset < (1 << PDTBits) * 8; offset += 8) {
176 // read/write, user, present, 4MB
177 uint64_t pdte = X86ISA::htog(0x87 | base);
178 physPort->writeBlob(PageDirTable[table] + offset,
179 (uint8_t *)(&pdte), 8);
180 base += pageSize;
181 }
182 }
183
184 /*
185 * Transition from real mode all the way up to Long mode
186 */
187 CR0 cr0 = threadContexts[0]->readMiscRegNoEffect(MISCREG_CR0);
188 //Turn off paging.
189 cr0.pg = 0;
190 threadContexts[0]->setMiscReg(MISCREG_CR0, cr0);
191 //Turn on protected mode.
192 cr0.pe = 1;
193 threadContexts[0]->setMiscReg(MISCREG_CR0, cr0);
194
195 CR4 cr4 = threadContexts[0]->readMiscRegNoEffect(MISCREG_CR4);
196 //Turn on pae.
197 cr4.pae = 1;
198 threadContexts[0]->setMiscReg(MISCREG_CR4, cr4);
199
200 //Point to the page tables.
201 threadContexts[0]->setMiscReg(MISCREG_CR3, PageMapLevel4);
202
203 Efer efer = threadContexts[0]->readMiscRegNoEffect(MISCREG_EFER);
204 //Enable long mode.
205 efer.lme = 1;
206 threadContexts[0]->setMiscReg(MISCREG_EFER, efer);
207
208 //Activate long mode.
209 cr0.pg = 1;
210 threadContexts[0]->setMiscReg(MISCREG_CR0, cr0);
211
212 /*
213 * Far jump into 64 bit mode.
214 */
215 // Set the selector
216 threadContexts[0]->setMiscReg(MISCREG_CS, 1);
217 // Manually set up the segment attributes. In the future when there's
218 // other existing functionality to do this, that could be used
219 // instead.
220 SegAttr csAttr = 0;
221 csAttr.writable = 0;
222 csAttr.readable = 1;
223 csAttr.expandDown = 0;
224 csAttr.dpl = 0;
225 csAttr.defaultSize = 0;
226 csAttr.longMode = 1;
227 threadContexts[0]->setMiscReg(MISCREG_CS_ATTR, csAttr);
228
229 threadContexts[0]->setPC(threadContexts[0]->getSystemPtr()->kernelEntry);
230 threadContexts[0]->setNextPC(threadContexts[0]->readPC());
231
232 // We should now be in long mode. Yay!
233
|
| 234 Addr ebdaPos = 0xF0000;
235
236 Addr headerSize, structSize;
|
239 //Write out the SMBios/DMI table
| 237 //Write out the SMBios/DMI table
|
240 writeOutSMBiosTable(0xF0000);
| 238 writeOutSMBiosTable(ebdaPos, headerSize, structSize);
239 ebdaPos += (headerSize + structSize);
|
241}
242
243void
| 240}
241
242void
|
244X86System::writeOutSMBiosTable(Addr header, Addr table)
| 243X86System::writeOutSMBiosTable(Addr header,
244 Addr &headerSize, Addr &structSize, Addr table)
|
245{
246 // Get a port to write the table and header to memory.
247 FunctionalPort * physPort = threadContexts[0]->getPhysPort();
248
249 // If the table location isn't specified, just put it after the header.
250 // The header size as of the 2.5 SMBios specification is 0x1F bytes
| 245{
246 // Get a port to write the table and header to memory.
247 FunctionalPort * physPort = threadContexts[0]->getPhysPort();
248
249 // If the table location isn't specified, just put it after the header.
250 // The header size as of the 2.5 SMBios specification is 0x1F bytes
|
251 if (!table) {
252 if (!smbiosTable->smbiosHeader.intermediateHeader.tableAddr)
253 smbiosTable->smbiosHeader.
254 intermediateHeader.tableAddr = header + 0x1F;
255 } else {
256 smbiosTable->smbiosHeader.intermediateHeader.tableAddr = table;
257 }
| 251 if (!table)
252 table = header + 0x1F;
253 smbiosTable->setTableAddr(table);
|
258
| 254
|
259 smbiosTable->writeOut(physPort, header);
| 255 smbiosTable->writeOut(physPort, header, headerSize, structSize);
256
257 // Do some bounds checking to make sure we at least didn't step on
258 // ourselves.
259 assert(header > table || header + headerSize <= table);
260 assert(table > header || table + structSize <= header);
|
260}
261
262
263X86System::~X86System()
264{
265 delete smbiosTable;
266}
267
268void
269X86System::serialize(std::ostream &os)
270{
271 System::serialize(os);
272}
273
274
275void
276X86System::unserialize(Checkpoint *cp, const std::string §ion)
277{
278 System::unserialize(cp,section);
279}
280
281X86System *
282X86SystemParams::create()
283{
284 return new X86System(this);
285}
| 261}
262
263
264X86System::~X86System()
265{
266 delete smbiosTable;
267}
268
269void
270X86System::serialize(std::ostream &os)
271{
272 System::serialize(os);
273}
274
275
276void
277X86System::unserialize(Checkpoint *cp, const std::string §ion)
278{
279 System::unserialize(cp,section);
280}
281
282X86System *
283X86SystemParams::create()
284{
285 return new X86System(this);
286}
|