1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * Copyright (c) 2018 TU Dresden
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions are
17 * met: redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer;
19 * redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in the
21 * documentation and/or other materials provided with the distribution;
22 * neither the name of the copyright holders nor the names of its
23 * contributors may be used to endorse or promote products derived from
24 * this software without specific prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 *
38 * Authors: Gabe Black
39 * Maximilian Stein
40 */
41
42#include "arch/x86/system.hh"
43
44#include "arch/x86/bios/intelmp.hh"
45#include "arch/x86/bios/smbios.hh"
46#include "arch/x86/isa_traits.hh"
47#include "base/loader/object_file.hh"
48#include "cpu/thread_context.hh"
49#include "params/X86System.hh"
50
51using namespace LittleEndianGuest;
52using namespace X86ISA;
53
54X86System::X86System(Params *p) :
55 System(p), smbiosTable(p->smbios_table),
56 mpFloatingPointer(p->intel_mp_pointer),
57 mpConfigTable(p->intel_mp_table),
58 rsdp(p->acpi_description_table_pointer)
59{
60}
61
62void
63X86ISA::installSegDesc(ThreadContext *tc, SegmentRegIndex seg,
64 SegDescriptor desc, bool longmode)
65{
66 bool honorBase = !longmode || seg == SEGMENT_REG_FS ||
67 seg == SEGMENT_REG_GS ||
68 seg == SEGMENT_REG_TSL ||
69 seg == SYS_SEGMENT_REG_TR;
70
71 SegAttr attr = 0;
72
73 attr.dpl = desc.dpl;
74 attr.unusable = 0;
75 attr.defaultSize = desc.d;
76 attr.longMode = desc.l;
77 attr.avl = desc.avl;
78 attr.granularity = desc.g;
79 attr.present = desc.p;
80 attr.system = desc.s;
81 attr.type = desc.type;
82 if (desc.s) {
83 if (desc.type.codeOrData) {
84 // Code segment
85 attr.expandDown = 0;
86 attr.readable = desc.type.r;
87 attr.writable = 0;
88 } else {
89 // Data segment
90 attr.expandDown = desc.type.e;
91 attr.readable = 1;
92 attr.writable = desc.type.w;
93 }
94 } else {
95 attr.readable = 1;
96 attr.writable = 1;
97 attr.expandDown = 0;
98 }
99
100 tc->setMiscReg(MISCREG_SEG_BASE(seg), desc.base);
101 tc->setMiscReg(MISCREG_SEG_EFF_BASE(seg), honorBase ? desc.base : 0);
102 tc->setMiscReg(MISCREG_SEG_LIMIT(seg), desc.limit);
| 1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * Copyright (c) 2018 TU Dresden
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions are
17 * met: redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer;
19 * redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in the
21 * documentation and/or other materials provided with the distribution;
22 * neither the name of the copyright holders nor the names of its
23 * contributors may be used to endorse or promote products derived from
24 * this software without specific prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 *
38 * Authors: Gabe Black
39 * Maximilian Stein
40 */
41
42#include "arch/x86/system.hh"
43
44#include "arch/x86/bios/intelmp.hh"
45#include "arch/x86/bios/smbios.hh"
46#include "arch/x86/isa_traits.hh"
47#include "base/loader/object_file.hh"
48#include "cpu/thread_context.hh"
49#include "params/X86System.hh"
50
51using namespace LittleEndianGuest;
52using namespace X86ISA;
53
54X86System::X86System(Params *p) :
55 System(p), smbiosTable(p->smbios_table),
56 mpFloatingPointer(p->intel_mp_pointer),
57 mpConfigTable(p->intel_mp_table),
58 rsdp(p->acpi_description_table_pointer)
59{
60}
61
62void
63X86ISA::installSegDesc(ThreadContext *tc, SegmentRegIndex seg,
64 SegDescriptor desc, bool longmode)
65{
66 bool honorBase = !longmode || seg == SEGMENT_REG_FS ||
67 seg == SEGMENT_REG_GS ||
68 seg == SEGMENT_REG_TSL ||
69 seg == SYS_SEGMENT_REG_TR;
70
71 SegAttr attr = 0;
72
73 attr.dpl = desc.dpl;
74 attr.unusable = 0;
75 attr.defaultSize = desc.d;
76 attr.longMode = desc.l;
77 attr.avl = desc.avl;
78 attr.granularity = desc.g;
79 attr.present = desc.p;
80 attr.system = desc.s;
81 attr.type = desc.type;
82 if (desc.s) {
83 if (desc.type.codeOrData) {
84 // Code segment
85 attr.expandDown = 0;
86 attr.readable = desc.type.r;
87 attr.writable = 0;
88 } else {
89 // Data segment
90 attr.expandDown = desc.type.e;
91 attr.readable = 1;
92 attr.writable = desc.type.w;
93 }
94 } else {
95 attr.readable = 1;
96 attr.writable = 1;
97 attr.expandDown = 0;
98 }
99
100 tc->setMiscReg(MISCREG_SEG_BASE(seg), desc.base);
101 tc->setMiscReg(MISCREG_SEG_EFF_BASE(seg), honorBase ? desc.base : 0);
102 tc->setMiscReg(MISCREG_SEG_LIMIT(seg), desc.limit);
|
103 tc->setMiscReg(MISCREG_SEG_ATTR(seg), (MiscReg)attr);
| 103 tc->setMiscReg(MISCREG_SEG_ATTR(seg), (RegVal)attr);
|
104}
105
106void
107X86System::initState()
108{
109 System::initState();
110
111 if (!kernel)
112 fatal("No kernel to load.\n");
113
114 if (kernel->getArch() == ObjectFile::I386)
115 fatal("Loading a 32 bit x86 kernel is not supported.\n");
116
117 ThreadContext *tc = threadContexts[0];
118 // This is the boot strap processor (BSP). Initialize it to look like
119 // the boot loader has just turned control over to the 64 bit OS. We
120 // won't actually set up real mode or legacy protected mode descriptor
121 // tables because we aren't executing any code that would require
122 // them. We do, however toggle the control bits in the correct order
123 // while allowing consistency checks and the underlying mechansims
124 // just to be safe.
125
126 const int NumPDTs = 4;
127
128 const Addr PageMapLevel4 = 0x70000;
129 const Addr PageDirPtrTable = 0x71000;
130 const Addr PageDirTable[NumPDTs] =
131 {0x72000, 0x73000, 0x74000, 0x75000};
132 const Addr GDTBase = 0x76000;
133
134 const int PML4Bits = 9;
135 const int PDPTBits = 9;
136 const int PDTBits = 9;
137
138 /*
139 * Set up the gdt.
140 */
141 uint8_t numGDTEntries = 0;
142 // Place holder at selector 0
143 uint64_t nullDescriptor = 0;
144 physProxy.writeBlob(GDTBase + numGDTEntries * 8,
145 (uint8_t *)(&nullDescriptor), 8);
146 numGDTEntries++;
147
148 SegDescriptor initDesc = 0;
149 initDesc.type.codeOrData = 0; // code or data type
150 initDesc.type.c = 0; // conforming
151 initDesc.type.r = 1; // readable
152 initDesc.dpl = 0; // privilege
153 initDesc.p = 1; // present
154 initDesc.l = 1; // longmode - 64 bit
155 initDesc.d = 0; // operand size
156 initDesc.g = 1; // granularity
157 initDesc.s = 1; // system segment
158 initDesc.limit = 0xFFFFFFFF;
159 initDesc.base = 0;
160
161 // 64 bit code segment
162 SegDescriptor csDesc = initDesc;
163 csDesc.type.codeOrData = 1;
164 csDesc.dpl = 0;
165 // Because we're dealing with a pointer and I don't think it's
166 // guaranteed that there isn't anything in a nonvirtual class between
167 // it's beginning in memory and it's actual data, we'll use an
168 // intermediary.
169 uint64_t csDescVal = csDesc;
170 physProxy.writeBlob(GDTBase + numGDTEntries * 8,
171 (uint8_t *)(&csDescVal), 8);
172
173 numGDTEntries++;
174
175 SegSelector cs = 0;
176 cs.si = numGDTEntries - 1;
177
| 104}
105
106void
107X86System::initState()
108{
109 System::initState();
110
111 if (!kernel)
112 fatal("No kernel to load.\n");
113
114 if (kernel->getArch() == ObjectFile::I386)
115 fatal("Loading a 32 bit x86 kernel is not supported.\n");
116
117 ThreadContext *tc = threadContexts[0];
118 // This is the boot strap processor (BSP). Initialize it to look like
119 // the boot loader has just turned control over to the 64 bit OS. We
120 // won't actually set up real mode or legacy protected mode descriptor
121 // tables because we aren't executing any code that would require
122 // them. We do, however toggle the control bits in the correct order
123 // while allowing consistency checks and the underlying mechansims
124 // just to be safe.
125
126 const int NumPDTs = 4;
127
128 const Addr PageMapLevel4 = 0x70000;
129 const Addr PageDirPtrTable = 0x71000;
130 const Addr PageDirTable[NumPDTs] =
131 {0x72000, 0x73000, 0x74000, 0x75000};
132 const Addr GDTBase = 0x76000;
133
134 const int PML4Bits = 9;
135 const int PDPTBits = 9;
136 const int PDTBits = 9;
137
138 /*
139 * Set up the gdt.
140 */
141 uint8_t numGDTEntries = 0;
142 // Place holder at selector 0
143 uint64_t nullDescriptor = 0;
144 physProxy.writeBlob(GDTBase + numGDTEntries * 8,
145 (uint8_t *)(&nullDescriptor), 8);
146 numGDTEntries++;
147
148 SegDescriptor initDesc = 0;
149 initDesc.type.codeOrData = 0; // code or data type
150 initDesc.type.c = 0; // conforming
151 initDesc.type.r = 1; // readable
152 initDesc.dpl = 0; // privilege
153 initDesc.p = 1; // present
154 initDesc.l = 1; // longmode - 64 bit
155 initDesc.d = 0; // operand size
156 initDesc.g = 1; // granularity
157 initDesc.s = 1; // system segment
158 initDesc.limit = 0xFFFFFFFF;
159 initDesc.base = 0;
160
161 // 64 bit code segment
162 SegDescriptor csDesc = initDesc;
163 csDesc.type.codeOrData = 1;
164 csDesc.dpl = 0;
165 // Because we're dealing with a pointer and I don't think it's
166 // guaranteed that there isn't anything in a nonvirtual class between
167 // it's beginning in memory and it's actual data, we'll use an
168 // intermediary.
169 uint64_t csDescVal = csDesc;
170 physProxy.writeBlob(GDTBase + numGDTEntries * 8,
171 (uint8_t *)(&csDescVal), 8);
172
173 numGDTEntries++;
174
175 SegSelector cs = 0;
176 cs.si = numGDTEntries - 1;
177
|
178 tc->setMiscReg(MISCREG_CS, (MiscReg)cs);
| 178 tc->setMiscReg(MISCREG_CS, (RegVal)cs);
|
179
180 // 32 bit data segment
181 SegDescriptor dsDesc = initDesc;
182 uint64_t dsDescVal = dsDesc;
183 physProxy.writeBlob(GDTBase + numGDTEntries * 8,
184 (uint8_t *)(&dsDescVal), 8);
185
186 numGDTEntries++;
187
188 SegSelector ds = 0;
189 ds.si = numGDTEntries - 1;
190
| 179
180 // 32 bit data segment
181 SegDescriptor dsDesc = initDesc;
182 uint64_t dsDescVal = dsDesc;
183 physProxy.writeBlob(GDTBase + numGDTEntries * 8,
184 (uint8_t *)(&dsDescVal), 8);
185
186 numGDTEntries++;
187
188 SegSelector ds = 0;
189 ds.si = numGDTEntries - 1;
190
|
191 tc->setMiscReg(MISCREG_DS, (MiscReg)ds);
192 tc->setMiscReg(MISCREG_ES, (MiscReg)ds);
193 tc->setMiscReg(MISCREG_FS, (MiscReg)ds);
194 tc->setMiscReg(MISCREG_GS, (MiscReg)ds);
195 tc->setMiscReg(MISCREG_SS, (MiscReg)ds);
| 191 tc->setMiscReg(MISCREG_DS, (RegVal)ds);
192 tc->setMiscReg(MISCREG_ES, (RegVal)ds);
193 tc->setMiscReg(MISCREG_FS, (RegVal)ds);
194 tc->setMiscReg(MISCREG_GS, (RegVal)ds);
195 tc->setMiscReg(MISCREG_SS, (RegVal)ds);
|
196
197 tc->setMiscReg(MISCREG_TSL, 0);
198 tc->setMiscReg(MISCREG_TSG_BASE, GDTBase);
199 tc->setMiscReg(MISCREG_TSG_LIMIT, 8 * numGDTEntries - 1);
200
201 SegDescriptor tssDesc = initDesc;
202 uint64_t tssDescVal = tssDesc;
203 physProxy.writeBlob(GDTBase + numGDTEntries * 8,
204 (uint8_t *)(&tssDescVal), 8);
205
206 numGDTEntries++;
207
208 SegSelector tss = 0;
209 tss.si = numGDTEntries - 1;
210
| 196
197 tc->setMiscReg(MISCREG_TSL, 0);
198 tc->setMiscReg(MISCREG_TSG_BASE, GDTBase);
199 tc->setMiscReg(MISCREG_TSG_LIMIT, 8 * numGDTEntries - 1);
200
201 SegDescriptor tssDesc = initDesc;
202 uint64_t tssDescVal = tssDesc;
203 physProxy.writeBlob(GDTBase + numGDTEntries * 8,
204 (uint8_t *)(&tssDescVal), 8);
205
206 numGDTEntries++;
207
208 SegSelector tss = 0;
209 tss.si = numGDTEntries - 1;
210
|
211 tc->setMiscReg(MISCREG_TR, (MiscReg)tss);
| 211 tc->setMiscReg(MISCREG_TR, (RegVal)tss);
|
212 installSegDesc(tc, SYS_SEGMENT_REG_TR, tssDesc, true);
213
214 /*
215 * Identity map the first 4GB of memory. In order to map this region
216 * of memory in long mode, there needs to be one actual page map level
217 * 4 entry which points to one page directory pointer table which
218 * points to 4 different page directory tables which are full of two
219 * megabyte pages. All of the other entries in valid tables are set
220 * to indicate that they don't pertain to anything valid and will
221 * cause a fault if used.
222 */
223
224 // Put valid values in all of the various table entries which indicate
225 // that those entries don't point to further tables or pages. Then
226 // set the values of those entries which are needed.
227
228 // Page Map Level 4
229
230 // read/write, user, not present
231 uint64_t pml4e = X86ISA::htog(0x6);
232 for (int offset = 0; offset < (1 << PML4Bits) * 8; offset += 8) {
233 physProxy.writeBlob(PageMapLevel4 + offset, (uint8_t *)(&pml4e), 8);
234 }
235 // Point to the only PDPT
236 pml4e = X86ISA::htog(0x7 | PageDirPtrTable);
237 physProxy.writeBlob(PageMapLevel4, (uint8_t *)(&pml4e), 8);
238
239 // Page Directory Pointer Table
240
241 // read/write, user, not present
242 uint64_t pdpe = X86ISA::htog(0x6);
243 for (int offset = 0; offset < (1 << PDPTBits) * 8; offset += 8) {
244 physProxy.writeBlob(PageDirPtrTable + offset,
245 (uint8_t *)(&pdpe), 8);
246 }
247 // Point to the PDTs
248 for (int table = 0; table < NumPDTs; table++) {
249 pdpe = X86ISA::htog(0x7 | PageDirTable[table]);
250 physProxy.writeBlob(PageDirPtrTable + table * 8,
251 (uint8_t *)(&pdpe), 8);
252 }
253
254 // Page Directory Tables
255
256 Addr base = 0;
257 const Addr pageSize = 2 << 20;
258 for (int table = 0; table < NumPDTs; table++) {
259 for (int offset = 0; offset < (1 << PDTBits) * 8; offset += 8) {
260 // read/write, user, present, 4MB
261 uint64_t pdte = X86ISA::htog(0x87 | base);
262 physProxy.writeBlob(PageDirTable[table] + offset,
263 (uint8_t *)(&pdte), 8);
264 base += pageSize;
265 }
266 }
267
268 /*
269 * Transition from real mode all the way up to Long mode
270 */
271 CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0);
272 // Turn off paging.
273 cr0.pg = 0;
274 tc->setMiscReg(MISCREG_CR0, cr0);
275 // Turn on protected mode.
276 cr0.pe = 1;
277 tc->setMiscReg(MISCREG_CR0, cr0);
278
279 CR4 cr4 = tc->readMiscRegNoEffect(MISCREG_CR4);
280 // Turn on pae.
281 cr4.pae = 1;
282 tc->setMiscReg(MISCREG_CR4, cr4);
283
284 // Point to the page tables.
285 tc->setMiscReg(MISCREG_CR3, PageMapLevel4);
286
287 Efer efer = tc->readMiscRegNoEffect(MISCREG_EFER);
288 // Enable long mode.
289 efer.lme = 1;
290 tc->setMiscReg(MISCREG_EFER, efer);
291
292 // Start using longmode segments.
293 installSegDesc(tc, SEGMENT_REG_CS, csDesc, true);
294 installSegDesc(tc, SEGMENT_REG_DS, dsDesc, true);
295 installSegDesc(tc, SEGMENT_REG_ES, dsDesc, true);
296 installSegDesc(tc, SEGMENT_REG_FS, dsDesc, true);
297 installSegDesc(tc, SEGMENT_REG_GS, dsDesc, true);
298 installSegDesc(tc, SEGMENT_REG_SS, dsDesc, true);
299
300 // Activate long mode.
301 cr0.pg = 1;
302 tc->setMiscReg(MISCREG_CR0, cr0);
303
304 tc->pcState(tc->getSystemPtr()->kernelEntry);
305
306 // We should now be in long mode. Yay!
307
308 Addr ebdaPos = 0xF0000;
309 Addr fixed, table;
310
311 // Write out the SMBios/DMI table.
312 writeOutSMBiosTable(ebdaPos, fixed, table);
313 ebdaPos += (fixed + table);
314 ebdaPos = roundUp(ebdaPos, 16);
315
316 // Write out the Intel MP Specification configuration table.
317 writeOutMPTable(ebdaPos, fixed, table);
318 ebdaPos += (fixed + table);
319}
320
321void
322X86System::writeOutSMBiosTable(Addr header,
323 Addr &headerSize, Addr &structSize, Addr table)
324{
325 // If the table location isn't specified, just put it after the header.
326 // The header size as of the 2.5 SMBios specification is 0x1F bytes.
327 if (!table)
328 table = header + 0x1F;
329 smbiosTable->setTableAddr(table);
330
331 smbiosTable->writeOut(physProxy, header, headerSize, structSize);
332
333 // Do some bounds checking to make sure we at least didn't step on
334 // ourselves.
335 assert(header > table || header + headerSize <= table);
336 assert(table > header || table + structSize <= header);
337}
338
339void
340X86System::writeOutMPTable(Addr fp,
341 Addr &fpSize, Addr &tableSize, Addr table)
342{
343 // If the table location isn't specified and it exists, just put
344 // it after the floating pointer. The fp size as of the 1.4 Intel MP
345 // specification is 0x10 bytes.
346 if (mpConfigTable) {
347 if (!table)
348 table = fp + 0x10;
349 mpFloatingPointer->setTableAddr(table);
350 }
351
352 fpSize = mpFloatingPointer->writeOut(physProxy, fp);
353 if (mpConfigTable)
354 tableSize = mpConfigTable->writeOut(physProxy, table);
355 else
356 tableSize = 0;
357
358 // Do some bounds checking to make sure we at least didn't step on
359 // ourselves and the fp structure was the size we thought it was.
360 assert(fp > table || fp + fpSize <= table);
361 assert(table > fp || table + tableSize <= fp);
362 assert(fpSize == 0x10);
363}
364
365
366X86System::~X86System()
367{
368 delete smbiosTable;
369}
370
371X86System *
372X86SystemParams::create()
373{
374 return new X86System(this);
375}
| 212 installSegDesc(tc, SYS_SEGMENT_REG_TR, tssDesc, true);
213
214 /*
215 * Identity map the first 4GB of memory. In order to map this region
216 * of memory in long mode, there needs to be one actual page map level
217 * 4 entry which points to one page directory pointer table which
218 * points to 4 different page directory tables which are full of two
219 * megabyte pages. All of the other entries in valid tables are set
220 * to indicate that they don't pertain to anything valid and will
221 * cause a fault if used.
222 */
223
224 // Put valid values in all of the various table entries which indicate
225 // that those entries don't point to further tables or pages. Then
226 // set the values of those entries which are needed.
227
228 // Page Map Level 4
229
230 // read/write, user, not present
231 uint64_t pml4e = X86ISA::htog(0x6);
232 for (int offset = 0; offset < (1 << PML4Bits) * 8; offset += 8) {
233 physProxy.writeBlob(PageMapLevel4 + offset, (uint8_t *)(&pml4e), 8);
234 }
235 // Point to the only PDPT
236 pml4e = X86ISA::htog(0x7 | PageDirPtrTable);
237 physProxy.writeBlob(PageMapLevel4, (uint8_t *)(&pml4e), 8);
238
239 // Page Directory Pointer Table
240
241 // read/write, user, not present
242 uint64_t pdpe = X86ISA::htog(0x6);
243 for (int offset = 0; offset < (1 << PDPTBits) * 8; offset += 8) {
244 physProxy.writeBlob(PageDirPtrTable + offset,
245 (uint8_t *)(&pdpe), 8);
246 }
247 // Point to the PDTs
248 for (int table = 0; table < NumPDTs; table++) {
249 pdpe = X86ISA::htog(0x7 | PageDirTable[table]);
250 physProxy.writeBlob(PageDirPtrTable + table * 8,
251 (uint8_t *)(&pdpe), 8);
252 }
253
254 // Page Directory Tables
255
256 Addr base = 0;
257 const Addr pageSize = 2 << 20;
258 for (int table = 0; table < NumPDTs; table++) {
259 for (int offset = 0; offset < (1 << PDTBits) * 8; offset += 8) {
260 // read/write, user, present, 4MB
261 uint64_t pdte = X86ISA::htog(0x87 | base);
262 physProxy.writeBlob(PageDirTable[table] + offset,
263 (uint8_t *)(&pdte), 8);
264 base += pageSize;
265 }
266 }
267
268 /*
269 * Transition from real mode all the way up to Long mode
270 */
271 CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0);
272 // Turn off paging.
273 cr0.pg = 0;
274 tc->setMiscReg(MISCREG_CR0, cr0);
275 // Turn on protected mode.
276 cr0.pe = 1;
277 tc->setMiscReg(MISCREG_CR0, cr0);
278
279 CR4 cr4 = tc->readMiscRegNoEffect(MISCREG_CR4);
280 // Turn on pae.
281 cr4.pae = 1;
282 tc->setMiscReg(MISCREG_CR4, cr4);
283
284 // Point to the page tables.
285 tc->setMiscReg(MISCREG_CR3, PageMapLevel4);
286
287 Efer efer = tc->readMiscRegNoEffect(MISCREG_EFER);
288 // Enable long mode.
289 efer.lme = 1;
290 tc->setMiscReg(MISCREG_EFER, efer);
291
292 // Start using longmode segments.
293 installSegDesc(tc, SEGMENT_REG_CS, csDesc, true);
294 installSegDesc(tc, SEGMENT_REG_DS, dsDesc, true);
295 installSegDesc(tc, SEGMENT_REG_ES, dsDesc, true);
296 installSegDesc(tc, SEGMENT_REG_FS, dsDesc, true);
297 installSegDesc(tc, SEGMENT_REG_GS, dsDesc, true);
298 installSegDesc(tc, SEGMENT_REG_SS, dsDesc, true);
299
300 // Activate long mode.
301 cr0.pg = 1;
302 tc->setMiscReg(MISCREG_CR0, cr0);
303
304 tc->pcState(tc->getSystemPtr()->kernelEntry);
305
306 // We should now be in long mode. Yay!
307
308 Addr ebdaPos = 0xF0000;
309 Addr fixed, table;
310
311 // Write out the SMBios/DMI table.
312 writeOutSMBiosTable(ebdaPos, fixed, table);
313 ebdaPos += (fixed + table);
314 ebdaPos = roundUp(ebdaPos, 16);
315
316 // Write out the Intel MP Specification configuration table.
317 writeOutMPTable(ebdaPos, fixed, table);
318 ebdaPos += (fixed + table);
319}
320
321void
322X86System::writeOutSMBiosTable(Addr header,
323 Addr &headerSize, Addr &structSize, Addr table)
324{
325 // If the table location isn't specified, just put it after the header.
326 // The header size as of the 2.5 SMBios specification is 0x1F bytes.
327 if (!table)
328 table = header + 0x1F;
329 smbiosTable->setTableAddr(table);
330
331 smbiosTable->writeOut(physProxy, header, headerSize, structSize);
332
333 // Do some bounds checking to make sure we at least didn't step on
334 // ourselves.
335 assert(header > table || header + headerSize <= table);
336 assert(table > header || table + structSize <= header);
337}
338
339void
340X86System::writeOutMPTable(Addr fp,
341 Addr &fpSize, Addr &tableSize, Addr table)
342{
343 // If the table location isn't specified and it exists, just put
344 // it after the floating pointer. The fp size as of the 1.4 Intel MP
345 // specification is 0x10 bytes.
346 if (mpConfigTable) {
347 if (!table)
348 table = fp + 0x10;
349 mpFloatingPointer->setTableAddr(table);
350 }
351
352 fpSize = mpFloatingPointer->writeOut(physProxy, fp);
353 if (mpConfigTable)
354 tableSize = mpConfigTable->writeOut(physProxy, table);
355 else
356 tableSize = 0;
357
358 // Do some bounds checking to make sure we at least didn't step on
359 // ourselves and the fp structure was the size we thought it was.
360 assert(fp > table || fp + fpSize <= table);
361 assert(table > fp || table + tableSize <= fp);
362 assert(fpSize == 0x10);
363}
364
365
366X86System::~X86System()
367{
368 delete smbiosTable;
369}
370
371X86System *
372X86SystemParams::create()
373{
374 return new X86System(this);
375}
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