1/* 2 * Copyright (c) 2007 The Hewlett-Packard Development Company 3 * Copyright (c) 2018 TU Dresden 4 * All rights reserved. 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated 12 * unmodified and in its entirety in all distributions of the software, 13 * modified or unmodified, in source code or in binary form. 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions are 17 * met: redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer; 19 * redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution; 22 * neither the name of the copyright holders nor the names of its 23 * contributors may be used to endorse or promote products derived from 24 * this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 27 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 28 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 29 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 30 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 31 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 32 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 33 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 34 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 35 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 36 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37 * 38 * Authors: Gabe Black 39 * Maximilian Stein 40 */ 41 42#include "arch/x86/system.hh" 43 44#include "arch/x86/bios/intelmp.hh" 45#include "arch/x86/bios/smbios.hh" 46#include "arch/x86/isa_traits.hh" 47#include "base/loader/object_file.hh" 48#include "cpu/thread_context.hh" 49#include "params/X86System.hh" 50 51using namespace LittleEndianGuest; 52using namespace X86ISA; 53 54X86System::X86System(Params *p) : 55 System(p), smbiosTable(p->smbios_table), 56 mpFloatingPointer(p->intel_mp_pointer), 57 mpConfigTable(p->intel_mp_table), 58 rsdp(p->acpi_description_table_pointer) 59{ 60} 61 62void 63X86ISA::installSegDesc(ThreadContext *tc, SegmentRegIndex seg, 64 SegDescriptor desc, bool longmode) 65{
| 1/* 2 * Copyright (c) 2007 The Hewlett-Packard Development Company 3 * Copyright (c) 2018 TU Dresden 4 * All rights reserved. 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated 12 * unmodified and in its entirety in all distributions of the software, 13 * modified or unmodified, in source code or in binary form. 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions are 17 * met: redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer; 19 * redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution; 22 * neither the name of the copyright holders nor the names of its 23 * contributors may be used to endorse or promote products derived from 24 * this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 27 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 28 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 29 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 30 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 31 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 32 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 33 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 34 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 35 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 36 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37 * 38 * Authors: Gabe Black 39 * Maximilian Stein 40 */ 41 42#include "arch/x86/system.hh" 43 44#include "arch/x86/bios/intelmp.hh" 45#include "arch/x86/bios/smbios.hh" 46#include "arch/x86/isa_traits.hh" 47#include "base/loader/object_file.hh" 48#include "cpu/thread_context.hh" 49#include "params/X86System.hh" 50 51using namespace LittleEndianGuest; 52using namespace X86ISA; 53 54X86System::X86System(Params *p) : 55 System(p), smbiosTable(p->smbios_table), 56 mpFloatingPointer(p->intel_mp_pointer), 57 mpConfigTable(p->intel_mp_table), 58 rsdp(p->acpi_description_table_pointer) 59{ 60} 61 62void 63X86ISA::installSegDesc(ThreadContext *tc, SegmentRegIndex seg, 64 SegDescriptor desc, bool longmode) 65{
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166 167 // 64 bit code segment 168 SegDescriptor csDesc = initDesc; 169 csDesc.type.codeOrData = 1; 170 csDesc.dpl = 0; 171 // Because we're dealing with a pointer and I don't think it's 172 // guaranteed that there isn't anything in a nonvirtual class between 173 // it's beginning in memory and it's actual data, we'll use an 174 // intermediary. 175 uint64_t csDescVal = csDesc; 176 physProxy.writeBlob(GDTBase + numGDTEntries * 8, 177 (uint8_t *)(&csDescVal), 8); 178 179 numGDTEntries++; 180 181 SegSelector cs = 0; 182 cs.si = numGDTEntries - 1; 183 184 tc->setMiscReg(MISCREG_CS, (MiscReg)cs); 185 186 // 32 bit data segment 187 SegDescriptor dsDesc = initDesc; 188 uint64_t dsDescVal = dsDesc; 189 physProxy.writeBlob(GDTBase + numGDTEntries * 8, 190 (uint8_t *)(&dsDescVal), 8); 191 192 numGDTEntries++; 193 194 SegSelector ds = 0; 195 ds.si = numGDTEntries - 1; 196 197 tc->setMiscReg(MISCREG_DS, (MiscReg)ds); 198 tc->setMiscReg(MISCREG_ES, (MiscReg)ds); 199 tc->setMiscReg(MISCREG_FS, (MiscReg)ds); 200 tc->setMiscReg(MISCREG_GS, (MiscReg)ds); 201 tc->setMiscReg(MISCREG_SS, (MiscReg)ds); 202 203 tc->setMiscReg(MISCREG_TSL, 0); 204 tc->setMiscReg(MISCREG_TSG_BASE, GDTBase); 205 tc->setMiscReg(MISCREG_TSG_LIMIT, 8 * numGDTEntries - 1); 206 207 SegDescriptor tssDesc = initDesc; 208 uint64_t tssDescVal = tssDesc; 209 physProxy.writeBlob(GDTBase + numGDTEntries * 8, 210 (uint8_t *)(&tssDescVal), 8); 211 212 numGDTEntries++; 213 214 SegSelector tss = 0; 215 tss.si = numGDTEntries - 1; 216 217 tc->setMiscReg(MISCREG_TR, (MiscReg)tss); 218 installSegDesc(tc, SYS_SEGMENT_REG_TR, tssDesc, true); 219 220 /* 221 * Identity map the first 4GB of memory. In order to map this region 222 * of memory in long mode, there needs to be one actual page map level 223 * 4 entry which points to one page directory pointer table which 224 * points to 4 different page directory tables which are full of two 225 * megabyte pages. All of the other entries in valid tables are set 226 * to indicate that they don't pertain to anything valid and will 227 * cause a fault if used. 228 */ 229 230 // Put valid values in all of the various table entries which indicate 231 // that those entries don't point to further tables or pages. Then 232 // set the values of those entries which are needed. 233 234 // Page Map Level 4 235 236 // read/write, user, not present 237 uint64_t pml4e = X86ISA::htog(0x6); 238 for (int offset = 0; offset < (1 << PML4Bits) * 8; offset += 8) { 239 physProxy.writeBlob(PageMapLevel4 + offset, (uint8_t *)(&pml4e), 8); 240 } 241 // Point to the only PDPT 242 pml4e = X86ISA::htog(0x7 | PageDirPtrTable); 243 physProxy.writeBlob(PageMapLevel4, (uint8_t *)(&pml4e), 8); 244 245 // Page Directory Pointer Table 246 247 // read/write, user, not present 248 uint64_t pdpe = X86ISA::htog(0x6); 249 for (int offset = 0; offset < (1 << PDPTBits) * 8; offset += 8) { 250 physProxy.writeBlob(PageDirPtrTable + offset, 251 (uint8_t *)(&pdpe), 8); 252 } 253 // Point to the PDTs 254 for (int table = 0; table < NumPDTs; table++) { 255 pdpe = X86ISA::htog(0x7 | PageDirTable[table]); 256 physProxy.writeBlob(PageDirPtrTable + table * 8, 257 (uint8_t *)(&pdpe), 8); 258 } 259 260 // Page Directory Tables 261 262 Addr base = 0; 263 const Addr pageSize = 2 << 20; 264 for (int table = 0; table < NumPDTs; table++) { 265 for (int offset = 0; offset < (1 << PDTBits) * 8; offset += 8) { 266 // read/write, user, present, 4MB 267 uint64_t pdte = X86ISA::htog(0x87 | base); 268 physProxy.writeBlob(PageDirTable[table] + offset, 269 (uint8_t *)(&pdte), 8); 270 base += pageSize; 271 } 272 } 273 274 /* 275 * Transition from real mode all the way up to Long mode 276 */ 277 CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0); 278 // Turn off paging. 279 cr0.pg = 0; 280 tc->setMiscReg(MISCREG_CR0, cr0); 281 // Turn on protected mode. 282 cr0.pe = 1; 283 tc->setMiscReg(MISCREG_CR0, cr0); 284 285 CR4 cr4 = tc->readMiscRegNoEffect(MISCREG_CR4); 286 // Turn on pae. 287 cr4.pae = 1; 288 tc->setMiscReg(MISCREG_CR4, cr4); 289 290 // Point to the page tables. 291 tc->setMiscReg(MISCREG_CR3, PageMapLevel4); 292 293 Efer efer = tc->readMiscRegNoEffect(MISCREG_EFER); 294 // Enable long mode. 295 efer.lme = 1; 296 tc->setMiscReg(MISCREG_EFER, efer); 297 298 // Start using longmode segments. 299 installSegDesc(tc, SEGMENT_REG_CS, csDesc, true); 300 installSegDesc(tc, SEGMENT_REG_DS, dsDesc, true); 301 installSegDesc(tc, SEGMENT_REG_ES, dsDesc, true); 302 installSegDesc(tc, SEGMENT_REG_FS, dsDesc, true); 303 installSegDesc(tc, SEGMENT_REG_GS, dsDesc, true); 304 installSegDesc(tc, SEGMENT_REG_SS, dsDesc, true); 305 306 // Activate long mode. 307 cr0.pg = 1; 308 tc->setMiscReg(MISCREG_CR0, cr0); 309 310 tc->pcState(tc->getSystemPtr()->kernelEntry); 311 312 // We should now be in long mode. Yay! 313 314 Addr ebdaPos = 0xF0000; 315 Addr fixed, table; 316 317 // Write out the SMBios/DMI table. 318 writeOutSMBiosTable(ebdaPos, fixed, table); 319 ebdaPos += (fixed + table); 320 ebdaPos = roundUp(ebdaPos, 16); 321 322 // Write out the Intel MP Specification configuration table. 323 writeOutMPTable(ebdaPos, fixed, table); 324 ebdaPos += (fixed + table); 325} 326 327void 328X86System::writeOutSMBiosTable(Addr header, 329 Addr &headerSize, Addr &structSize, Addr table) 330{ 331 // If the table location isn't specified, just put it after the header. 332 // The header size as of the 2.5 SMBios specification is 0x1F bytes. 333 if (!table) 334 table = header + 0x1F; 335 smbiosTable->setTableAddr(table); 336 337 smbiosTable->writeOut(physProxy, header, headerSize, structSize); 338 339 // Do some bounds checking to make sure we at least didn't step on 340 // ourselves. 341 assert(header > table || header + headerSize <= table); 342 assert(table > header || table + structSize <= header); 343} 344 345void 346X86System::writeOutMPTable(Addr fp, 347 Addr &fpSize, Addr &tableSize, Addr table) 348{ 349 // If the table location isn't specified and it exists, just put 350 // it after the floating pointer. The fp size as of the 1.4 Intel MP 351 // specification is 0x10 bytes. 352 if (mpConfigTable) { 353 if (!table) 354 table = fp + 0x10; 355 mpFloatingPointer->setTableAddr(table); 356 } 357 358 fpSize = mpFloatingPointer->writeOut(physProxy, fp); 359 if (mpConfigTable) 360 tableSize = mpConfigTable->writeOut(physProxy, table); 361 else 362 tableSize = 0; 363 364 // Do some bounds checking to make sure we at least didn't step on 365 // ourselves and the fp structure was the size we thought it was. 366 assert(fp > table || fp + fpSize <= table); 367 assert(table > fp || table + tableSize <= fp); 368 assert(fpSize == 0x10); 369} 370 371 372X86System::~X86System() 373{ 374 delete smbiosTable; 375} 376 377X86System * 378X86SystemParams::create() 379{ 380 return new X86System(this); 381}
| 160 161 // 64 bit code segment 162 SegDescriptor csDesc = initDesc; 163 csDesc.type.codeOrData = 1; 164 csDesc.dpl = 0; 165 // Because we're dealing with a pointer and I don't think it's 166 // guaranteed that there isn't anything in a nonvirtual class between 167 // it's beginning in memory and it's actual data, we'll use an 168 // intermediary. 169 uint64_t csDescVal = csDesc; 170 physProxy.writeBlob(GDTBase + numGDTEntries * 8, 171 (uint8_t *)(&csDescVal), 8); 172 173 numGDTEntries++; 174 175 SegSelector cs = 0; 176 cs.si = numGDTEntries - 1; 177 178 tc->setMiscReg(MISCREG_CS, (MiscReg)cs); 179 180 // 32 bit data segment 181 SegDescriptor dsDesc = initDesc; 182 uint64_t dsDescVal = dsDesc; 183 physProxy.writeBlob(GDTBase + numGDTEntries * 8, 184 (uint8_t *)(&dsDescVal), 8); 185 186 numGDTEntries++; 187 188 SegSelector ds = 0; 189 ds.si = numGDTEntries - 1; 190 191 tc->setMiscReg(MISCREG_DS, (MiscReg)ds); 192 tc->setMiscReg(MISCREG_ES, (MiscReg)ds); 193 tc->setMiscReg(MISCREG_FS, (MiscReg)ds); 194 tc->setMiscReg(MISCREG_GS, (MiscReg)ds); 195 tc->setMiscReg(MISCREG_SS, (MiscReg)ds); 196 197 tc->setMiscReg(MISCREG_TSL, 0); 198 tc->setMiscReg(MISCREG_TSG_BASE, GDTBase); 199 tc->setMiscReg(MISCREG_TSG_LIMIT, 8 * numGDTEntries - 1); 200 201 SegDescriptor tssDesc = initDesc; 202 uint64_t tssDescVal = tssDesc; 203 physProxy.writeBlob(GDTBase + numGDTEntries * 8, 204 (uint8_t *)(&tssDescVal), 8); 205 206 numGDTEntries++; 207 208 SegSelector tss = 0; 209 tss.si = numGDTEntries - 1; 210 211 tc->setMiscReg(MISCREG_TR, (MiscReg)tss); 212 installSegDesc(tc, SYS_SEGMENT_REG_TR, tssDesc, true); 213 214 /* 215 * Identity map the first 4GB of memory. In order to map this region 216 * of memory in long mode, there needs to be one actual page map level 217 * 4 entry which points to one page directory pointer table which 218 * points to 4 different page directory tables which are full of two 219 * megabyte pages. All of the other entries in valid tables are set 220 * to indicate that they don't pertain to anything valid and will 221 * cause a fault if used. 222 */ 223 224 // Put valid values in all of the various table entries which indicate 225 // that those entries don't point to further tables or pages. Then 226 // set the values of those entries which are needed. 227 228 // Page Map Level 4 229 230 // read/write, user, not present 231 uint64_t pml4e = X86ISA::htog(0x6); 232 for (int offset = 0; offset < (1 << PML4Bits) * 8; offset += 8) { 233 physProxy.writeBlob(PageMapLevel4 + offset, (uint8_t *)(&pml4e), 8); 234 } 235 // Point to the only PDPT 236 pml4e = X86ISA::htog(0x7 | PageDirPtrTable); 237 physProxy.writeBlob(PageMapLevel4, (uint8_t *)(&pml4e), 8); 238 239 // Page Directory Pointer Table 240 241 // read/write, user, not present 242 uint64_t pdpe = X86ISA::htog(0x6); 243 for (int offset = 0; offset < (1 << PDPTBits) * 8; offset += 8) { 244 physProxy.writeBlob(PageDirPtrTable + offset, 245 (uint8_t *)(&pdpe), 8); 246 } 247 // Point to the PDTs 248 for (int table = 0; table < NumPDTs; table++) { 249 pdpe = X86ISA::htog(0x7 | PageDirTable[table]); 250 physProxy.writeBlob(PageDirPtrTable + table * 8, 251 (uint8_t *)(&pdpe), 8); 252 } 253 254 // Page Directory Tables 255 256 Addr base = 0; 257 const Addr pageSize = 2 << 20; 258 for (int table = 0; table < NumPDTs; table++) { 259 for (int offset = 0; offset < (1 << PDTBits) * 8; offset += 8) { 260 // read/write, user, present, 4MB 261 uint64_t pdte = X86ISA::htog(0x87 | base); 262 physProxy.writeBlob(PageDirTable[table] + offset, 263 (uint8_t *)(&pdte), 8); 264 base += pageSize; 265 } 266 } 267 268 /* 269 * Transition from real mode all the way up to Long mode 270 */ 271 CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0); 272 // Turn off paging. 273 cr0.pg = 0; 274 tc->setMiscReg(MISCREG_CR0, cr0); 275 // Turn on protected mode. 276 cr0.pe = 1; 277 tc->setMiscReg(MISCREG_CR0, cr0); 278 279 CR4 cr4 = tc->readMiscRegNoEffect(MISCREG_CR4); 280 // Turn on pae. 281 cr4.pae = 1; 282 tc->setMiscReg(MISCREG_CR4, cr4); 283 284 // Point to the page tables. 285 tc->setMiscReg(MISCREG_CR3, PageMapLevel4); 286 287 Efer efer = tc->readMiscRegNoEffect(MISCREG_EFER); 288 // Enable long mode. 289 efer.lme = 1; 290 tc->setMiscReg(MISCREG_EFER, efer); 291 292 // Start using longmode segments. 293 installSegDesc(tc, SEGMENT_REG_CS, csDesc, true); 294 installSegDesc(tc, SEGMENT_REG_DS, dsDesc, true); 295 installSegDesc(tc, SEGMENT_REG_ES, dsDesc, true); 296 installSegDesc(tc, SEGMENT_REG_FS, dsDesc, true); 297 installSegDesc(tc, SEGMENT_REG_GS, dsDesc, true); 298 installSegDesc(tc, SEGMENT_REG_SS, dsDesc, true); 299 300 // Activate long mode. 301 cr0.pg = 1; 302 tc->setMiscReg(MISCREG_CR0, cr0); 303 304 tc->pcState(tc->getSystemPtr()->kernelEntry); 305 306 // We should now be in long mode. Yay! 307 308 Addr ebdaPos = 0xF0000; 309 Addr fixed, table; 310 311 // Write out the SMBios/DMI table. 312 writeOutSMBiosTable(ebdaPos, fixed, table); 313 ebdaPos += (fixed + table); 314 ebdaPos = roundUp(ebdaPos, 16); 315 316 // Write out the Intel MP Specification configuration table. 317 writeOutMPTable(ebdaPos, fixed, table); 318 ebdaPos += (fixed + table); 319} 320 321void 322X86System::writeOutSMBiosTable(Addr header, 323 Addr &headerSize, Addr &structSize, Addr table) 324{ 325 // If the table location isn't specified, just put it after the header. 326 // The header size as of the 2.5 SMBios specification is 0x1F bytes. 327 if (!table) 328 table = header + 0x1F; 329 smbiosTable->setTableAddr(table); 330 331 smbiosTable->writeOut(physProxy, header, headerSize, structSize); 332 333 // Do some bounds checking to make sure we at least didn't step on 334 // ourselves. 335 assert(header > table || header + headerSize <= table); 336 assert(table > header || table + structSize <= header); 337} 338 339void 340X86System::writeOutMPTable(Addr fp, 341 Addr &fpSize, Addr &tableSize, Addr table) 342{ 343 // If the table location isn't specified and it exists, just put 344 // it after the floating pointer. The fp size as of the 1.4 Intel MP 345 // specification is 0x10 bytes. 346 if (mpConfigTable) { 347 if (!table) 348 table = fp + 0x10; 349 mpFloatingPointer->setTableAddr(table); 350 } 351 352 fpSize = mpFloatingPointer->writeOut(physProxy, fp); 353 if (mpConfigTable) 354 tableSize = mpConfigTable->writeOut(physProxy, table); 355 else 356 tableSize = 0; 357 358 // Do some bounds checking to make sure we at least didn't step on 359 // ourselves and the fp structure was the size we thought it was. 360 assert(fp > table || fp + fpSize <= table); 361 assert(table > fp || table + tableSize <= fp); 362 assert(fpSize == 0x10); 363} 364 365 366X86System::~X86System() 367{ 368 delete smbiosTable; 369} 370 371X86System * 372X86SystemParams::create() 373{ 374 return new X86System(this); 375}
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