msr.cc (8582:dd79a696b91c) msr.cc (9875:5cfad3486991)
1/*
2 * Copyright (c) 2011 Google
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#include "arch/x86/regs/msr.hh"
1/*
2 * Copyright (c) 2011 Google
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#include "arch/x86/regs/msr.hh"
32#include "base/hashmap.hh"
33
34namespace X86ISA
35{
36
32
33namespace X86ISA
34{
35
37typedef m5::hash_map<Addr, MiscRegIndex> MsrMap;
38
39typedef MsrMap::value_type MsrVal;
40
41const MsrMap::value_type msrMapData[] = {
42 MsrVal(0x10, MISCREG_TSC),
43 MsrVal(0x1B, MISCREG_APIC_BASE),
44 MsrVal(0xFE, MISCREG_MTRRCAP),
45 MsrVal(0x174, MISCREG_SYSENTER_CS),
46 MsrVal(0x175, MISCREG_SYSENTER_ESP),
47 MsrVal(0x176, MISCREG_SYSENTER_EIP),
48 MsrVal(0x179, MISCREG_MCG_CAP),
49 MsrVal(0x17A, MISCREG_MCG_STATUS),
50 MsrVal(0x17B, MISCREG_MCG_CTL),
51 MsrVal(0x1D9, MISCREG_DEBUG_CTL_MSR),
52 MsrVal(0x1DB, MISCREG_LAST_BRANCH_FROM_IP),
53 MsrVal(0x1DC, MISCREG_LAST_BRANCH_TO_IP),
54 MsrVal(0x1DD, MISCREG_LAST_EXCEPTION_FROM_IP),
55 MsrVal(0x1DE, MISCREG_LAST_EXCEPTION_TO_IP),
56 MsrVal(0x200, MISCREG_MTRR_PHYS_BASE_0),
57 MsrVal(0x201, MISCREG_MTRR_PHYS_MASK_0),
58 MsrVal(0x202, MISCREG_MTRR_PHYS_BASE_1),
59 MsrVal(0x203, MISCREG_MTRR_PHYS_MASK_1),
60 MsrVal(0x204, MISCREG_MTRR_PHYS_BASE_2),
61 MsrVal(0x205, MISCREG_MTRR_PHYS_MASK_2),
62 MsrVal(0x206, MISCREG_MTRR_PHYS_BASE_3),
63 MsrVal(0x207, MISCREG_MTRR_PHYS_MASK_3),
64 MsrVal(0x208, MISCREG_MTRR_PHYS_BASE_4),
65 MsrVal(0x209, MISCREG_MTRR_PHYS_MASK_4),
66 MsrVal(0x20A, MISCREG_MTRR_PHYS_BASE_5),
67 MsrVal(0x20B, MISCREG_MTRR_PHYS_MASK_5),
68 MsrVal(0x20C, MISCREG_MTRR_PHYS_BASE_6),
69 MsrVal(0x20D, MISCREG_MTRR_PHYS_MASK_6),
70 MsrVal(0x20E, MISCREG_MTRR_PHYS_BASE_7),
71 MsrVal(0x20F, MISCREG_MTRR_PHYS_MASK_7),
72 MsrVal(0x250, MISCREG_MTRR_FIX_64K_00000),
73 MsrVal(0x258, MISCREG_MTRR_FIX_16K_80000),
74 MsrVal(0x259, MISCREG_MTRR_FIX_16K_A0000),
75 MsrVal(0x268, MISCREG_MTRR_FIX_4K_C0000),
76 MsrVal(0x269, MISCREG_MTRR_FIX_4K_C8000),
77 MsrVal(0x26A, MISCREG_MTRR_FIX_4K_D0000),
78 MsrVal(0x26B, MISCREG_MTRR_FIX_4K_D8000),
79 MsrVal(0x26C, MISCREG_MTRR_FIX_4K_E0000),
80 MsrVal(0x26D, MISCREG_MTRR_FIX_4K_E8000),
81 MsrVal(0x26E, MISCREG_MTRR_FIX_4K_F0000),
82 MsrVal(0x26F, MISCREG_MTRR_FIX_4K_F8000),
83 MsrVal(0x277, MISCREG_PAT),
84 MsrVal(0x2FF, MISCREG_DEF_TYPE),
85 MsrVal(0x400, MISCREG_MC0_CTL),
86 MsrVal(0x404, MISCREG_MC1_CTL),
87 MsrVal(0x408, MISCREG_MC2_CTL),
88 MsrVal(0x40C, MISCREG_MC3_CTL),
89 MsrVal(0x410, MISCREG_MC4_CTL),
90 MsrVal(0x414, MISCREG_MC5_CTL),
91 MsrVal(0x418, MISCREG_MC6_CTL),
92 MsrVal(0x41C, MISCREG_MC7_CTL),
93 MsrVal(0x401, MISCREG_MC0_STATUS),
94 MsrVal(0x405, MISCREG_MC1_STATUS),
95 MsrVal(0x409, MISCREG_MC2_STATUS),
96 MsrVal(0x40D, MISCREG_MC3_STATUS),
97 MsrVal(0x411, MISCREG_MC4_STATUS),
98 MsrVal(0x415, MISCREG_MC5_STATUS),
99 MsrVal(0x419, MISCREG_MC6_STATUS),
100 MsrVal(0x41D, MISCREG_MC7_STATUS),
101 MsrVal(0x402, MISCREG_MC0_ADDR),
102 MsrVal(0x406, MISCREG_MC1_ADDR),
103 MsrVal(0x40A, MISCREG_MC2_ADDR),
104 MsrVal(0x40E, MISCREG_MC3_ADDR),
105 MsrVal(0x412, MISCREG_MC4_ADDR),
106 MsrVal(0x416, MISCREG_MC5_ADDR),
107 MsrVal(0x41A, MISCREG_MC6_ADDR),
108 MsrVal(0x41E, MISCREG_MC7_ADDR),
109 MsrVal(0x403, MISCREG_MC0_MISC),
110 MsrVal(0x407, MISCREG_MC1_MISC),
111 MsrVal(0x40B, MISCREG_MC2_MISC),
112 MsrVal(0x40F, MISCREG_MC3_MISC),
113 MsrVal(0x413, MISCREG_MC4_MISC),
114 MsrVal(0x417, MISCREG_MC5_MISC),
115 MsrVal(0x41B, MISCREG_MC6_MISC),
116 MsrVal(0x41F, MISCREG_MC7_MISC),
117 MsrVal(0xC0000080, MISCREG_EFER),
118 MsrVal(0xC0000081, MISCREG_STAR),
119 MsrVal(0xC0000082, MISCREG_LSTAR),
120 MsrVal(0xC0000083, MISCREG_CSTAR),
121 MsrVal(0xC0000084, MISCREG_SF_MASK),
122 MsrVal(0xC0000100, MISCREG_FS_BASE),
123 MsrVal(0xC0000101, MISCREG_GS_BASE),
124 MsrVal(0xC0000102, MISCREG_KERNEL_GS_BASE),
125 MsrVal(0xC0000103, MISCREG_TSC_AUX),
126 MsrVal(0xC0010000, MISCREG_PERF_EVT_SEL0),
127 MsrVal(0xC0010001, MISCREG_PERF_EVT_SEL1),
128 MsrVal(0xC0010002, MISCREG_PERF_EVT_SEL2),
129 MsrVal(0xC0010003, MISCREG_PERF_EVT_SEL3),
130 MsrVal(0xC0010004, MISCREG_PERF_EVT_CTR0),
131 MsrVal(0xC0010005, MISCREG_PERF_EVT_CTR1),
132 MsrVal(0xC0010006, MISCREG_PERF_EVT_CTR2),
133 MsrVal(0xC0010007, MISCREG_PERF_EVT_CTR3),
134 MsrVal(0xC0010010, MISCREG_SYSCFG),
135 MsrVal(0xC0010016, MISCREG_IORR_BASE0),
136 MsrVal(0xC0010017, MISCREG_IORR_BASE1),
137 MsrVal(0xC0010018, MISCREG_IORR_MASK0),
138 MsrVal(0xC0010019, MISCREG_IORR_MASK1),
139 MsrVal(0xC001001A, MISCREG_TOP_MEM),
140 MsrVal(0xC001001D, MISCREG_TOP_MEM2),
141 MsrVal(0xC0010114, MISCREG_VM_CR),
142 MsrVal(0xC0010115, MISCREG_IGNNE),
143 MsrVal(0xC0010116, MISCREG_SMM_CTL),
144 MsrVal(0xC0010117, MISCREG_VM_HSAVE_PA)
145};
146
147static const unsigned msrMapSize = sizeof(msrMapData) / sizeof(msrMapData[0]);
148
36typedef MsrMap::value_type MsrVal;
37
38const MsrMap::value_type msrMapData[] = {
39 MsrVal(0x10, MISCREG_TSC),
40 MsrVal(0x1B, MISCREG_APIC_BASE),
41 MsrVal(0xFE, MISCREG_MTRRCAP),
42 MsrVal(0x174, MISCREG_SYSENTER_CS),
43 MsrVal(0x175, MISCREG_SYSENTER_ESP),
44 MsrVal(0x176, MISCREG_SYSENTER_EIP),
45 MsrVal(0x179, MISCREG_MCG_CAP),
46 MsrVal(0x17A, MISCREG_MCG_STATUS),
47 MsrVal(0x17B, MISCREG_MCG_CTL),
48 MsrVal(0x1D9, MISCREG_DEBUG_CTL_MSR),
49 MsrVal(0x1DB, MISCREG_LAST_BRANCH_FROM_IP),
50 MsrVal(0x1DC, MISCREG_LAST_BRANCH_TO_IP),
51 MsrVal(0x1DD, MISCREG_LAST_EXCEPTION_FROM_IP),
52 MsrVal(0x1DE, MISCREG_LAST_EXCEPTION_TO_IP),
53 MsrVal(0x200, MISCREG_MTRR_PHYS_BASE_0),
54 MsrVal(0x201, MISCREG_MTRR_PHYS_MASK_0),
55 MsrVal(0x202, MISCREG_MTRR_PHYS_BASE_1),
56 MsrVal(0x203, MISCREG_MTRR_PHYS_MASK_1),
57 MsrVal(0x204, MISCREG_MTRR_PHYS_BASE_2),
58 MsrVal(0x205, MISCREG_MTRR_PHYS_MASK_2),
59 MsrVal(0x206, MISCREG_MTRR_PHYS_BASE_3),
60 MsrVal(0x207, MISCREG_MTRR_PHYS_MASK_3),
61 MsrVal(0x208, MISCREG_MTRR_PHYS_BASE_4),
62 MsrVal(0x209, MISCREG_MTRR_PHYS_MASK_4),
63 MsrVal(0x20A, MISCREG_MTRR_PHYS_BASE_5),
64 MsrVal(0x20B, MISCREG_MTRR_PHYS_MASK_5),
65 MsrVal(0x20C, MISCREG_MTRR_PHYS_BASE_6),
66 MsrVal(0x20D, MISCREG_MTRR_PHYS_MASK_6),
67 MsrVal(0x20E, MISCREG_MTRR_PHYS_BASE_7),
68 MsrVal(0x20F, MISCREG_MTRR_PHYS_MASK_7),
69 MsrVal(0x250, MISCREG_MTRR_FIX_64K_00000),
70 MsrVal(0x258, MISCREG_MTRR_FIX_16K_80000),
71 MsrVal(0x259, MISCREG_MTRR_FIX_16K_A0000),
72 MsrVal(0x268, MISCREG_MTRR_FIX_4K_C0000),
73 MsrVal(0x269, MISCREG_MTRR_FIX_4K_C8000),
74 MsrVal(0x26A, MISCREG_MTRR_FIX_4K_D0000),
75 MsrVal(0x26B, MISCREG_MTRR_FIX_4K_D8000),
76 MsrVal(0x26C, MISCREG_MTRR_FIX_4K_E0000),
77 MsrVal(0x26D, MISCREG_MTRR_FIX_4K_E8000),
78 MsrVal(0x26E, MISCREG_MTRR_FIX_4K_F0000),
79 MsrVal(0x26F, MISCREG_MTRR_FIX_4K_F8000),
80 MsrVal(0x277, MISCREG_PAT),
81 MsrVal(0x2FF, MISCREG_DEF_TYPE),
82 MsrVal(0x400, MISCREG_MC0_CTL),
83 MsrVal(0x404, MISCREG_MC1_CTL),
84 MsrVal(0x408, MISCREG_MC2_CTL),
85 MsrVal(0x40C, MISCREG_MC3_CTL),
86 MsrVal(0x410, MISCREG_MC4_CTL),
87 MsrVal(0x414, MISCREG_MC5_CTL),
88 MsrVal(0x418, MISCREG_MC6_CTL),
89 MsrVal(0x41C, MISCREG_MC7_CTL),
90 MsrVal(0x401, MISCREG_MC0_STATUS),
91 MsrVal(0x405, MISCREG_MC1_STATUS),
92 MsrVal(0x409, MISCREG_MC2_STATUS),
93 MsrVal(0x40D, MISCREG_MC3_STATUS),
94 MsrVal(0x411, MISCREG_MC4_STATUS),
95 MsrVal(0x415, MISCREG_MC5_STATUS),
96 MsrVal(0x419, MISCREG_MC6_STATUS),
97 MsrVal(0x41D, MISCREG_MC7_STATUS),
98 MsrVal(0x402, MISCREG_MC0_ADDR),
99 MsrVal(0x406, MISCREG_MC1_ADDR),
100 MsrVal(0x40A, MISCREG_MC2_ADDR),
101 MsrVal(0x40E, MISCREG_MC3_ADDR),
102 MsrVal(0x412, MISCREG_MC4_ADDR),
103 MsrVal(0x416, MISCREG_MC5_ADDR),
104 MsrVal(0x41A, MISCREG_MC6_ADDR),
105 MsrVal(0x41E, MISCREG_MC7_ADDR),
106 MsrVal(0x403, MISCREG_MC0_MISC),
107 MsrVal(0x407, MISCREG_MC1_MISC),
108 MsrVal(0x40B, MISCREG_MC2_MISC),
109 MsrVal(0x40F, MISCREG_MC3_MISC),
110 MsrVal(0x413, MISCREG_MC4_MISC),
111 MsrVal(0x417, MISCREG_MC5_MISC),
112 MsrVal(0x41B, MISCREG_MC6_MISC),
113 MsrVal(0x41F, MISCREG_MC7_MISC),
114 MsrVal(0xC0000080, MISCREG_EFER),
115 MsrVal(0xC0000081, MISCREG_STAR),
116 MsrVal(0xC0000082, MISCREG_LSTAR),
117 MsrVal(0xC0000083, MISCREG_CSTAR),
118 MsrVal(0xC0000084, MISCREG_SF_MASK),
119 MsrVal(0xC0000100, MISCREG_FS_BASE),
120 MsrVal(0xC0000101, MISCREG_GS_BASE),
121 MsrVal(0xC0000102, MISCREG_KERNEL_GS_BASE),
122 MsrVal(0xC0000103, MISCREG_TSC_AUX),
123 MsrVal(0xC0010000, MISCREG_PERF_EVT_SEL0),
124 MsrVal(0xC0010001, MISCREG_PERF_EVT_SEL1),
125 MsrVal(0xC0010002, MISCREG_PERF_EVT_SEL2),
126 MsrVal(0xC0010003, MISCREG_PERF_EVT_SEL3),
127 MsrVal(0xC0010004, MISCREG_PERF_EVT_CTR0),
128 MsrVal(0xC0010005, MISCREG_PERF_EVT_CTR1),
129 MsrVal(0xC0010006, MISCREG_PERF_EVT_CTR2),
130 MsrVal(0xC0010007, MISCREG_PERF_EVT_CTR3),
131 MsrVal(0xC0010010, MISCREG_SYSCFG),
132 MsrVal(0xC0010016, MISCREG_IORR_BASE0),
133 MsrVal(0xC0010017, MISCREG_IORR_BASE1),
134 MsrVal(0xC0010018, MISCREG_IORR_MASK0),
135 MsrVal(0xC0010019, MISCREG_IORR_MASK1),
136 MsrVal(0xC001001A, MISCREG_TOP_MEM),
137 MsrVal(0xC001001D, MISCREG_TOP_MEM2),
138 MsrVal(0xC0010114, MISCREG_VM_CR),
139 MsrVal(0xC0010115, MISCREG_IGNNE),
140 MsrVal(0xC0010116, MISCREG_SMM_CTL),
141 MsrVal(0xC0010117, MISCREG_VM_HSAVE_PA)
142};
143
144static const unsigned msrMapSize = sizeof(msrMapData) / sizeof(msrMapData[0]);
145
149static MsrMap msrMap(msrMapData, msrMapData + msrMapSize);
146const MsrMap msrMap(msrMapData, msrMapData + msrMapSize);
150
151bool
152msrAddrToIndex(MiscRegIndex &regNum, Addr addr)
153{
147
148bool
149msrAddrToIndex(MiscRegIndex &regNum, Addr addr)
150{
154 MsrMap::iterator it = msrMap.find(addr);
151 MsrMap::const_iterator it(msrMap.find(addr));
155 if (it == msrMap.end()) {
156 return false;
157 } else {
158 regNum = it->second;
159 return true;
160 }
161}
162
163} // namespace X86ISA
152 if (it == msrMap.end()) {
153 return false;
154 } else {
155 regNum = it->second;
156 return true;
157 }
158}
159
160} // namespace X86ISA