misc.hh (10554:fe2e2f06a7c8) misc.hh (11324:31ca646c7685)
1/*
2 * Copyright (c) 2007-2008 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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96 CC2Bit = 1 << 10,
97 CC3Bit = 1 << 14,
98 BusyBit = 1 << 15,
99 };
100
101 enum MiscRegIndex
102 {
103 // Control registers
1/*
2 * Copyright (c) 2007-2008 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 87 unchanged lines hidden (view full) ---

96 CC2Bit = 1 << 10,
97 CC3Bit = 1 << 14,
98 BusyBit = 1 << 15,
99 };
100
101 enum MiscRegIndex
102 {
103 // Control registers
104 // Most of these are invalid.
104 // Most of these are invalid. See isValidMiscReg() below.
105 MISCREG_CR_BASE,
106 MISCREG_CR0 = MISCREG_CR_BASE,
107 MISCREG_CR1,
108 MISCREG_CR2,
109 MISCREG_CR3,
110 MISCREG_CR4,
111 MISCREG_CR5,
112 MISCREG_CR6,

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394 MISCREG_APIC_BASE,
395
396 // "Fake" MSRs for internally implemented devices
397 MISCREG_PCI_CONFIG_ADDRESS,
398
399 NUM_MISCREGS
400 };
401
105 MISCREG_CR_BASE,
106 MISCREG_CR0 = MISCREG_CR_BASE,
107 MISCREG_CR1,
108 MISCREG_CR2,
109 MISCREG_CR3,
110 MISCREG_CR4,
111 MISCREG_CR5,
112 MISCREG_CR6,

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394 MISCREG_APIC_BASE,
395
396 // "Fake" MSRs for internally implemented devices
397 MISCREG_PCI_CONFIG_ADDRESS,
398
399 NUM_MISCREGS
400 };
401
402 static inline bool
403 isValidMiscReg(int index)
404 {
405 return (index >= MISCREG_CR0 && index < NUM_MISCREGS &&
406 index != MISCREG_CR1 &&
407 !(index > MISCREG_CR4 && index < MISCREG_CR8) &&
408 !(index > MISCREG_CR8 && index <= MISCREG_CR15));
409 }
410
402 static inline MiscRegIndex
403 MISCREG_CR(int index)
404 {
405 assert(index >= 0 && index < NumCRegs);
406 return (MiscRegIndex)(MISCREG_CR_BASE + index);
407 }
408
409 static inline MiscRegIndex

--- 591 unchanged lines hidden --- 		411 static inline MiscRegIndex
412 MISCREG_CR(int index)
413 {
414 assert(index >= 0 && index < NumCRegs);
415 return (MiscRegIndex)(MISCREG_CR_BASE + index);
416 }
417
418 static inline MiscRegIndex

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