1/*
2 * Copyright (c) 2014 Advanced Micro Devices, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Alexandru Dutu
29 */
30
31#include "arch/x86/pseudo_inst.hh"
| 1/*
2 * Copyright (c) 2014 Advanced Micro Devices, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Alexandru Dutu
29 */
30
31#include "arch/x86/pseudo_inst.hh"
|
34
35using namespace X86ISA;
36
37namespace X86ISA {
38
39/*
40 * This function is executed when the simulation is executing the syscall
41 * handler in System Emulation mode.
42 */
43void
44m5Syscall(ThreadContext *tc)
45{
46 DPRINTF(PseudoInst, "PseudoInst::m5Syscall()\n");
47
48 tc->syscall(tc->readIntReg(INTREG_RAX));
49 MiscReg rflags = tc->readMiscReg(MISCREG_RFLAGS);
50 rflags &= ~(1 << 16);
51 tc->setMiscReg(MISCREG_RFLAGS, rflags);
52}
53
54/*
55 * This function is executed when the simulation is executing the pagefault
56 * handler in System Emulation mode.
57 */
58void
59m5PageFault(ThreadContext *tc)
60{
61 DPRINTF(PseudoInst, "PseudoInst::m5PageFault()\n");
62
63 Process *p = tc->getProcessPtr();
64 if (!p->fixupStackFault(tc->readMiscReg(MISCREG_CR2))) {
| 36
37using namespace X86ISA;
38
39namespace X86ISA {
40
41/*
42 * This function is executed when the simulation is executing the syscall
43 * handler in System Emulation mode.
44 */
45void
46m5Syscall(ThreadContext *tc)
47{
48 DPRINTF(PseudoInst, "PseudoInst::m5Syscall()\n");
49
50 tc->syscall(tc->readIntReg(INTREG_RAX));
51 MiscReg rflags = tc->readMiscReg(MISCREG_RFLAGS);
52 rflags &= ~(1 << 16);
53 tc->setMiscReg(MISCREG_RFLAGS, rflags);
54}
55
56/*
57 * This function is executed when the simulation is executing the pagefault
58 * handler in System Emulation mode.
59 */
60void
61m5PageFault(ThreadContext *tc)
62{
63 DPRINTF(PseudoInst, "PseudoInst::m5PageFault()\n");
64
65 Process *p = tc->getProcessPtr();
66 if (!p->fixupStackFault(tc->readMiscReg(MISCREG_CR2))) {
|
65 panic("Page fault at %#x ", tc->readMiscReg(MISCREG_CR2));
66 }
| 67 SETranslatingPortProxy proxy = tc->getMemProxy();
68 // at this point we should have 6 values on the interrupt stack
69 int size = 6;
70 uint64_t is[size];
71 // reading the interrupt handler stack
72 proxy.readBlob(ISTVirtAddr + PageBytes - size*sizeof(uint64_t),
73 (uint8_t *)&is, sizeof(is));
74 panic("Page fault at addr %#x\n\tInterrupt handler stack:\n"
75 "\tss: %#x\n"
76 "\trsp: %#x\n"
77 "\trflags: %#x\n"
78 "\tcs: %#x\n"
79 "\trip: %#x\n"
80 "\terr_code: %#x\n",
81 tc->readMiscReg(MISCREG_CR2),
82 is[5], is[4], is[3], is[2], is[1], is[0]);
83 }
|