process.hh (9552:460cf901acba) process.hh (10299:bec0c5ffc323)
1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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39
40#ifndef __ARCH_X86_PROCESS_HH__
41#define __ARCH_X86_PROCESS_HH__
42
43#include <string>
44#include <vector>
45
46#include "sim/process.hh"
1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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39
40#ifndef __ARCH_X86_PROCESS_HH__
41#define __ARCH_X86_PROCESS_HH__
42
43#include <string>
44#include <vector>
45
46#include "sim/process.hh"
47#include "mem/multi_level_page_table.hh"
47
48class SyscallDesc;
49
50namespace X86ISA
51{
52 enum X86AuxiliaryVectorTypes {
53 M5_AT_SYSINFO = 32,
54 M5_AT_SYSINFO_EHDR = 33

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128 void argsInit(int intSize, int pageSize);
129 void initState();
130
131 void syscall(int64_t callnum, ThreadContext *tc);
132 X86ISA::IntReg getSyscallArg(ThreadContext *tc, int &i);
133 X86ISA::IntReg getSyscallArg(ThreadContext *tc, int &i, int width);
134 void setSyscallArg(ThreadContext *tc, int i, X86ISA::IntReg val);
135 };
48
49class SyscallDesc;
50
51namespace X86ISA
52{
53 enum X86AuxiliaryVectorTypes {
54 M5_AT_SYSINFO = 32,
55 M5_AT_SYSINFO_EHDR = 33

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129 void argsInit(int intSize, int pageSize);
130 void initState();
131
132 void syscall(int64_t callnum, ThreadContext *tc);
133 X86ISA::IntReg getSyscallArg(ThreadContext *tc, int &i);
134 X86ISA::IntReg getSyscallArg(ThreadContext *tc, int &i, int width);
135 void setSyscallArg(ThreadContext *tc, int i, X86ISA::IntReg val);
136 };
137
138 /**
139 * Declaration of architectural page table for x86.
140 *
141 * These page tables are stored in system memory and respect x86 specification.
142 */
143 typedef MultiLevelPageTable<PageTableOps> ArchPageTable;
144
136}
137
138#endif // __ARCH_X86_PROCESS_HH__
145}
146
147#endif // __ARCH_X86_PROCESS_HH__