process.cc (6110:5051aafec8d5) process.cc (6140:7a2dc7d41ee1)
1/*
2 * Copyright (c) 2003-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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227 csAttr.readable = 1;
228 csAttr.expandDown = 0;
229 csAttr.dpl = 3;
230 csAttr.defaultSize = 0;
231 csAttr.longMode = 1;
232
233 tc->setMiscRegNoEffect(MISCREG_CS_ATTR, csAttr);
234
1/*
2 * Copyright (c) 2003-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 218 unchanged lines hidden (view full) ---

227 csAttr.readable = 1;
228 csAttr.expandDown = 0;
229 csAttr.dpl = 3;
230 csAttr.defaultSize = 0;
231 csAttr.longMode = 1;
232
233 tc->setMiscRegNoEffect(MISCREG_CS_ATTR, csAttr);
234
235 Efer efer = 0;
236 efer.sce = 1; // Enable system call extensions.
237 efer.lme = 1; // Enable long mode.
238 efer.lma = 1; // Activate long mode.
239 efer.nxe = 1; // Enable nx support.
240 efer.svme = 0; // Disable svm support for now. It isn't implemented.
241 efer.ffxsr = 1; // Turn on fast fxsave and fxrstor.
242 tc->setMiscReg(MISCREG_EFER, efer);
243
235 //Set up the registers that describe the operating mode.
236 CR0 cr0 = 0;
237 cr0.pg = 1; // Turn on paging.
238 cr0.cd = 0; // Don't disable caching.
239 cr0.nw = 0; // This is bit is defined to be ignored.
240 cr0.am = 0; // No alignment checking
241 cr0.wp = 0; // Supervisor mode can write read only pages
242 cr0.ne = 1;
243 cr0.et = 1; // This should always be 1
244 cr0.ts = 0; // We don't do task switching, so causing fp exceptions
245 // would be pointless.
246 cr0.em = 0; // Allow x87 instructions to execute natively.
247 cr0.mp = 1; // This doesn't really matter, but the manual suggests
248 // setting it to one.
249 cr0.pe = 1; // We're definitely in protected mode.
250 tc->setMiscReg(MISCREG_CR0, cr0);
244 //Set up the registers that describe the operating mode.
245 CR0 cr0 = 0;
246 cr0.pg = 1; // Turn on paging.
247 cr0.cd = 0; // Don't disable caching.
248 cr0.nw = 0; // This is bit is defined to be ignored.
249 cr0.am = 0; // No alignment checking
250 cr0.wp = 0; // Supervisor mode can write read only pages
251 cr0.ne = 1;
252 cr0.et = 1; // This should always be 1
253 cr0.ts = 0; // We don't do task switching, so causing fp exceptions
254 // would be pointless.
255 cr0.em = 0; // Allow x87 instructions to execute natively.
256 cr0.mp = 1; // This doesn't really matter, but the manual suggests
257 // setting it to one.
258 cr0.pe = 1; // We're definitely in protected mode.
259 tc->setMiscReg(MISCREG_CR0, cr0);
251
252 Efer efer = 0;
253 efer.sce = 1; // Enable system call extensions.
254 efer.lme = 1; // Enable long mode.
255 efer.lma = 1; // Activate long mode.
256 efer.nxe = 1; // Enable nx support.
257 efer.svme = 0; // Disable svm support for now. It isn't implemented.
258 efer.ffxsr = 1; // Turn on fast fxsave and fxrstor.
259 tc->setMiscReg(MISCREG_EFER, efer);
260 }
261}
262
263void
264I386LiveProcess::startup()
265{
266 LiveProcess::startup();
267

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335
336 tc->setMiscRegNoEffect(MISCREG_TSG_BASE, _gdtStart);
337 tc->setMiscRegNoEffect(MISCREG_TSG_EFF_BASE, _gdtStart);
338 tc->setMiscRegNoEffect(MISCREG_TSG_LIMIT, _gdtStart + _gdtSize - 1);
339
340 // Set the LDT selector to 0 to deactivate it.
341 tc->setMiscRegNoEffect(MISCREG_TSL, 0);
342
260 }
261}
262
263void
264I386LiveProcess::startup()
265{
266 LiveProcess::startup();
267

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335
336 tc->setMiscRegNoEffect(MISCREG_TSG_BASE, _gdtStart);
337 tc->setMiscRegNoEffect(MISCREG_TSG_EFF_BASE, _gdtStart);
338 tc->setMiscRegNoEffect(MISCREG_TSG_LIMIT, _gdtStart + _gdtSize - 1);
339
340 // Set the LDT selector to 0 to deactivate it.
341 tc->setMiscRegNoEffect(MISCREG_TSL, 0);
342
343 Efer efer = 0;
344 efer.sce = 1; // Enable system call extensions.
345 efer.lme = 1; // Enable long mode.
346 efer.lma = 0; // Deactivate long mode.
347 efer.nxe = 1; // Enable nx support.
348 efer.svme = 0; // Disable svm support for now. It isn't implemented.
349 efer.ffxsr = 1; // Turn on fast fxsave and fxrstor.
350 tc->setMiscReg(MISCREG_EFER, efer);
351
343 //Set up the registers that describe the operating mode.
344 CR0 cr0 = 0;
345 cr0.pg = 1; // Turn on paging.
346 cr0.cd = 0; // Don't disable caching.
347 cr0.nw = 0; // This is bit is defined to be ignored.
348 cr0.am = 0; // No alignment checking
349 cr0.wp = 0; // Supervisor mode can write read only pages
350 cr0.ne = 1;
351 cr0.et = 1; // This should always be 1
352 cr0.ts = 0; // We don't do task switching, so causing fp exceptions
353 // would be pointless.
354 cr0.em = 0; // Allow x87 instructions to execute natively.
355 cr0.mp = 1; // This doesn't really matter, but the manual suggests
356 // setting it to one.
357 cr0.pe = 1; // We're definitely in protected mode.
358 tc->setMiscReg(MISCREG_CR0, cr0);
352 //Set up the registers that describe the operating mode.
353 CR0 cr0 = 0;
354 cr0.pg = 1; // Turn on paging.
355 cr0.cd = 0; // Don't disable caching.
356 cr0.nw = 0; // This is bit is defined to be ignored.
357 cr0.am = 0; // No alignment checking
358 cr0.wp = 0; // Supervisor mode can write read only pages
359 cr0.ne = 1;
360 cr0.et = 1; // This should always be 1
361 cr0.ts = 0; // We don't do task switching, so causing fp exceptions
362 // would be pointless.
363 cr0.em = 0; // Allow x87 instructions to execute natively.
364 cr0.mp = 1; // This doesn't really matter, but the manual suggests
365 // setting it to one.
366 cr0.pe = 1; // We're definitely in protected mode.
367 tc->setMiscReg(MISCREG_CR0, cr0);
359
360 Efer efer = 0;
361 efer.sce = 1; // Enable system call extensions.
362 efer.lme = 1; // Enable long mode.
363 efer.lma = 0; // Deactivate long mode.
364 efer.nxe = 1; // Enable nx support.
365 efer.svme = 0; // Disable svm support for now. It isn't implemented.
366 efer.ffxsr = 1; // Turn on fast fxsave and fxrstor.
367 tc->setMiscReg(MISCREG_EFER, efer);
368 }
369}
370
371template<class IntType>
372void
373X86LiveProcess::argsInit(int pageSize,
374 std::vector<AuxVector<IntType> > extraAuxvs)
375{

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369}
370
371template<class IntType>
372void
373X86LiveProcess::argsInit(int pageSize,
374 std::vector<AuxVector<IntType> > extraAuxvs)
375{

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