process.cc (10318:98771a936b61) process.cc (10554:fe2e2f06a7c8)
1/*
1/*
2 * Copyright (c) 2014 Advanced Micro Devices, Inc.
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license

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40 * Authors: Gabe Black
41 * Ali Saidi
42 */
43
44#include "arch/x86/regs/misc.hh"
45#include "arch/x86/regs/segment.hh"
46#include "arch/x86/isa_traits.hh"
47#include "arch/x86/process.hh"
3 * Copyright (c) 2007 The Hewlett-Packard Development Company
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license

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41 * Authors: Gabe Black
42 * Ali Saidi
43 */
44
45#include "arch/x86/regs/misc.hh"
46#include "arch/x86/regs/segment.hh"
47#include "arch/x86/isa_traits.hh"
48#include "arch/x86/process.hh"
49#include "arch/x86/system.hh"
48#include "arch/x86/types.hh"
49#include "base/loader/elf_object.hh"
50#include "base/loader/object_file.hh"
51#include "base/misc.hh"
52#include "base/trace.hh"
53#include "cpu/thread_context.hh"
54#include "debug/Stack.hh"
50#include "arch/x86/types.hh"
51#include "base/loader/elf_object.hh"
52#include "base/loader/object_file.hh"
53#include "base/misc.hh"
54#include "base/trace.hh"
55#include "cpu/thread_context.hh"
56#include "debug/Stack.hh"
57#include "mem/multi_level_page_table.hh"
55#include "mem/page_table.hh"
56#include "sim/process_impl.hh"
57#include "sim/syscall_emul.hh"
58#include "sim/system.hh"
59
60using namespace std;
61using namespace X86ISA;
62

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178 uint8_t vgettimeofdayBlob[] = {
179 0x48,0xc7,0xc0,0x60,0x00,0x00,0x00, // mov $0x60,%rax
180 0x0f,0x05, // syscall
181 0xc3 // retq
182 };
183 initVirtMem.writeBlob(vsyscallPage.base + vsyscallPage.vgettimeofdayOffset,
184 vgettimeofdayBlob, sizeof(vgettimeofdayBlob));
185
58#include "mem/page_table.hh"
59#include "sim/process_impl.hh"
60#include "sim/syscall_emul.hh"
61#include "sim/system.hh"
62
63using namespace std;
64using namespace X86ISA;
65

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181 uint8_t vgettimeofdayBlob[] = {
182 0x48,0xc7,0xc0,0x60,0x00,0x00,0x00, // mov $0x60,%rax
183 0x0f,0x05, // syscall
184 0xc3 // retq
185 };
186 initVirtMem.writeBlob(vsyscallPage.base + vsyscallPage.vgettimeofdayOffset,
187 vgettimeofdayBlob, sizeof(vgettimeofdayBlob));
188
186 for (int i = 0; i < contextIds.size(); i++) {
187 ThreadContext * tc = system->getThreadContext(contextIds[i]);
189 if (kvmInSE) {
190 PortProxy physProxy = system->physProxy;
188
191
189 SegAttr dataAttr = 0;
190 dataAttr.dpl = 3;
191 dataAttr.unusable = 0;
192 dataAttr.defaultSize = 1;
193 dataAttr.longMode = 1;
194 dataAttr.avl = 0;
195 dataAttr.granularity = 1;
196 dataAttr.present = 1;
197 dataAttr.type = 3;
198 dataAttr.writable = 1;
199 dataAttr.readable = 1;
200 dataAttr.expandDown = 0;
201 dataAttr.system = 1;
192 /*
193 * Set up the gdt.
194 */
195 uint8_t numGDTEntries = 0;
196 uint64_t nullDescriptor = 0;
197 physProxy.writeBlob(GDTPhysAddr + numGDTEntries * 8,
198 (uint8_t *)(&nullDescriptor), 8);
199 numGDTEntries++;
202
200
203 //Initialize the segment registers.
204 for(int seg = 0; seg < NUM_SEGMENTREGS; seg++) {
205 tc->setMiscRegNoEffect(MISCREG_SEG_BASE(seg), 0);
206 tc->setMiscRegNoEffect(MISCREG_SEG_EFF_BASE(seg), 0);
207 tc->setMiscRegNoEffect(MISCREG_SEG_ATTR(seg), dataAttr);
201 SegDescriptor initDesc = 0;
202 initDesc.type.codeOrData = 0; // code or data type
203 initDesc.type.c = 0; // conforming
204 initDesc.type.r = 1; // readable
205 initDesc.dpl = 0; // privilege
206 initDesc.p = 1; // present
207 initDesc.l = 1; // longmode - 64 bit
208 initDesc.d = 0; // operand size
209 initDesc.g = 1; // granularity
210 initDesc.s = 1; // system segment
211 initDesc.limitHigh = 0xFFFF;
212 initDesc.limitLow = 0xF;
213 initDesc.baseHigh = 0x0;
214 initDesc.baseLow = 0x0;
215
216 //64 bit code segment
217 SegDescriptor csLowPLDesc = initDesc;
218 csLowPLDesc.type.codeOrData = 1;
219 csLowPLDesc.dpl = 0;
220 uint64_t csLowPLDescVal = csLowPLDesc;
221 physProxy.writeBlob(GDTPhysAddr + numGDTEntries * 8,
222 (uint8_t *)(&csLowPLDescVal), 8);
223
224 numGDTEntries++;
225
226 SegSelector csLowPL = 0;
227 csLowPL.si = numGDTEntries - 1;
228 csLowPL.rpl = 0;
229
230 //64 bit data segment
231 SegDescriptor dsLowPLDesc = initDesc;
232 dsLowPLDesc.type.codeOrData = 0;
233 dsLowPLDesc.dpl = 0;
234 uint64_t dsLowPLDescVal = dsLowPLDesc;
235 physProxy.writeBlob(GDTPhysAddr + numGDTEntries * 8,
236 (uint8_t *)(&dsLowPLDescVal), 8);
237
238 numGDTEntries++;
239
240 SegSelector dsLowPL = 0;
241 dsLowPL.si = numGDTEntries - 1;
242 dsLowPL.rpl = 0;
243
244 //64 bit data segment
245 SegDescriptor dsDesc = initDesc;
246 dsDesc.type.codeOrData = 0;
247 dsDesc.dpl = 3;
248 uint64_t dsDescVal = dsDesc;
249 physProxy.writeBlob(GDTPhysAddr + numGDTEntries * 8,
250 (uint8_t *)(&dsDescVal), 8);
251
252 numGDTEntries++;
253
254 SegSelector ds = 0;
255 ds.si = numGDTEntries - 1;
256 ds.rpl = 3;
257
258 //64 bit code segment
259 SegDescriptor csDesc = initDesc;
260 csDesc.type.codeOrData = 1;
261 csDesc.dpl = 3;
262 uint64_t csDescVal = csDesc;
263 physProxy.writeBlob(GDTPhysAddr + numGDTEntries * 8,
264 (uint8_t *)(&csDescVal), 8);
265
266 numGDTEntries++;
267
268 SegSelector cs = 0;
269 cs.si = numGDTEntries - 1;
270 cs.rpl = 3;
271
272 SegSelector scall = 0;
273 scall.si = csLowPL.si;
274 scall.rpl = 0;
275
276 SegSelector sret = 0;
277 sret.si = dsLowPL.si;
278 sret.rpl = 3;
279
280 /* In long mode the TSS has been extended to 16 Bytes */
281 TSSlow TSSDescLow = 0;
282 TSSDescLow.type = 0xB;
283 TSSDescLow.dpl = 0; // Privelege level 0
284 TSSDescLow.p = 1; // Present
285 TSSDescLow.g = 1; // Page granularity
286 TSSDescLow.limitHigh = 0xF;
287 TSSDescLow.limitLow = 0xFFFF;
288 TSSDescLow.baseLow = (((uint32_t)TSSVirtAddr) << 8) >> 8;
289 TSSDescLow.baseHigh = (uint8_t)(((uint32_t)TSSVirtAddr) >> 24);
290
291 TSShigh TSSDescHigh = 0;
292 TSSDescHigh.base = (uint32_t)(TSSVirtAddr >> 32);
293
294 struct TSSDesc {
295 uint64_t low;
296 uint64_t high;
297 } tssDescVal = {TSSDescLow, TSSDescHigh};
298
299 physProxy.writeBlob(GDTPhysAddr + numGDTEntries * 8,
300 (uint8_t *)(&tssDescVal), sizeof(tssDescVal));
301
302 numGDTEntries++;
303
304 SegSelector tssSel = 0;
305 tssSel.si = numGDTEntries - 1;
306
307 uint64_t tss_base_addr = (TSSDescHigh.base << 32) | ((TSSDescLow.baseHigh << 24) | TSSDescLow.baseLow);
308 uint64_t tss_limit = TSSDescLow.limitLow | (TSSDescLow.limitHigh << 16);
309
310 SegAttr tss_attr = 0;
311
312 tss_attr.type = TSSDescLow.type;
313 tss_attr.dpl = TSSDescLow.dpl;
314 tss_attr.present = TSSDescLow.p;
315 tss_attr.granularity = TSSDescLow.g;
316 tss_attr.unusable = 0;
317
318 for (int i = 0; i < contextIds.size(); i++) {
319 ThreadContext * tc = system->getThreadContext(contextIds[i]);
320
321 tc->setMiscReg(MISCREG_CS, (MiscReg)cs);
322 tc->setMiscReg(MISCREG_DS, (MiscReg)ds);
323 tc->setMiscReg(MISCREG_ES, (MiscReg)ds);
324 tc->setMiscReg(MISCREG_FS, (MiscReg)ds);
325 tc->setMiscReg(MISCREG_GS, (MiscReg)ds);
326 tc->setMiscReg(MISCREG_SS, (MiscReg)ds);
327
328 // LDT
329 tc->setMiscReg(MISCREG_TSL, 0);
330 SegAttr tslAttr = 0;
331 tslAttr.present = 1;
332 tslAttr.type = 2;
333 tc->setMiscReg(MISCREG_TSL_ATTR, tslAttr);
334
335 tc->setMiscReg(MISCREG_TSG_BASE, GDTVirtAddr);
336 tc->setMiscReg(MISCREG_TSG_LIMIT, 8 * numGDTEntries - 1);
337
338 tc->setMiscReg(MISCREG_TR, (MiscReg)tssSel);
339 tc->setMiscReg(MISCREG_SEG_BASE(SYS_SEGMENT_REG_TR), tss_base_addr);
340 tc->setMiscReg(MISCREG_SEG_EFF_BASE(SYS_SEGMENT_REG_TR), 0);
341 tc->setMiscReg(MISCREG_SEG_LIMIT(SYS_SEGMENT_REG_TR), tss_limit);
342 tc->setMiscReg(MISCREG_SEG_ATTR(SYS_SEGMENT_REG_TR), (MiscReg)tss_attr);
343
344 //Start using longmode segments.
345 installSegDesc(tc, SEGMENT_REG_CS, csDesc, true);
346 installSegDesc(tc, SEGMENT_REG_DS, dsDesc, true);
347 installSegDesc(tc, SEGMENT_REG_ES, dsDesc, true);
348 installSegDesc(tc, SEGMENT_REG_FS, dsDesc, true);
349 installSegDesc(tc, SEGMENT_REG_GS, dsDesc, true);
350 installSegDesc(tc, SEGMENT_REG_SS, dsDesc, true);
351
352 Efer efer = 0;
353 efer.sce = 1; // Enable system call extensions.
354 efer.lme = 1; // Enable long mode.
355 efer.lma = 1; // Activate long mode.
356 efer.nxe = 0; // Enable nx support.
357 efer.svme = 1; // Enable svm support for now.
358 efer.ffxsr = 0; // Turn on fast fxsave and fxrstor.
359 tc->setMiscReg(MISCREG_EFER, efer);
360
361 //Set up the registers that describe the operating mode.
362 CR0 cr0 = 0;
363 cr0.pg = 1; // Turn on paging.
364 cr0.cd = 0; // Don't disable caching.
365 cr0.nw = 0; // This is bit is defined to be ignored.
366 cr0.am = 1; // No alignment checking
367 cr0.wp = 1; // Supervisor mode can write read only pages
368 cr0.ne = 1;
369 cr0.et = 1; // This should always be 1
370 cr0.ts = 0; // We don't do task switching, so causing fp exceptions
371 // would be pointless.
372 cr0.em = 0; // Allow x87 instructions to execute natively.
373 cr0.mp = 1; // This doesn't really matter, but the manual suggests
374 // setting it to one.
375 cr0.pe = 1; // We're definitely in protected mode.
376 tc->setMiscReg(MISCREG_CR0, cr0);
377
378 CR0 cr2 = 0;
379 tc->setMiscReg(MISCREG_CR2, cr2);
380
381 CR3 cr3 = pageTablePhysAddr;
382 tc->setMiscReg(MISCREG_CR3, cr3);
383
384 CR4 cr4 = 0;
385 //Turn on pae.
386 cr4.osxsave = 1; // Enable XSAVE and Proc Extended States
387 cr4.osxmmexcpt = 1; // Operating System Unmasked Exception
388 cr4.osfxsr = 1; // Operating System FXSave/FSRSTOR Support
389 cr4.pce = 0; // Performance-Monitoring Counter Enable
390 cr4.pge = 0; // Page-Global Enable
391 cr4.mce = 0; // Machine Check Enable
392 cr4.pae = 1; // Physical-Address Extension
393 cr4.pse = 0; // Page Size Extensions
394 cr4.de = 0; // Debugging Extensions
395 cr4.tsd = 0; // Time Stamp Disable
396 cr4.pvi = 0; // Protected-Mode Virtual Interrupts
397 cr4.vme = 0; // Virtual-8086 Mode Extensions
398
399 tc->setMiscReg(MISCREG_CR4, cr4);
400
401 CR4 cr8 = 0;
402 tc->setMiscReg(MISCREG_CR8, cr8);
403
404 const Addr PageMapLevel4 = pageTablePhysAddr;
405 //Point to the page tables.
406 tc->setMiscReg(MISCREG_CR3, PageMapLevel4);
407
408 tc->setMiscReg(MISCREG_MXCSR, 0x1f80);
409
410 tc->setMiscReg(MISCREG_APIC_BASE, 0xfee00900);
411
412 tc->setMiscReg(MISCREG_SEG_BASE(MISCREG_TSG - MISCREG_SEG_SEL_BASE), GDTVirtAddr);
413 tc->setMiscReg(MISCREG_SEG_LIMIT(MISCREG_TSG - MISCREG_SEG_SEL_BASE), 0xffff);
414
415 tc->setMiscReg(MISCREG_SEG_BASE(MISCREG_IDTR - MISCREG_SEG_SEL_BASE), IDTVirtAddr);
416 tc->setMiscReg(MISCREG_SEG_LIMIT(MISCREG_IDTR - MISCREG_SEG_SEL_BASE), 0xffff);
417
418 /* enabling syscall and sysret */
419 MiscReg star = ((MiscReg)sret << 48) | ((MiscReg)scall << 32);
420 tc->setMiscReg(MISCREG_STAR, star);
421 MiscReg lstar = (MiscReg) syscallCodeVirtAddr;
422 tc->setMiscReg(MISCREG_LSTAR, lstar);
423 MiscReg sfmask = (1<<8) | (1<<10); // TF | DF
424 tc->setMiscReg(MISCREG_SF_MASK, sfmask);
208 }
209
425 }
426
210 SegAttr csAttr = 0;
211 csAttr.dpl = 3;
212 csAttr.unusable = 0;
213 csAttr.defaultSize = 0;
214 csAttr.longMode = 1;
215 csAttr.avl = 0;
216 csAttr.granularity = 1;
217 csAttr.present = 1;
218 csAttr.type = 10;
219 csAttr.writable = 0;
220 csAttr.readable = 1;
221 csAttr.expandDown = 0;
222 csAttr.system = 1;
427 /*
428 * Setting up the content of the TSS
429 * and writting it to physical memory
430 */
223
431
224 tc->setMiscRegNoEffect(MISCREG_CS_ATTR, csAttr);
432 struct {
433 uint32_t reserved0; // +00h
434 uint32_t RSP0_low; // +04h
435 uint32_t RSP0_high; // +08h
436 uint32_t RSP1_low; // +0Ch
437 uint32_t RSP1_high; // +10h
438 uint32_t RSP2_low; // +14h
439 uint32_t RSP2_high; // +18h
440 uint32_t reserved1; // +1Ch
441 uint32_t reserved2; // +20h
442 uint32_t IST1_low; // +24h
443 uint32_t IST1_high; // +28h
444 uint32_t IST2_low; // +2Ch
445 uint32_t IST2_high; // +30h
446 uint32_t IST3_low; // +34h
447 uint32_t IST3_high; // +38h
448 uint32_t IST4_low; // +3Ch
449 uint32_t IST4_high; // +40h
450 uint32_t IST5_low; // +44h
451 uint32_t IST5_high; // +48h
452 uint32_t IST6_low; // +4Ch
453 uint32_t IST6_high; // +50h
454 uint32_t IST7_low; // +54h
455 uint32_t IST7_high; // +58h
456 uint32_t reserved3; // +5Ch
457 uint32_t reserved4; // +60h
458 uint16_t reserved5; // +64h
459 uint16_t IO_MapBase; // +66h
460 } tss;
225
461
226 Efer efer = 0;
227 efer.sce = 1; // Enable system call extensions.
228 efer.lme = 1; // Enable long mode.
229 efer.lma = 1; // Activate long mode.
230 efer.nxe = 1; // Enable nx support.
231 efer.svme = 0; // Disable svm support for now. It isn't implemented.
232 efer.ffxsr = 1; // Turn on fast fxsave and fxrstor.
233 tc->setMiscReg(MISCREG_EFER, efer);
462 /** setting Interrupt Stack Table */
463 uint64_t IST_start = ISTVirtAddr + PageBytes;
464 tss.IST1_low = (uint32_t)IST_start;
465 tss.IST1_high = (uint32_t)(IST_start >> 32);
466 tss.RSP0_low = tss.IST1_low;
467 tss.RSP0_high = tss.IST1_high;
468 tss.RSP1_low = tss.IST1_low;
469 tss.RSP1_high = tss.IST1_high;
470 tss.RSP2_low = tss.IST1_low;
471 tss.RSP2_high = tss.IST1_high;
472 physProxy.writeBlob(TSSPhysAddr, (uint8_t *)(&tss), sizeof(tss));
234
473
235 //Set up the registers that describe the operating mode.
236 CR0 cr0 = 0;
237 cr0.pg = 1; // Turn on paging.
238 cr0.cd = 0; // Don't disable caching.
239 cr0.nw = 0; // This is bit is defined to be ignored.
240 cr0.am = 0; // No alignment checking
241 cr0.wp = 0; // Supervisor mode can write read only pages
242 cr0.ne = 1;
243 cr0.et = 1; // This should always be 1
244 cr0.ts = 0; // We don't do task switching, so causing fp exceptions
245 // would be pointless.
246 cr0.em = 0; // Allow x87 instructions to execute natively.
247 cr0.mp = 1; // This doesn't really matter, but the manual suggests
248 // setting it to one.
249 cr0.pe = 1; // We're definitely in protected mode.
250 tc->setMiscReg(MISCREG_CR0, cr0);
474 /* Setting IDT gates */
475 GateDescriptorLow PFGateLow = 0;
476 PFGateLow.offsetHigh = (uint16_t)((uint32_t)PFHandlerVirtAddr >> 16);
477 PFGateLow.offsetLow = (uint16_t)PFHandlerVirtAddr;
478 PFGateLow.selector = (MiscReg)csLowPL;
479 PFGateLow.p = 1;
480 PFGateLow.dpl = 0;
481 PFGateLow.type = 0xe; // gate interrupt type
482 PFGateLow.IST = 0; // setting IST to 0 and using RSP0
251
483
252 tc->setMiscReg(MISCREG_MXCSR, 0x1f80);
484 GateDescriptorHigh PFGateHigh = 0;
485 PFGateHigh.offset = (uint32_t)(PFHandlerVirtAddr >> 32);
486
487 struct {
488 uint64_t low;
489 uint64_t high;
490 } PFGate = {PFGateLow, PFGateHigh};
491
492 physProxy.writeBlob(IDTPhysAddr + 0xE0,
493 (uint8_t *)(&PFGate), sizeof(PFGate));
494
495 /** System call handler */
496 uint8_t syscallBlob[] = {
497 0x48,0xa3,0x00,0x60,0x00,
498 0x00,0x00,0xc9,0xff,0xff, // mov %rax, (0xffffc90000005600)
499 0x48,0x0f,0x07, // sysret
500 };
501
502 physProxy.writeBlob(syscallCodePhysAddr,
503 syscallBlob, sizeof(syscallBlob));
504
505 /** Page fault handler */
506 uint8_t faultBlob[] = {
507 0x48,0xa3,0x00,0x61,0x00,
508 0x00,0x00,0xc9,0xff,0xff, // mov %rax, (0xffffc90000005700)
509 0x48,0x83,0xc4,0x08, // add $0x8,%rsp # skip error
510 0x48,0xcf, // iretq
511 };
512
513 physProxy.writeBlob(PFHandlerPhysAddr, faultBlob, sizeof(faultBlob));
514
515 MultiLevelPageTable<PageTableOps> *pt =
516 dynamic_cast<MultiLevelPageTable<PageTableOps> *>(pTable);
517
518 /* Syscall handler */
519 pt->map(syscallCodeVirtAddr, syscallCodePhysAddr, PageBytes, false);
520 /* GDT */
521 pt->map(GDTVirtAddr, GDTPhysAddr, PageBytes, false);
522 /* IDT */
523 pt->map(IDTVirtAddr, IDTPhysAddr, PageBytes, false);
524 /* TSS */
525 pt->map(TSSVirtAddr, TSSPhysAddr, PageBytes, false);
526 /* IST */
527 pt->map(ISTVirtAddr, ISTPhysAddr, PageBytes, false);
528 /* PF handler */
529 pt->map(PFHandlerVirtAddr, PFHandlerPhysAddr, PageBytes, false);
530 /* MMIO region for m5ops */
531 pt->map(MMIORegionVirtAddr, MMIORegionPhysAddr, 16*PageBytes, false);
532 } else {
533 for (int i = 0; i < contextIds.size(); i++) {
534 ThreadContext * tc = system->getThreadContext(contextIds[i]);
535
536 SegAttr dataAttr = 0;
537 dataAttr.dpl = 3;
538 dataAttr.unusable = 0;
539 dataAttr.defaultSize = 1;
540 dataAttr.longMode = 1;
541 dataAttr.avl = 0;
542 dataAttr.granularity = 1;
543 dataAttr.present = 1;
544 dataAttr.type = 3;
545 dataAttr.writable = 1;
546 dataAttr.readable = 1;
547 dataAttr.expandDown = 0;
548 dataAttr.system = 1;
549
550 //Initialize the segment registers.
551 for(int seg = 0; seg < NUM_SEGMENTREGS; seg++) {
552 tc->setMiscRegNoEffect(MISCREG_SEG_BASE(seg), 0);
553 tc->setMiscRegNoEffect(MISCREG_SEG_EFF_BASE(seg), 0);
554 tc->setMiscRegNoEffect(MISCREG_SEG_ATTR(seg), dataAttr);
555 }
556
557 SegAttr csAttr = 0;
558 csAttr.dpl = 3;
559 csAttr.unusable = 0;
560 csAttr.defaultSize = 0;
561 csAttr.longMode = 1;
562 csAttr.avl = 0;
563 csAttr.granularity = 1;
564 csAttr.present = 1;
565 csAttr.type = 10;
566 csAttr.writable = 0;
567 csAttr.readable = 1;
568 csAttr.expandDown = 0;
569 csAttr.system = 1;
570
571 tc->setMiscRegNoEffect(MISCREG_CS_ATTR, csAttr);
572
573 Efer efer = 0;
574 efer.sce = 1; // Enable system call extensions.
575 efer.lme = 1; // Enable long mode.
576 efer.lma = 1; // Activate long mode.
577 efer.nxe = 1; // Enable nx support.
578 efer.svme = 0; // Disable svm support for now. It isn't implemented.
579 efer.ffxsr = 1; // Turn on fast fxsave and fxrstor.
580 tc->setMiscReg(MISCREG_EFER, efer);
581
582 //Set up the registers that describe the operating mode.
583 CR0 cr0 = 0;
584 cr0.pg = 1; // Turn on paging.
585 cr0.cd = 0; // Don't disable caching.
586 cr0.nw = 0; // This is bit is defined to be ignored.
587 cr0.am = 0; // No alignment checking
588 cr0.wp = 0; // Supervisor mode can write read only pages
589 cr0.ne = 1;
590 cr0.et = 1; // This should always be 1
591 cr0.ts = 0; // We don't do task switching, so causing fp exceptions
592 // would be pointless.
593 cr0.em = 0; // Allow x87 instructions to execute natively.
594 cr0.mp = 1; // This doesn't really matter, but the manual suggests
595 // setting it to one.
596 cr0.pe = 1; // We're definitely in protected mode.
597 tc->setMiscReg(MISCREG_CR0, cr0);
598
599 tc->setMiscReg(MISCREG_MXCSR, 0x1f80);
600 }
253 }
254}
255
256void
257I386LiveProcess::initState()
258{
259 X86LiveProcess::initState();
260

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568 int space_needed =
569 info_block_size +
570 aux_data_size +
571 aux_padding +
572 frame_size;
573
574 stack_min = stack_base - space_needed;
575 stack_min = roundDown(stack_min, align);
601 }
602}
603
604void
605I386LiveProcess::initState()
606{
607 X86LiveProcess::initState();
608

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916 int space_needed =
917 info_block_size +
918 aux_data_size +
919 aux_padding +
920 frame_size;
921
922 stack_min = stack_base - space_needed;
923 stack_min = roundDown(stack_min, align);
576 stack_size = stack_base - stack_min;
924 stack_size = roundUp(stack_base - stack_min, pageSize);
577
578 // map memory
925
926 // map memory
579 allocateMem(roundDown(stack_min, pageSize), roundUp(stack_size, pageSize));
927 Addr stack_end = roundDown(stack_base - stack_size, pageSize);
580
928
929 DPRINTF(Stack, "Mapping the stack: 0x%x %dB\n", stack_end, stack_size);
930 allocateMem(stack_end, stack_size);
931
581 // map out initial stack contents
582 IntType sentry_base = stack_base - sentry_size;
583 IntType file_name_base = sentry_base - file_name_size;
584 IntType env_data_base = file_name_base - env_data_size;
585 IntType arg_data_base = env_data_base - arg_data_size;
586 IntType aux_data_base = arg_data_base - info_block_padding - aux_data_size;
587 IntType auxv_array_base = aux_data_base - aux_array_size - aux_padding;
588 IntType envp_array_base = auxv_array_base - envp_array_size;

--- 135 unchanged lines hidden --- 		932 // map out initial stack contents
933 IntType sentry_base = stack_base - sentry_size;
934 IntType file_name_base = sentry_base - file_name_size;
935 IntType env_data_base = file_name_base - env_data_size;
936 IntType arg_data_base = env_data_base - arg_data_size;
937 IntType aux_data_base = arg_data_base - info_block_padding - aux_data_size;
938 IntType auxv_array_base = aux_data_base - aux_array_size - aux_padding;
939 IntType envp_array_base = auxv_array_base - envp_array_size;

--- 135 unchanged lines hidden ---