1/*
2 * Copyright (c) 2014 Advanced Micro Devices, Inc.
3 * Copyright (c) 2007 The Hewlett-Packard Development Company
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2003-2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Gabe Black
42 * Ali Saidi
43 */
44
45#include "arch/x86/process.hh"
46
47#include <string>
48#include <vector>
49
50#include "arch/x86/isa_traits.hh"
51#include "arch/x86/regs/misc.hh"
52#include "arch/x86/regs/segment.hh"
53#include "arch/x86/system.hh"
54#include "arch/x86/types.hh"
55#include "base/loader/elf_object.hh"
56#include "base/loader/object_file.hh"
57#include "base/logging.hh"
58#include "base/trace.hh"
59#include "cpu/thread_context.hh"
60#include "debug/Stack.hh"
61#include "mem/multi_level_page_table.hh"
62#include "mem/page_table.hh"
63#include "params/Process.hh"
64#include "sim/aux_vector.hh"
65#include "sim/process_impl.hh"
66#include "sim/syscall_desc.hh"
67#include "sim/syscall_return.hh"
68#include "sim/system.hh"
69
70using namespace std;
71using namespace X86ISA;
72
73static const int ArgumentReg[] = {
74 INTREG_RDI,
75 INTREG_RSI,
76 INTREG_RDX,
77 // This argument register is r10 for syscalls and rcx for C.
78 INTREG_R10W,
79 // INTREG_RCX,
80 INTREG_R8W,
81 INTREG_R9W
82};
83
84static const int NumArgumentRegs M5_VAR_USED =
85 sizeof(ArgumentReg) / sizeof(const int);
86
87static const int ArgumentReg32[] = {
88 INTREG_EBX,
89 INTREG_ECX,
90 INTREG_EDX,
91 INTREG_ESI,
92 INTREG_EDI,
93 INTREG_EBP
94};
95
96static const int NumArgumentRegs32 M5_VAR_USED =
97 sizeof(ArgumentReg) / sizeof(const int);
98
|
99template class MultiLevelPageTable<LongModePTE<47, 39>,
100 LongModePTE<38, 30>,
101 LongModePTE<29, 21>,
102 LongModePTE<20, 12> >;
103typedef MultiLevelPageTable<LongModePTE<47, 39>,
104 LongModePTE<38, 30>,
105 LongModePTE<29, 21>,
106 LongModePTE<20, 12> > ArchPageTable;
107 |
108X86Process::X86Process(ProcessParams *params, ObjectFile *objFile,
109 SyscallDesc *_syscallDescs, int _numSyscallDescs)
110 : Process(params, params->useArchPT ?
111 static_cast<EmulationPageTable *>(
|
103 new ArchPageTable(
104 params->name, params->pid,
105 params->system, PageBytes,
106 PageTableLayout)) :
|
112 new ArchPageTable(params->name, params->pid,
113 params->system, PageBytes)) : |
114 new EmulationPageTable(params->name, params->pid,
115 PageBytes),
116 objFile),
117 syscallDescs(_syscallDescs), numSyscallDescs(_numSyscallDescs)
118{
119}
120
121void X86Process::clone(ThreadContext *old_tc, ThreadContext *new_tc,
122 Process *p, TheISA::IntReg flags)
123{
124 Process::clone(old_tc, new_tc, p, flags);
125 X86Process *process = (X86Process*)p;
126 *process = *this;
127}
128
129X86_64Process::X86_64Process(ProcessParams *params, ObjectFile *objFile,
130 SyscallDesc *_syscallDescs, int _numSyscallDescs)
131 : X86Process(params, objFile, _syscallDescs, _numSyscallDescs)
132{
133
134 vsyscallPage.base = 0xffffffffff600000ULL;
135 vsyscallPage.size = PageBytes;
136 vsyscallPage.vtimeOffset = 0x400;
137 vsyscallPage.vgettimeofdayOffset = 0x0;
138
139 Addr brk_point = roundUp(objFile->dataBase() + objFile->dataSize() +
140 objFile->bssSize(), PageBytes);
141 Addr stack_base = 0x7FFFFFFFF000ULL;
142 Addr max_stack_size = 8 * 1024 * 1024;
143 Addr next_thread_stack_base = stack_base - max_stack_size;
144 Addr mmap_end = 0x7FFFF7FFF000ULL;
145
146 memState = make_shared<MemState>(brk_point, stack_base, max_stack_size,
147 next_thread_stack_base, mmap_end);
148}
149
150void
151I386Process::syscall(int64_t callnum, ThreadContext *tc, Fault *fault)
152{
153 TheISA::PCState pc = tc->pcState();
154 Addr eip = pc.pc();
155 if (eip >= vsyscallPage.base &&
156 eip < vsyscallPage.base + vsyscallPage.size) {
157 pc.npc(vsyscallPage.base + vsyscallPage.vsysexitOffset);
158 tc->pcState(pc);
159 }
160 X86Process::syscall(callnum, tc, fault);
161}
162
163
164I386Process::I386Process(ProcessParams *params, ObjectFile *objFile,
165 SyscallDesc *_syscallDescs, int _numSyscallDescs)
166 : X86Process(params, objFile, _syscallDescs, _numSyscallDescs)
167{
168 _gdtStart = ULL(0xffffd000);
169 _gdtSize = PageBytes;
170
171 vsyscallPage.base = 0xffffe000ULL;
172 vsyscallPage.size = PageBytes;
173 vsyscallPage.vsyscallOffset = 0x400;
174 vsyscallPage.vsysexitOffset = 0x410;
175
176 Addr brk_point = roundUp(objFile->dataBase() + objFile->dataSize() +
177 objFile->bssSize(), PageBytes);
178 Addr stack_base = _gdtStart;
179 Addr max_stack_size = 8 * 1024 * 1024;
180 Addr next_thread_stack_base = stack_base - max_stack_size;
181 Addr mmap_end = 0xB7FFF000ULL;
182
183 memState = make_shared<MemState>(brk_point, stack_base, max_stack_size,
184 next_thread_stack_base, mmap_end);
185}
186
187SyscallDesc*
188X86Process::getDesc(int callnum)
189{
190 if (callnum < 0 || callnum >= numSyscallDescs)
191 return NULL;
192 return &syscallDescs[callnum];
193}
194
195void
196X86_64Process::initState()
197{
198 X86Process::initState();
199
200 argsInit(PageBytes);
201
202 // Set up the vsyscall page for this process.
203 allocateMem(vsyscallPage.base, vsyscallPage.size);
204 uint8_t vtimeBlob[] = {
205 0x48,0xc7,0xc0,0xc9,0x00,0x00,0x00, // mov $0xc9,%rax
206 0x0f,0x05, // syscall
207 0xc3 // retq
208 };
209 initVirtMem.writeBlob(vsyscallPage.base + vsyscallPage.vtimeOffset,
210 vtimeBlob, sizeof(vtimeBlob));
211
212 uint8_t vgettimeofdayBlob[] = {
213 0x48,0xc7,0xc0,0x60,0x00,0x00,0x00, // mov $0x60,%rax
214 0x0f,0x05, // syscall
215 0xc3 // retq
216 };
217 initVirtMem.writeBlob(vsyscallPage.base + vsyscallPage.vgettimeofdayOffset,
218 vgettimeofdayBlob, sizeof(vgettimeofdayBlob));
219
220 if (kvmInSE) {
221 PortProxy physProxy = system->physProxy;
222
223 Addr syscallCodePhysAddr = system->allocPhysPages(1);
224 Addr gdtPhysAddr = system->allocPhysPages(1);
225 Addr idtPhysAddr = system->allocPhysPages(1);
226 Addr istPhysAddr = system->allocPhysPages(1);
227 Addr tssPhysAddr = system->allocPhysPages(1);
228 Addr pfHandlerPhysAddr = system->allocPhysPages(1);
229
230 /*
231 * Set up the gdt.
232 */
233 uint8_t numGDTEntries = 0;
234 uint64_t nullDescriptor = 0;
235 physProxy.writeBlob(gdtPhysAddr + numGDTEntries * 8,
236 (uint8_t *)(&nullDescriptor), 8);
237 numGDTEntries++;
238
239 SegDescriptor initDesc = 0;
240 initDesc.type.codeOrData = 0; // code or data type
241 initDesc.type.c = 0; // conforming
242 initDesc.type.r = 1; // readable
243 initDesc.dpl = 0; // privilege
244 initDesc.p = 1; // present
245 initDesc.l = 1; // longmode - 64 bit
246 initDesc.d = 0; // operand size
247 initDesc.g = 1; // granularity
248 initDesc.s = 1; // system segment
249 initDesc.limitHigh = 0xFFFF;
250 initDesc.limitLow = 0xF;
251 initDesc.baseHigh = 0x0;
252 initDesc.baseLow = 0x0;
253
254 //64 bit code segment
255 SegDescriptor csLowPLDesc = initDesc;
256 csLowPLDesc.type.codeOrData = 1;
257 csLowPLDesc.dpl = 0;
258 uint64_t csLowPLDescVal = csLowPLDesc;
259 physProxy.writeBlob(gdtPhysAddr + numGDTEntries * 8,
260 (uint8_t *)(&csLowPLDescVal), 8);
261
262 numGDTEntries++;
263
264 SegSelector csLowPL = 0;
265 csLowPL.si = numGDTEntries - 1;
266 csLowPL.rpl = 0;
267
268 //64 bit data segment
269 SegDescriptor dsLowPLDesc = initDesc;
270 dsLowPLDesc.type.codeOrData = 0;
271 dsLowPLDesc.dpl = 0;
272 uint64_t dsLowPLDescVal = dsLowPLDesc;
273 physProxy.writeBlob(gdtPhysAddr + numGDTEntries * 8,
274 (uint8_t *)(&dsLowPLDescVal), 8);
275
276 numGDTEntries++;
277
278 SegSelector dsLowPL = 0;
279 dsLowPL.si = numGDTEntries - 1;
280 dsLowPL.rpl = 0;
281
282 //64 bit data segment
283 SegDescriptor dsDesc = initDesc;
284 dsDesc.type.codeOrData = 0;
285 dsDesc.dpl = 3;
286 uint64_t dsDescVal = dsDesc;
287 physProxy.writeBlob(gdtPhysAddr + numGDTEntries * 8,
288 (uint8_t *)(&dsDescVal), 8);
289
290 numGDTEntries++;
291
292 SegSelector ds = 0;
293 ds.si = numGDTEntries - 1;
294 ds.rpl = 3;
295
296 //64 bit code segment
297 SegDescriptor csDesc = initDesc;
298 csDesc.type.codeOrData = 1;
299 csDesc.dpl = 3;
300 uint64_t csDescVal = csDesc;
301 physProxy.writeBlob(gdtPhysAddr + numGDTEntries * 8,
302 (uint8_t *)(&csDescVal), 8);
303
304 numGDTEntries++;
305
306 SegSelector cs = 0;
307 cs.si = numGDTEntries - 1;
308 cs.rpl = 3;
309
310 SegSelector scall = 0;
311 scall.si = csLowPL.si;
312 scall.rpl = 0;
313
314 SegSelector sret = 0;
315 sret.si = dsLowPL.si;
316 sret.rpl = 3;
317
318 /* In long mode the TSS has been extended to 16 Bytes */
319 TSSlow TSSDescLow = 0;
320 TSSDescLow.type = 0xB;
321 TSSDescLow.dpl = 0; // Privelege level 0
322 TSSDescLow.p = 1; // Present
323 TSSDescLow.g = 1; // Page granularity
324 TSSDescLow.limitHigh = 0xF;
325 TSSDescLow.limitLow = 0xFFFF;
326 TSSDescLow.baseLow = bits(TSSVirtAddr, 23, 0);
327 TSSDescLow.baseHigh = bits(TSSVirtAddr, 31, 24);
328
329 TSShigh TSSDescHigh = 0;
330 TSSDescHigh.base = bits(TSSVirtAddr, 63, 32);
331
332 struct TSSDesc {
333 uint64_t low;
334 uint64_t high;
335 } tssDescVal = {TSSDescLow, TSSDescHigh};
336
337 physProxy.writeBlob(gdtPhysAddr + numGDTEntries * 8,
338 (uint8_t *)(&tssDescVal), sizeof(tssDescVal));
339
340 numGDTEntries++;
341
342 SegSelector tssSel = 0;
343 tssSel.si = numGDTEntries - 1;
344
345 uint64_t tss_base_addr = (TSSDescHigh.base << 32) |
346 (TSSDescLow.baseHigh << 24) |
347 TSSDescLow.baseLow;
348 uint64_t tss_limit = TSSDescLow.limitLow | (TSSDescLow.limitHigh << 16);
349
350 SegAttr tss_attr = 0;
351
352 tss_attr.type = TSSDescLow.type;
353 tss_attr.dpl = TSSDescLow.dpl;
354 tss_attr.present = TSSDescLow.p;
355 tss_attr.granularity = TSSDescLow.g;
356 tss_attr.unusable = 0;
357
358 for (int i = 0; i < contextIds.size(); i++) {
359 ThreadContext * tc = system->getThreadContext(contextIds[i]);
360
361 tc->setMiscReg(MISCREG_CS, cs);
362 tc->setMiscReg(MISCREG_DS, ds);
363 tc->setMiscReg(MISCREG_ES, ds);
364 tc->setMiscReg(MISCREG_FS, ds);
365 tc->setMiscReg(MISCREG_GS, ds);
366 tc->setMiscReg(MISCREG_SS, ds);
367
368 // LDT
369 tc->setMiscReg(MISCREG_TSL, 0);
370 SegAttr tslAttr = 0;
371 tslAttr.present = 1;
372 tslAttr.type = 2;
373 tc->setMiscReg(MISCREG_TSL_ATTR, tslAttr);
374
375 tc->setMiscReg(MISCREG_TSG_BASE, GDTVirtAddr);
376 tc->setMiscReg(MISCREG_TSG_LIMIT, 8 * numGDTEntries - 1);
377
378 tc->setMiscReg(MISCREG_TR, tssSel);
379 tc->setMiscReg(MISCREG_TR_BASE, tss_base_addr);
380 tc->setMiscReg(MISCREG_TR_EFF_BASE, 0);
381 tc->setMiscReg(MISCREG_TR_LIMIT, tss_limit);
382 tc->setMiscReg(MISCREG_TR_ATTR, tss_attr);
383
384 //Start using longmode segments.
385 installSegDesc(tc, SEGMENT_REG_CS, csDesc, true);
386 installSegDesc(tc, SEGMENT_REG_DS, dsDesc, true);
387 installSegDesc(tc, SEGMENT_REG_ES, dsDesc, true);
388 installSegDesc(tc, SEGMENT_REG_FS, dsDesc, true);
389 installSegDesc(tc, SEGMENT_REG_GS, dsDesc, true);
390 installSegDesc(tc, SEGMENT_REG_SS, dsDesc, true);
391
392 Efer efer = 0;
393 efer.sce = 1; // Enable system call extensions.
394 efer.lme = 1; // Enable long mode.
395 efer.lma = 1; // Activate long mode.
396 efer.nxe = 0; // Enable nx support.
397 efer.svme = 1; // Enable svm support for now.
398 efer.ffxsr = 0; // Turn on fast fxsave and fxrstor.
399 tc->setMiscReg(MISCREG_EFER, efer);
400
401 //Set up the registers that describe the operating mode.
402 CR0 cr0 = 0;
403 cr0.pg = 1; // Turn on paging.
404 cr0.cd = 0; // Don't disable caching.
405 cr0.nw = 0; // This is bit is defined to be ignored.
406 cr0.am = 1; // No alignment checking
407 cr0.wp = 1; // Supervisor mode can write read only pages
408 cr0.ne = 1;
409 cr0.et = 1; // This should always be 1
410 cr0.ts = 0; // We don't do task switching, so causing fp exceptions
411 // would be pointless.
412 cr0.em = 0; // Allow x87 instructions to execute natively.
413 cr0.mp = 1; // This doesn't really matter, but the manual suggests
414 // setting it to one.
415 cr0.pe = 1; // We're definitely in protected mode.
416 tc->setMiscReg(MISCREG_CR0, cr0);
417
418 CR0 cr2 = 0;
419 tc->setMiscReg(MISCREG_CR2, cr2);
420
421 CR3 cr3 = dynamic_cast<ArchPageTable *>(pTable)->basePtr();
422 tc->setMiscReg(MISCREG_CR3, cr3);
423
424 CR4 cr4 = 0;
425 //Turn on pae.
426 cr4.osxsave = 1; // Enable XSAVE and Proc Extended States
427 cr4.osxmmexcpt = 1; // Operating System Unmasked Exception
428 cr4.osfxsr = 1; // Operating System FXSave/FSRSTOR Support
429 cr4.pce = 0; // Performance-Monitoring Counter Enable
430 cr4.pge = 0; // Page-Global Enable
431 cr4.mce = 0; // Machine Check Enable
432 cr4.pae = 1; // Physical-Address Extension
433 cr4.pse = 0; // Page Size Extensions
434 cr4.de = 0; // Debugging Extensions
435 cr4.tsd = 0; // Time Stamp Disable
436 cr4.pvi = 0; // Protected-Mode Virtual Interrupts
437 cr4.vme = 0; // Virtual-8086 Mode Extensions
438
439 tc->setMiscReg(MISCREG_CR4, cr4);
440
441 CR4 cr8 = 0;
442 tc->setMiscReg(MISCREG_CR8, cr8);
443
444 tc->setMiscReg(MISCREG_MXCSR, 0x1f80);
445
446 tc->setMiscReg(MISCREG_APIC_BASE, 0xfee00900);
447
448 tc->setMiscReg(MISCREG_TSG_BASE, GDTVirtAddr);
449 tc->setMiscReg(MISCREG_TSG_LIMIT, 0xffff);
450
451 tc->setMiscReg(MISCREG_IDTR_BASE, IDTVirtAddr);
452 tc->setMiscReg(MISCREG_IDTR_LIMIT, 0xffff);
453
454 /* enabling syscall and sysret */
455 MiscReg star = ((MiscReg)sret << 48) | ((MiscReg)scall << 32);
456 tc->setMiscReg(MISCREG_STAR, star);
457 MiscReg lstar = (MiscReg)syscallCodeVirtAddr;
458 tc->setMiscReg(MISCREG_LSTAR, lstar);
459 MiscReg sfmask = (1 << 8) | (1 << 10); // TF | DF
460 tc->setMiscReg(MISCREG_SF_MASK, sfmask);
461 }
462
463 /* Set up the content of the TSS and write it to physical memory. */
464
465 struct {
466 uint32_t reserved0; // +00h
467 uint32_t RSP0_low; // +04h
468 uint32_t RSP0_high; // +08h
469 uint32_t RSP1_low; // +0Ch
470 uint32_t RSP1_high; // +10h
471 uint32_t RSP2_low; // +14h
472 uint32_t RSP2_high; // +18h
473 uint32_t reserved1; // +1Ch
474 uint32_t reserved2; // +20h
475 uint32_t IST1_low; // +24h
476 uint32_t IST1_high; // +28h
477 uint32_t IST2_low; // +2Ch
478 uint32_t IST2_high; // +30h
479 uint32_t IST3_low; // +34h
480 uint32_t IST3_high; // +38h
481 uint32_t IST4_low; // +3Ch
482 uint32_t IST4_high; // +40h
483 uint32_t IST5_low; // +44h
484 uint32_t IST5_high; // +48h
485 uint32_t IST6_low; // +4Ch
486 uint32_t IST6_high; // +50h
487 uint32_t IST7_low; // +54h
488 uint32_t IST7_high; // +58h
489 uint32_t reserved3; // +5Ch
490 uint32_t reserved4; // +60h
491 uint16_t reserved5; // +64h
492 uint16_t IO_MapBase; // +66h
493 } tss;
494
495 /** setting Interrupt Stack Table */
496 uint64_t IST_start = ISTVirtAddr + PageBytes;
497 tss.IST1_low = IST_start;
498 tss.IST1_high = IST_start >> 32;
499 tss.RSP0_low = tss.IST1_low;
500 tss.RSP0_high = tss.IST1_high;
501 tss.RSP1_low = tss.IST1_low;
502 tss.RSP1_high = tss.IST1_high;
503 tss.RSP2_low = tss.IST1_low;
504 tss.RSP2_high = tss.IST1_high;
505 physProxy.writeBlob(tssPhysAddr, (uint8_t *)(&tss), sizeof(tss));
506
507 /* Setting IDT gates */
508 GateDescriptorLow PFGateLow = 0;
509 PFGateLow.offsetHigh = bits(PFHandlerVirtAddr, 31, 16);
510 PFGateLow.offsetLow = bits(PFHandlerVirtAddr, 15, 0);
511 PFGateLow.selector = csLowPL;
512 PFGateLow.p = 1;
513 PFGateLow.dpl = 0;
514 PFGateLow.type = 0xe; // gate interrupt type
515 PFGateLow.IST = 0; // setting IST to 0 and using RSP0
516
517 GateDescriptorHigh PFGateHigh = 0;
518 PFGateHigh.offset = bits(PFHandlerVirtAddr, 63, 32);
519
520 struct {
521 uint64_t low;
522 uint64_t high;
523 } PFGate = {PFGateLow, PFGateHigh};
524
525 physProxy.writeBlob(idtPhysAddr + 0xE0,
526 (uint8_t *)(&PFGate), sizeof(PFGate));
527
528 /* System call handler */
529 uint8_t syscallBlob[] = {
530 // mov %rax, (0xffffc90000005600)
531 0x48, 0xa3, 0x00, 0x60, 0x00,
532 0x00, 0x00, 0xc9, 0xff, 0xff,
533 // sysret
534 0x48, 0x0f, 0x07
535 };
536
537 physProxy.writeBlob(syscallCodePhysAddr,
538 syscallBlob, sizeof(syscallBlob));
539
540 /** Page fault handler */
541 uint8_t faultBlob[] = {
542 // mov %rax, (0xffffc90000005700)
543 0x48, 0xa3, 0x00, 0x61, 0x00,
544 0x00, 0x00, 0xc9, 0xff, 0xff,
545 // add $0x8, %rsp # skip error
546 0x48, 0x83, 0xc4, 0x08,
547 // iretq
548 0x48, 0xcf
549 };
550
551 physProxy.writeBlob(pfHandlerPhysAddr, faultBlob, sizeof(faultBlob));
552
|
546 MultiLevelPageTable<PageTableOps> *pt =
547 dynamic_cast<MultiLevelPageTable<PageTableOps> *>(pTable);
548
|
553 /* Syscall handler */
|
550 pt->map(syscallCodeVirtAddr, syscallCodePhysAddr, PageBytes, false);
|
554 pTable->map(syscallCodeVirtAddr, syscallCodePhysAddr,
555 PageBytes, false); |
556 /* GDT */
|
552 pt->map(GDTVirtAddr, gdtPhysAddr, PageBytes, false);
|
| 557 pTable->map(GDTVirtAddr, gdtPhysAddr, PageBytes, false); |
558 /* IDT */
|
554 pt->map(IDTVirtAddr, idtPhysAddr, PageBytes, false);
|
| 559 pTable->map(IDTVirtAddr, idtPhysAddr, PageBytes, false); |
560 /* TSS */
|
556 pt->map(TSSVirtAddr, tssPhysAddr, PageBytes, false);
|
| 561 pTable->map(TSSVirtAddr, tssPhysAddr, PageBytes, false); |
562 /* IST */
|
558 pt->map(ISTVirtAddr, istPhysAddr, PageBytes, false);
|
| 563 pTable->map(ISTVirtAddr, istPhysAddr, PageBytes, false); |
564 /* PF handler */
|
560 pt->map(PFHandlerVirtAddr, pfHandlerPhysAddr, PageBytes, false);
|
| 565 pTable->map(PFHandlerVirtAddr, pfHandlerPhysAddr, PageBytes, false); |
566 /* MMIO region for m5ops */
|
562 pt->map(MMIORegionVirtAddr, MMIORegionPhysAddr, 16*PageBytes, false);
|
567 pTable->map(MMIORegionVirtAddr, MMIORegionPhysAddr,
568 16 * PageBytes, false); |
569 } else {
570 for (int i = 0; i < contextIds.size(); i++) {
571 ThreadContext * tc = system->getThreadContext(contextIds[i]);
572
573 SegAttr dataAttr = 0;
574 dataAttr.dpl = 3;
575 dataAttr.unusable = 0;
576 dataAttr.defaultSize = 1;
577 dataAttr.longMode = 1;
578 dataAttr.avl = 0;
579 dataAttr.granularity = 1;
580 dataAttr.present = 1;
581 dataAttr.type = 3;
582 dataAttr.writable = 1;
583 dataAttr.readable = 1;
584 dataAttr.expandDown = 0;
585 dataAttr.system = 1;
586
587 // Initialize the segment registers.
588 for (int seg = 0; seg < NUM_SEGMENTREGS; seg++) {
589 tc->setMiscRegNoEffect(MISCREG_SEG_BASE(seg), 0);
590 tc->setMiscRegNoEffect(MISCREG_SEG_EFF_BASE(seg), 0);
591 tc->setMiscRegNoEffect(MISCREG_SEG_ATTR(seg), dataAttr);
592 }
593
594 SegAttr csAttr = 0;
595 csAttr.dpl = 3;
596 csAttr.unusable = 0;
597 csAttr.defaultSize = 0;
598 csAttr.longMode = 1;
599 csAttr.avl = 0;
600 csAttr.granularity = 1;
601 csAttr.present = 1;
602 csAttr.type = 10;
603 csAttr.writable = 0;
604 csAttr.readable = 1;
605 csAttr.expandDown = 0;
606 csAttr.system = 1;
607
608 tc->setMiscRegNoEffect(MISCREG_CS_ATTR, csAttr);
609
610 Efer efer = 0;
611 efer.sce = 1; // Enable system call extensions.
612 efer.lme = 1; // Enable long mode.
613 efer.lma = 1; // Activate long mode.
614 efer.nxe = 1; // Enable nx support.
615 efer.svme = 0; // Disable svm support for now. It isn't implemented.
616 efer.ffxsr = 1; // Turn on fast fxsave and fxrstor.
617 tc->setMiscReg(MISCREG_EFER, efer);
618
619 // Set up the registers that describe the operating mode.
620 CR0 cr0 = 0;
621 cr0.pg = 1; // Turn on paging.
622 cr0.cd = 0; // Don't disable caching.
623 cr0.nw = 0; // This is bit is defined to be ignored.
624 cr0.am = 0; // No alignment checking
625 cr0.wp = 0; // Supervisor mode can write read only pages
626 cr0.ne = 1;
627 cr0.et = 1; // This should always be 1
628 cr0.ts = 0; // We don't do task switching, so causing fp exceptions
629 // would be pointless.
630 cr0.em = 0; // Allow x87 instructions to execute natively.
631 cr0.mp = 1; // This doesn't really matter, but the manual suggests
632 // setting it to one.
633 cr0.pe = 1; // We're definitely in protected mode.
634 tc->setMiscReg(MISCREG_CR0, cr0);
635
636 tc->setMiscReg(MISCREG_MXCSR, 0x1f80);
637 }
638 }
639}
640
641void
642I386Process::initState()
643{
644 X86Process::initState();
645
646 argsInit(PageBytes);
647
648 /*
649 * Set up a GDT for this process. The whole GDT wouldn't really be for
650 * this process, but the only parts we care about are.
651 */
652 allocateMem(_gdtStart, _gdtSize);
653 uint64_t zero = 0;
654 assert(_gdtSize % sizeof(zero) == 0);
655 for (Addr gdtCurrent = _gdtStart;
656 gdtCurrent < _gdtStart + _gdtSize; gdtCurrent += sizeof(zero)) {
657 initVirtMem.write(gdtCurrent, zero);
658 }
659
660 // Set up the vsyscall page for this process.
661 allocateMem(vsyscallPage.base, vsyscallPage.size);
662 uint8_t vsyscallBlob[] = {
663 0x51, // push %ecx
664 0x52, // push %edp
665 0x55, // push %ebp
666 0x89, 0xe5, // mov %esp, %ebp
667 0x0f, 0x34 // sysenter
668 };
669 initVirtMem.writeBlob(vsyscallPage.base + vsyscallPage.vsyscallOffset,
670 vsyscallBlob, sizeof(vsyscallBlob));
671
672 uint8_t vsysexitBlob[] = {
673 0x5d, // pop %ebp
674 0x5a, // pop %edx
675 0x59, // pop %ecx
676 0xc3 // ret
677 };
678 initVirtMem.writeBlob(vsyscallPage.base + vsyscallPage.vsysexitOffset,
679 vsysexitBlob, sizeof(vsysexitBlob));
680
681 for (int i = 0; i < contextIds.size(); i++) {
682 ThreadContext * tc = system->getThreadContext(contextIds[i]);
683
684 SegAttr dataAttr = 0;
685 dataAttr.dpl = 3;
686 dataAttr.unusable = 0;
687 dataAttr.defaultSize = 1;
688 dataAttr.longMode = 0;
689 dataAttr.avl = 0;
690 dataAttr.granularity = 1;
691 dataAttr.present = 1;
692 dataAttr.type = 3;
693 dataAttr.writable = 1;
694 dataAttr.readable = 1;
695 dataAttr.expandDown = 0;
696 dataAttr.system = 1;
697
698 // Initialize the segment registers.
699 for (int seg = 0; seg < NUM_SEGMENTREGS; seg++) {
700 tc->setMiscRegNoEffect(MISCREG_SEG_BASE(seg), 0);
701 tc->setMiscRegNoEffect(MISCREG_SEG_EFF_BASE(seg), 0);
702 tc->setMiscRegNoEffect(MISCREG_SEG_ATTR(seg), dataAttr);
703 tc->setMiscRegNoEffect(MISCREG_SEG_SEL(seg), 0xB);
704 tc->setMiscRegNoEffect(MISCREG_SEG_LIMIT(seg), (uint32_t)(-1));
705 }
706
707 SegAttr csAttr = 0;
708 csAttr.dpl = 3;
709 csAttr.unusable = 0;
710 csAttr.defaultSize = 1;
711 csAttr.longMode = 0;
712 csAttr.avl = 0;
713 csAttr.granularity = 1;
714 csAttr.present = 1;
715 csAttr.type = 0xa;
716 csAttr.writable = 0;
717 csAttr.readable = 1;
718 csAttr.expandDown = 0;
719 csAttr.system = 1;
720
721 tc->setMiscRegNoEffect(MISCREG_CS_ATTR, csAttr);
722
723 tc->setMiscRegNoEffect(MISCREG_TSG_BASE, _gdtStart);
724 tc->setMiscRegNoEffect(MISCREG_TSG_EFF_BASE, _gdtStart);
725 tc->setMiscRegNoEffect(MISCREG_TSG_LIMIT, _gdtStart + _gdtSize - 1);
726
727 // Set the LDT selector to 0 to deactivate it.
728 tc->setMiscRegNoEffect(MISCREG_TSL, 0);
729
730 Efer efer = 0;
731 efer.sce = 1; // Enable system call extensions.
732 efer.lme = 1; // Enable long mode.
733 efer.lma = 0; // Deactivate long mode.
734 efer.nxe = 1; // Enable nx support.
735 efer.svme = 0; // Disable svm support for now. It isn't implemented.
736 efer.ffxsr = 1; // Turn on fast fxsave and fxrstor.
737 tc->setMiscReg(MISCREG_EFER, efer);
738
739 // Set up the registers that describe the operating mode.
740 CR0 cr0 = 0;
741 cr0.pg = 1; // Turn on paging.
742 cr0.cd = 0; // Don't disable caching.
743 cr0.nw = 0; // This is bit is defined to be ignored.
744 cr0.am = 0; // No alignment checking
745 cr0.wp = 0; // Supervisor mode can write read only pages
746 cr0.ne = 1;
747 cr0.et = 1; // This should always be 1
748 cr0.ts = 0; // We don't do task switching, so causing fp exceptions
749 // would be pointless.
750 cr0.em = 0; // Allow x87 instructions to execute natively.
751 cr0.mp = 1; // This doesn't really matter, but the manual suggests
752 // setting it to one.
753 cr0.pe = 1; // We're definitely in protected mode.
754 tc->setMiscReg(MISCREG_CR0, cr0);
755
756 tc->setMiscReg(MISCREG_MXCSR, 0x1f80);
757 }
758}
759
760template<class IntType>
761void
762X86Process::argsInit(int pageSize,
763 std::vector<AuxVector<IntType> > extraAuxvs)
764{
765 int intSize = sizeof(IntType);
766
767 typedef AuxVector<IntType> auxv_t;
768 std::vector<auxv_t> auxv = extraAuxvs;
769
770 string filename;
771 if (argv.size() < 1)
772 filename = "";
773 else
774 filename = argv[0];
775
776 // We want 16 byte alignment
777 uint64_t align = 16;
778
779 // Patch the ld_bias for dynamic executables.
780 updateBias();
781
782 // load object file into target memory
783 objFile->loadSections(initVirtMem);
784
785 enum X86CpuFeature {
786 X86_OnboardFPU = 1 << 0,
787 X86_VirtualModeExtensions = 1 << 1,
788 X86_DebuggingExtensions = 1 << 2,
789 X86_PageSizeExtensions = 1 << 3,
790
791 X86_TimeStampCounter = 1 << 4,
792 X86_ModelSpecificRegisters = 1 << 5,
793 X86_PhysicalAddressExtensions = 1 << 6,
794 X86_MachineCheckExtensions = 1 << 7,
795
796 X86_CMPXCHG8Instruction = 1 << 8,
797 X86_OnboardAPIC = 1 << 9,
798 X86_SYSENTER_SYSEXIT = 1 << 11,
799
800 X86_MemoryTypeRangeRegisters = 1 << 12,
801 X86_PageGlobalEnable = 1 << 13,
802 X86_MachineCheckArchitecture = 1 << 14,
803 X86_CMOVInstruction = 1 << 15,
804
805 X86_PageAttributeTable = 1 << 16,
806 X86_36BitPSEs = 1 << 17,
807 X86_ProcessorSerialNumber = 1 << 18,
808 X86_CLFLUSHInstruction = 1 << 19,
809
810 X86_DebugTraceStore = 1 << 21,
811 X86_ACPIViaMSR = 1 << 22,
812 X86_MultimediaExtensions = 1 << 23,
813
814 X86_FXSAVE_FXRSTOR = 1 << 24,
815 X86_StreamingSIMDExtensions = 1 << 25,
816 X86_StreamingSIMDExtensions2 = 1 << 26,
817 X86_CPUSelfSnoop = 1 << 27,
818
819 X86_HyperThreading = 1 << 28,
820 X86_AutomaticClockControl = 1 << 29,
821 X86_IA64Processor = 1 << 30
822 };
823
824 // Setup the auxiliary vectors. These will already have endian
825 // conversion. Auxiliary vectors are loaded only for elf formatted
826 // executables; the auxv is responsible for passing information from
827 // the OS to the interpreter.
828 ElfObject * elfObject = dynamic_cast<ElfObject *>(objFile);
829 if (elfObject) {
830 uint64_t features =
831 X86_OnboardFPU |
832 X86_VirtualModeExtensions |
833 X86_DebuggingExtensions |
834 X86_PageSizeExtensions |
835 X86_TimeStampCounter |
836 X86_ModelSpecificRegisters |
837 X86_PhysicalAddressExtensions |
838 X86_MachineCheckExtensions |
839 X86_CMPXCHG8Instruction |
840 X86_OnboardAPIC |
841 X86_SYSENTER_SYSEXIT |
842 X86_MemoryTypeRangeRegisters |
843 X86_PageGlobalEnable |
844 X86_MachineCheckArchitecture |
845 X86_CMOVInstruction |
846 X86_PageAttributeTable |
847 X86_36BitPSEs |
848// X86_ProcessorSerialNumber |
849 X86_CLFLUSHInstruction |
850// X86_DebugTraceStore |
851// X86_ACPIViaMSR |
852 X86_MultimediaExtensions |
853 X86_FXSAVE_FXRSTOR |
854 X86_StreamingSIMDExtensions |
855 X86_StreamingSIMDExtensions2 |
856// X86_CPUSelfSnoop |
857// X86_HyperThreading |
858// X86_AutomaticClockControl |
859// X86_IA64Processor |
860 0;
861
862 // Bits which describe the system hardware capabilities
863 // XXX Figure out what these should be
864 auxv.push_back(auxv_t(M5_AT_HWCAP, features));
865 // The system page size
866 auxv.push_back(auxv_t(M5_AT_PAGESZ, X86ISA::PageBytes));
867 // Frequency at which times() increments
868 // Defined to be 100 in the kernel source.
869 auxv.push_back(auxv_t(M5_AT_CLKTCK, 100));
870 // This is the virtual address of the program header tables if they
871 // appear in the executable image.
872 auxv.push_back(auxv_t(M5_AT_PHDR, elfObject->programHeaderTable()));
873 // This is the size of a program header entry from the elf file.
874 auxv.push_back(auxv_t(M5_AT_PHENT, elfObject->programHeaderSize()));
875 // This is the number of program headers from the original elf file.
876 auxv.push_back(auxv_t(M5_AT_PHNUM, elfObject->programHeaderCount()));
877 // This is the base address of the ELF interpreter; it should be
878 // zero for static executables or contain the base address for
879 // dynamic executables.
880 auxv.push_back(auxv_t(M5_AT_BASE, getBias()));
881 // XXX Figure out what this should be.
882 auxv.push_back(auxv_t(M5_AT_FLAGS, 0));
883 // The entry point to the program
884 auxv.push_back(auxv_t(M5_AT_ENTRY, objFile->entryPoint()));
885 // Different user and group IDs
886 auxv.push_back(auxv_t(M5_AT_UID, uid()));
887 auxv.push_back(auxv_t(M5_AT_EUID, euid()));
888 auxv.push_back(auxv_t(M5_AT_GID, gid()));
889 auxv.push_back(auxv_t(M5_AT_EGID, egid()));
890 // Whether to enable "secure mode" in the executable
891 auxv.push_back(auxv_t(M5_AT_SECURE, 0));
892 // The address of 16 "random" bytes.
893 auxv.push_back(auxv_t(M5_AT_RANDOM, 0));
894 // The name of the program
895 auxv.push_back(auxv_t(M5_AT_EXECFN, 0));
896 // The platform string
897 auxv.push_back(auxv_t(M5_AT_PLATFORM, 0));
898 }
899
900 // Figure out how big the initial stack needs to be
901
902 // A sentry NULL void pointer at the top of the stack.
903 int sentry_size = intSize;
904
905 // This is the name of the file which is present on the initial stack
906 // It's purpose is to let the user space linker examine the original file.
907 int file_name_size = filename.size() + 1;
908
909 const int numRandomBytes = 16;
910 int aux_data_size = numRandomBytes;
911
912 string platform = "x86_64";
913 aux_data_size += platform.size() + 1;
914
915 int env_data_size = 0;
916 for (int i = 0; i < envp.size(); ++i)
917 env_data_size += envp[i].size() + 1;
918 int arg_data_size = 0;
919 for (int i = 0; i < argv.size(); ++i)
920 arg_data_size += argv[i].size() + 1;
921
922 // The info_block needs to be padded so its size is a multiple of the
923 // alignment mask. Also, it appears that there needs to be at least some
924 // padding, so if the size is already a multiple, we need to increase it
925 // anyway.
926 int base_info_block_size =
927 sentry_size + file_name_size + env_data_size + arg_data_size;
928
929 int info_block_size = roundUp(base_info_block_size, align);
930
931 int info_block_padding = info_block_size - base_info_block_size;
932
933 // Each auxiliary vector is two 8 byte words
934 int aux_array_size = intSize * 2 * (auxv.size() + 1);
935
936 int envp_array_size = intSize * (envp.size() + 1);
937 int argv_array_size = intSize * (argv.size() + 1);
938
939 int argc_size = intSize;
940
941 // Figure out the size of the contents of the actual initial frame
942 int frame_size =
943 aux_array_size +
944 envp_array_size +
945 argv_array_size +
946 argc_size;
947
948 // There needs to be padding after the auxiliary vector data so that the
949 // very bottom of the stack is aligned properly.
950 int partial_size = frame_size + aux_data_size;
951 int aligned_partial_size = roundUp(partial_size, align);
952 int aux_padding = aligned_partial_size - partial_size;
953
954 int space_needed =
955 info_block_size +
956 aux_data_size +
957 aux_padding +
958 frame_size;
959
960 Addr stack_base = memState->getStackBase();
961
962 Addr stack_min = stack_base - space_needed;
963 stack_min = roundDown(stack_min, align);
964
965 unsigned stack_size = stack_base - stack_min;
966 stack_size = roundUp(stack_size, pageSize);
967 memState->setStackSize(stack_size);
968
969 // map memory
970 Addr stack_end = roundDown(stack_base - stack_size, pageSize);
971
972 DPRINTF(Stack, "Mapping the stack: 0x%x %dB\n", stack_end, stack_size);
973 allocateMem(stack_end, stack_size);
974
975 // map out initial stack contents
976 IntType sentry_base = stack_base - sentry_size;
977 IntType file_name_base = sentry_base - file_name_size;
978 IntType env_data_base = file_name_base - env_data_size;
979 IntType arg_data_base = env_data_base - arg_data_size;
980 IntType aux_data_base = arg_data_base - info_block_padding - aux_data_size;
981 IntType auxv_array_base = aux_data_base - aux_array_size - aux_padding;
982 IntType envp_array_base = auxv_array_base - envp_array_size;
983 IntType argv_array_base = envp_array_base - argv_array_size;
984 IntType argc_base = argv_array_base - argc_size;
985
986 DPRINTF(Stack, "The addresses of items on the initial stack:\n");
987 DPRINTF(Stack, "0x%x - file name\n", file_name_base);
988 DPRINTF(Stack, "0x%x - env data\n", env_data_base);
989 DPRINTF(Stack, "0x%x - arg data\n", arg_data_base);
990 DPRINTF(Stack, "0x%x - aux data\n", aux_data_base);
991 DPRINTF(Stack, "0x%x - auxv array\n", auxv_array_base);
992 DPRINTF(Stack, "0x%x - envp array\n", envp_array_base);
993 DPRINTF(Stack, "0x%x - argv array\n", argv_array_base);
994 DPRINTF(Stack, "0x%x - argc \n", argc_base);
995 DPRINTF(Stack, "0x%x - stack min\n", stack_min);
996
997 // write contents to stack
998
999 // figure out argc
1000 IntType argc = argv.size();
1001 IntType guestArgc = X86ISA::htog(argc);
1002
1003 // Write out the sentry void *
1004 IntType sentry_NULL = 0;
1005 initVirtMem.writeBlob(sentry_base, (uint8_t*)&sentry_NULL, sentry_size);
1006
1007 // Write the file name
1008 initVirtMem.writeString(file_name_base, filename.c_str());
1009
1010 // Fix up the aux vectors which point to data
1011 assert(auxv[auxv.size() - 3].a_type == M5_AT_RANDOM);
1012 auxv[auxv.size() - 3].a_val = aux_data_base;
1013 assert(auxv[auxv.size() - 2].a_type == M5_AT_EXECFN);
1014 auxv[auxv.size() - 2].a_val = argv_array_base;
1015 assert(auxv[auxv.size() - 1].a_type == M5_AT_PLATFORM);
1016 auxv[auxv.size() - 1].a_val = aux_data_base + numRandomBytes;
1017
1018
1019 // Copy the aux stuff
1020 for (int x = 0; x < auxv.size(); x++) {
1021 initVirtMem.writeBlob(auxv_array_base + x * 2 * intSize,
1022 (uint8_t*)&(auxv[x].a_type), intSize);
1023 initVirtMem.writeBlob(auxv_array_base + (x * 2 + 1) * intSize,
1024 (uint8_t*)&(auxv[x].a_val), intSize);
1025 }
1026 // Write out the terminating zeroed auxiliary vector
1027 const uint64_t zero = 0;
1028 initVirtMem.writeBlob(auxv_array_base + auxv.size() * 2 * intSize,
1029 (uint8_t*)&zero, intSize);
1030 initVirtMem.writeBlob(auxv_array_base + (auxv.size() * 2 + 1) * intSize,
1031 (uint8_t*)&zero, intSize);
1032
1033 initVirtMem.writeString(aux_data_base, platform.c_str());
1034
1035 copyStringArray(envp, envp_array_base, env_data_base, initVirtMem);
1036 copyStringArray(argv, argv_array_base, arg_data_base, initVirtMem);
1037
1038 initVirtMem.writeBlob(argc_base, (uint8_t*)&guestArgc, intSize);
1039
1040 ThreadContext *tc = system->getThreadContext(contextIds[0]);
1041 // Set the stack pointer register
1042 tc->setIntReg(StackPointerReg, stack_min);
1043
1044 // There doesn't need to be any segment base added in since we're dealing
1045 // with the flat segmentation model.
1046 tc->pcState(getStartPC());
1047
1048 // Align the "stack_min" to a page boundary.
1049 memState->setStackMin(roundDown(stack_min, pageSize));
1050}
1051
1052void
1053X86_64Process::argsInit(int pageSize)
1054{
1055 std::vector<AuxVector<uint64_t> > extraAuxvs;
1056 extraAuxvs.push_back(AuxVector<uint64_t>(M5_AT_SYSINFO_EHDR,
1057 vsyscallPage.base));
1058 X86Process::argsInit<uint64_t>(pageSize, extraAuxvs);
1059}
1060
1061void
1062I386Process::argsInit(int pageSize)
1063{
1064 std::vector<AuxVector<uint32_t> > extraAuxvs;
1065 //Tell the binary where the vsyscall part of the vsyscall page is.
1066 extraAuxvs.push_back(AuxVector<uint32_t>(M5_AT_SYSINFO,
1067 vsyscallPage.base + vsyscallPage.vsyscallOffset));
1068 extraAuxvs.push_back(AuxVector<uint32_t>(M5_AT_SYSINFO_EHDR,
1069 vsyscallPage.base));
1070 X86Process::argsInit<uint32_t>(pageSize, extraAuxvs);
1071}
1072
1073void
1074X86Process::setSyscallReturn(ThreadContext *tc, SyscallReturn retval)
1075{
1076 tc->setIntReg(INTREG_RAX, retval.encodedValue());
1077}
1078
1079X86ISA::IntReg
1080X86_64Process::getSyscallArg(ThreadContext *tc, int &i)
1081{
1082 assert(i < NumArgumentRegs);
1083 return tc->readIntReg(ArgumentReg[i++]);
1084}
1085
1086void
1087X86_64Process::setSyscallArg(ThreadContext *tc, int i, X86ISA::IntReg val)
1088{
1089 assert(i < NumArgumentRegs);
1090 return tc->setIntReg(ArgumentReg[i], val);
1091}
1092
1093void
1094X86_64Process::clone(ThreadContext *old_tc, ThreadContext *new_tc,
1095 Process *p, TheISA::IntReg flags)
1096{
1097 X86Process::clone(old_tc, new_tc, p, flags);
1098 ((X86_64Process*)p)->vsyscallPage = vsyscallPage;
1099}
1100
1101X86ISA::IntReg
1102I386Process::getSyscallArg(ThreadContext *tc, int &i)
1103{
1104 assert(i < NumArgumentRegs32);
1105 return tc->readIntReg(ArgumentReg32[i++]);
1106}
1107
1108X86ISA::IntReg
1109I386Process::getSyscallArg(ThreadContext *tc, int &i, int width)
1110{
1111 assert(width == 32 || width == 64);
1112 assert(i < NumArgumentRegs);
1113 uint64_t retVal = tc->readIntReg(ArgumentReg32[i++]) & mask(32);
1114 if (width == 64)
1115 retVal |= ((uint64_t)tc->readIntReg(ArgumentReg[i++]) << 32);
1116 return retVal;
1117}
1118
1119void
1120I386Process::setSyscallArg(ThreadContext *tc, int i, X86ISA::IntReg val)
1121{
1122 assert(i < NumArgumentRegs);
1123 return tc->setIntReg(ArgumentReg[i], val);
1124}
1125
1126void
1127I386Process::clone(ThreadContext *old_tc, ThreadContext *new_tc,
1128 Process *p, TheISA::IntReg flags)
1129{
1130 X86Process::clone(old_tc, new_tc, p, flags);
1131 ((I386Process*)p)->vsyscallPage = vsyscallPage;
1132}
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