1/* 2 * Copyright (c) 2003-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 133 unchanged lines hidden (view full) --- 142 panic("Unimplemented trap to operating system: trap number %#x.\n", trapNum); 143 } 144} 145 146void 147X86LiveProcess::startup() 148{ 149 argsInit(sizeof(IntReg), VMPageSize); |
150 151 for (int i = 0; i < threadContexts.size(); i++) { 152 ThreadContext * tc = threadContexts[i]; 153 154 SegAttr dataAttr = 0; 155 dataAttr.writable = 1; 156 dataAttr.readable = 1; 157 dataAttr.expandDown = 0; 158 dataAttr.dpl = 3; 159 dataAttr.defaultSize = 0; 160 dataAttr.longMode = 1; 161 162 //Initialize the segment registers. 163 for(int seg = 0; seg < NUM_SEGMENTREGS; seg++) { 164 tc->setMiscRegNoEffect(MISCREG_SEG_BASE(seg), 0); 165 tc->setMiscRegNoEffect(MISCREG_SEG_ATTR(seg), dataAttr); 166 } 167 168 SegAttr csAttr = 0; 169 csAttr.writable = 0; 170 csAttr.readable = 1; 171 csAttr.expandDown = 0; 172 csAttr.dpl = 3; 173 csAttr.defaultSize = 0; 174 csAttr.longMode = 1; 175 176 tc->setMiscRegNoEffect(MISCREG_CS_ATTR, csAttr); 177 178 //Set up the registers that describe the operating mode. 179 CR0 cr0 = 0; 180 cr0.pg = 1; // Turn on paging. 181 cr0.cd = 0; // Don't disable caching. 182 cr0.nw = 0; // This is bit is defined to be ignored. 183 cr0.am = 0; // No alignment checking 184 cr0.wp = 0; // Supervisor mode can write read only pages 185 cr0.ne = 1; 186 cr0.et = 1; // This should always be 1 187 cr0.ts = 0; // We don't do task switching, so causing fp exceptions 188 // would be pointless. 189 cr0.em = 0; // Allow x87 instructions to execute natively. 190 cr0.mp = 1; // This doesn't really matter, but the manual suggests 191 // setting it to one. 192 cr0.pe = 1; // We're definitely in protected mode. 193 tc->setMiscReg(MISCREG_CR0, cr0); 194 195 Efer efer = 0; 196 efer.sce = 1; // Enable system call extensions. 197 efer.lme = 1; // Enable long mode. 198 efer.lma = 1; // Activate long mode. 199 efer.nxe = 1; // Enable nx support. 200 efer.svme = 0; // Disable svm support for now. It isn't implemented. 201 efer.ffxsr = 1; // Turn on fast fxsave and fxrstor. 202 tc->setMiscReg(MISCREG_EFER, efer); 203 } |
204} 205 206void 207X86LiveProcess::argsInit(int intSize, int pageSize) 208{ 209 typedef M5_64_auxv_t auxv_t; 210 Process::startup(); 211 --- 262 unchanged lines hidden --- |