process.cc (13867:9b10bbcf0543) process.cc (13894:8603648c1679)
1/*
2 * Copyright (c) 2014 Advanced Micro Devices, Inc.
3 * Copyright (c) 2007 The Hewlett-Packard Development Company
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2003-2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Gabe Black
42 * Ali Saidi
43 */
44
45#include "arch/x86/process.hh"
46
47#include <string>
48#include <vector>
49
50#include "arch/x86/isa_traits.hh"
51#include "arch/x86/regs/misc.hh"
52#include "arch/x86/regs/segment.hh"
53#include "arch/x86/system.hh"
54#include "arch/x86/types.hh"
55#include "base/loader/elf_object.hh"
56#include "base/loader/object_file.hh"
57#include "base/logging.hh"
58#include "base/trace.hh"
59#include "cpu/thread_context.hh"
60#include "debug/Stack.hh"
61#include "mem/multi_level_page_table.hh"
62#include "mem/page_table.hh"
63#include "params/Process.hh"
64#include "sim/aux_vector.hh"
65#include "sim/process_impl.hh"
66#include "sim/syscall_desc.hh"
67#include "sim/syscall_return.hh"
68#include "sim/system.hh"
69
70using namespace std;
71using namespace X86ISA;
72
73static const int ArgumentReg[] = {
74 INTREG_RDI,
75 INTREG_RSI,
76 INTREG_RDX,
77 // This argument register is r10 for syscalls and rcx for C.
78 INTREG_R10W,
79 // INTREG_RCX,
80 INTREG_R8W,
81 INTREG_R9W
82};
83
84static const int NumArgumentRegs M5_VAR_USED =
85 sizeof(ArgumentReg) / sizeof(const int);
86
87static const int ArgumentReg32[] = {
88 INTREG_EBX,
89 INTREG_ECX,
90 INTREG_EDX,
91 INTREG_ESI,
92 INTREG_EDI,
93 INTREG_EBP
94};
95
96static const int NumArgumentRegs32 M5_VAR_USED =
97 sizeof(ArgumentReg) / sizeof(const int);
98
99template class MultiLevelPageTable<LongModePTE<47, 39>,
100 LongModePTE<38, 30>,
101 LongModePTE<29, 21>,
102 LongModePTE<20, 12> >;
103typedef MultiLevelPageTable<LongModePTE<47, 39>,
104 LongModePTE<38, 30>,
105 LongModePTE<29, 21>,
106 LongModePTE<20, 12> > ArchPageTable;
107
108X86Process::X86Process(ProcessParams *params, ObjectFile *objFile,
109 SyscallDesc *_syscallDescs, int _numSyscallDescs)
110 : Process(params, params->useArchPT ?
111 static_cast<EmulationPageTable *>(
112 new ArchPageTable(params->name, params->pid,
113 params->system, PageBytes)) :
114 new EmulationPageTable(params->name, params->pid,
115 PageBytes),
116 objFile),
117 syscallDescs(_syscallDescs), numSyscallDescs(_numSyscallDescs)
118{
119}
120
121void X86Process::clone(ThreadContext *old_tc, ThreadContext *new_tc,
122 Process *p, RegVal flags)
123{
124 Process::clone(old_tc, new_tc, p, flags);
125 X86Process *process = (X86Process*)p;
126 *process = *this;
127}
128
129X86_64Process::X86_64Process(ProcessParams *params, ObjectFile *objFile,
130 SyscallDesc *_syscallDescs, int _numSyscallDescs)
131 : X86Process(params, objFile, _syscallDescs, _numSyscallDescs)
132{
133
134 vsyscallPage.base = 0xffffffffff600000ULL;
135 vsyscallPage.size = PageBytes;
136 vsyscallPage.vtimeOffset = 0x400;
137 vsyscallPage.vgettimeofdayOffset = 0x0;
138
139 Addr brk_point = roundUp(objFile->dataBase() + objFile->dataSize() +
140 objFile->bssSize(), PageBytes);
141 Addr stack_base = 0x7FFFFFFFF000ULL;
142 Addr max_stack_size = 8 * 1024 * 1024;
143 Addr next_thread_stack_base = stack_base - max_stack_size;
144 Addr mmap_end = 0x7FFFF7FFF000ULL;
145
146 memState = make_shared<MemState>(brk_point, stack_base, max_stack_size,
147 next_thread_stack_base, mmap_end);
148}
149
150void
151I386Process::syscall(int64_t callnum, ThreadContext *tc, Fault *fault)
152{
153 TheISA::PCState pc = tc->pcState();
154 Addr eip = pc.pc();
155 if (eip >= vsyscallPage.base &&
156 eip < vsyscallPage.base + vsyscallPage.size) {
157 pc.npc(vsyscallPage.base + vsyscallPage.vsysexitOffset);
158 tc->pcState(pc);
159 }
160 X86Process::syscall(callnum, tc, fault);
161}
162
163
164I386Process::I386Process(ProcessParams *params, ObjectFile *objFile,
165 SyscallDesc *_syscallDescs, int _numSyscallDescs)
166 : X86Process(params, objFile, _syscallDescs, _numSyscallDescs)
167{
168 if (kvmInSE)
169 panic("KVM CPU model does not support 32 bit processes");
170
171 _gdtStart = ULL(0xffffd000);
172 _gdtSize = PageBytes;
173
174 vsyscallPage.base = 0xffffe000ULL;
175 vsyscallPage.size = PageBytes;
176 vsyscallPage.vsyscallOffset = 0x400;
177 vsyscallPage.vsysexitOffset = 0x410;
178
179 Addr brk_point = roundUp(objFile->dataBase() + objFile->dataSize() +
180 objFile->bssSize(), PageBytes);
181 Addr stack_base = _gdtStart;
182 Addr max_stack_size = 8 * 1024 * 1024;
183 Addr next_thread_stack_base = stack_base - max_stack_size;
184 Addr mmap_end = 0xB7FFF000ULL;
185
186 memState = make_shared<MemState>(brk_point, stack_base, max_stack_size,
187 next_thread_stack_base, mmap_end);
188}
189
190SyscallDesc*
191X86Process::getDesc(int callnum)
192{
193 if (callnum < 0 || callnum >= numSyscallDescs)
194 return NULL;
195 return &syscallDescs[callnum];
196}
197
198void
199X86_64Process::initState()
200{
201 X86Process::initState();
202
203 if (useForClone)
204 return;
205
206 argsInit(PageBytes);
207
208 // Set up the vsyscall page for this process.
209 allocateMem(vsyscallPage.base, vsyscallPage.size);
210 uint8_t vtimeBlob[] = {
211 0x48,0xc7,0xc0,0xc9,0x00,0x00,0x00, // mov $0xc9,%rax
212 0x0f,0x05, // syscall
213 0xc3 // retq
214 };
215 initVirtMem.writeBlob(vsyscallPage.base + vsyscallPage.vtimeOffset,
216 vtimeBlob, sizeof(vtimeBlob));
217
218 uint8_t vgettimeofdayBlob[] = {
219 0x48,0xc7,0xc0,0x60,0x00,0x00,0x00, // mov $0x60,%rax
220 0x0f,0x05, // syscall
221 0xc3 // retq
222 };
223 initVirtMem.writeBlob(vsyscallPage.base + vsyscallPage.vgettimeofdayOffset,
224 vgettimeofdayBlob, sizeof(vgettimeofdayBlob));
225
226 if (kvmInSE) {
227 PortProxy physProxy = system->physProxy;
228
229 Addr syscallCodePhysAddr = system->allocPhysPages(1);
230 Addr gdtPhysAddr = system->allocPhysPages(1);
231 Addr idtPhysAddr = system->allocPhysPages(1);
232 Addr istPhysAddr = system->allocPhysPages(1);
233 Addr tssPhysAddr = system->allocPhysPages(1);
234 Addr pfHandlerPhysAddr = system->allocPhysPages(1);
235
236 /*
237 * Set up the gdt.
238 */
239 uint8_t numGDTEntries = 0;
240 uint64_t nullDescriptor = 0;
241 physProxy.writeBlob(gdtPhysAddr + numGDTEntries * 8,
242 (uint8_t *)(&nullDescriptor), 8);
243 numGDTEntries++;
244
245 SegDescriptor initDesc = 0;
246 initDesc.type.codeOrData = 0; // code or data type
247 initDesc.type.c = 0; // conforming
248 initDesc.type.r = 1; // readable
249 initDesc.dpl = 0; // privilege
250 initDesc.p = 1; // present
251 initDesc.l = 1; // longmode - 64 bit
252 initDesc.d = 0; // operand size
253 initDesc.s = 1; // system segment
254 initDesc.limit = 0xFFFFFFFF;
255 initDesc.base = 0;
256
257 //64 bit code segment
258 SegDescriptor csLowPLDesc = initDesc;
259 csLowPLDesc.type.codeOrData = 1;
260 csLowPLDesc.dpl = 0;
261 uint64_t csLowPLDescVal = csLowPLDesc;
262 physProxy.writeBlob(gdtPhysAddr + numGDTEntries * 8,
263 (uint8_t *)(&csLowPLDescVal), 8);
264
265 numGDTEntries++;
266
267 SegSelector csLowPL = 0;
268 csLowPL.si = numGDTEntries - 1;
269 csLowPL.rpl = 0;
270
271 //64 bit data segment
272 SegDescriptor dsLowPLDesc = initDesc;
273 dsLowPLDesc.type.codeOrData = 0;
274 dsLowPLDesc.dpl = 0;
275 uint64_t dsLowPLDescVal = dsLowPLDesc;
276 physProxy.writeBlob(gdtPhysAddr + numGDTEntries * 8,
277 (uint8_t *)(&dsLowPLDescVal), 8);
278
279 numGDTEntries++;
280
281 SegSelector dsLowPL = 0;
282 dsLowPL.si = numGDTEntries - 1;
283 dsLowPL.rpl = 0;
284
285 //64 bit data segment
286 SegDescriptor dsDesc = initDesc;
287 dsDesc.type.codeOrData = 0;
288 dsDesc.dpl = 3;
289 uint64_t dsDescVal = dsDesc;
290 physProxy.writeBlob(gdtPhysAddr + numGDTEntries * 8,
291 (uint8_t *)(&dsDescVal), 8);
292
293 numGDTEntries++;
294
295 SegSelector ds = 0;
296 ds.si = numGDTEntries - 1;
297 ds.rpl = 3;
298
299 //64 bit code segment
300 SegDescriptor csDesc = initDesc;
301 csDesc.type.codeOrData = 1;
302 csDesc.dpl = 3;
303 uint64_t csDescVal = csDesc;
304 physProxy.writeBlob(gdtPhysAddr + numGDTEntries * 8,
305 (uint8_t *)(&csDescVal), 8);
306
307 numGDTEntries++;
308
309 SegSelector cs = 0;
310 cs.si = numGDTEntries - 1;
311 cs.rpl = 3;
312
313 SegSelector scall = 0;
314 scall.si = csLowPL.si;
315 scall.rpl = 0;
316
317 SegSelector sret = 0;
318 sret.si = dsLowPL.si;
319 sret.rpl = 3;
320
321 /* In long mode the TSS has been extended to 16 Bytes */
322 TSSlow TSSDescLow = 0;
323 TSSDescLow.type = 0xB;
324 TSSDescLow.dpl = 0; // Privelege level 0
325 TSSDescLow.p = 1; // Present
326 TSSDescLow.limit = 0xFFFFFFFF;
327 TSSDescLow.base = bits(TSSVirtAddr, 31, 0);
328
329 TSShigh TSSDescHigh = 0;
330 TSSDescHigh.base = bits(TSSVirtAddr, 63, 32);
331
332 struct TSSDesc {
333 uint64_t low;
334 uint64_t high;
335 } tssDescVal = {TSSDescLow, TSSDescHigh};
336
337 physProxy.writeBlob(gdtPhysAddr + numGDTEntries * 8,
338 (uint8_t *)(&tssDescVal), sizeof(tssDescVal));
339
340 numGDTEntries++;
341
342 SegSelector tssSel = 0;
343 tssSel.si = numGDTEntries - 1;
344
345 uint64_t tss_base_addr = (TSSDescHigh.base << 32) | TSSDescLow.base;
346 uint64_t tss_limit = TSSDescLow.limit;
347
348 SegAttr tss_attr = 0;
349
350 tss_attr.type = TSSDescLow.type;
351 tss_attr.dpl = TSSDescLow.dpl;
352 tss_attr.present = TSSDescLow.p;
353 tss_attr.granularity = TSSDescLow.g;
354 tss_attr.unusable = 0;
355
356 for (int i = 0; i < contextIds.size(); i++) {
357 ThreadContext * tc = system->getThreadContext(contextIds[i]);
358
359 tc->setMiscReg(MISCREG_CS, cs);
360 tc->setMiscReg(MISCREG_DS, ds);
361 tc->setMiscReg(MISCREG_ES, ds);
362 tc->setMiscReg(MISCREG_FS, ds);
363 tc->setMiscReg(MISCREG_GS, ds);
364 tc->setMiscReg(MISCREG_SS, ds);
365
366 // LDT
367 tc->setMiscReg(MISCREG_TSL, 0);
368 SegAttr tslAttr = 0;
369 tslAttr.present = 1;
370 tslAttr.type = 2;
371 tc->setMiscReg(MISCREG_TSL_ATTR, tslAttr);
372
373 tc->setMiscReg(MISCREG_TSG_BASE, GDTVirtAddr);
374 tc->setMiscReg(MISCREG_TSG_LIMIT, 8 * numGDTEntries - 1);
375
376 tc->setMiscReg(MISCREG_TR, tssSel);
377 tc->setMiscReg(MISCREG_TR_BASE, tss_base_addr);
378 tc->setMiscReg(MISCREG_TR_EFF_BASE, 0);
379 tc->setMiscReg(MISCREG_TR_LIMIT, tss_limit);
380 tc->setMiscReg(MISCREG_TR_ATTR, tss_attr);
381
382 //Start using longmode segments.
383 installSegDesc(tc, SEGMENT_REG_CS, csDesc, true);
384 installSegDesc(tc, SEGMENT_REG_DS, dsDesc, true);
385 installSegDesc(tc, SEGMENT_REG_ES, dsDesc, true);
386 installSegDesc(tc, SEGMENT_REG_FS, dsDesc, true);
387 installSegDesc(tc, SEGMENT_REG_GS, dsDesc, true);
388 installSegDesc(tc, SEGMENT_REG_SS, dsDesc, true);
389
390 Efer efer = 0;
391 efer.sce = 1; // Enable system call extensions.
392 efer.lme = 1; // Enable long mode.
393 efer.lma = 1; // Activate long mode.
394 efer.nxe = 0; // Enable nx support.
395 efer.svme = 1; // Enable svm support for now.
396 efer.ffxsr = 0; // Turn on fast fxsave and fxrstor.
397 tc->setMiscReg(MISCREG_EFER, efer);
398
399 //Set up the registers that describe the operating mode.
400 CR0 cr0 = 0;
401 cr0.pg = 1; // Turn on paging.
402 cr0.cd = 0; // Don't disable caching.
403 cr0.nw = 0; // This is bit is defined to be ignored.
404 cr0.am = 1; // No alignment checking
405 cr0.wp = 1; // Supervisor mode can write read only pages
406 cr0.ne = 1;
407 cr0.et = 1; // This should always be 1
408 cr0.ts = 0; // We don't do task switching, so causing fp exceptions
409 // would be pointless.
410 cr0.em = 0; // Allow x87 instructions to execute natively.
411 cr0.mp = 1; // This doesn't really matter, but the manual suggests
412 // setting it to one.
413 cr0.pe = 1; // We're definitely in protected mode.
414 tc->setMiscReg(MISCREG_CR0, cr0);
415
416 CR0 cr2 = 0;
417 tc->setMiscReg(MISCREG_CR2, cr2);
418
419 CR3 cr3 = dynamic_cast<ArchPageTable *>(pTable)->basePtr();
420 tc->setMiscReg(MISCREG_CR3, cr3);
421
422 CR4 cr4 = 0;
423 //Turn on pae.
424 cr4.osxsave = 1; // Enable XSAVE and Proc Extended States
425 cr4.osxmmexcpt = 1; // Operating System Unmasked Exception
426 cr4.osfxsr = 1; // Operating System FXSave/FSRSTOR Support
427 cr4.pce = 0; // Performance-Monitoring Counter Enable
428 cr4.pge = 0; // Page-Global Enable
429 cr4.mce = 0; // Machine Check Enable
430 cr4.pae = 1; // Physical-Address Extension
431 cr4.pse = 0; // Page Size Extensions
432 cr4.de = 0; // Debugging Extensions
433 cr4.tsd = 0; // Time Stamp Disable
434 cr4.pvi = 0; // Protected-Mode Virtual Interrupts
435 cr4.vme = 0; // Virtual-8086 Mode Extensions
436
437 tc->setMiscReg(MISCREG_CR4, cr4);
438
439 CR4 cr8 = 0;
440 tc->setMiscReg(MISCREG_CR8, cr8);
441
442 tc->setMiscReg(MISCREG_MXCSR, 0x1f80);
443
444 tc->setMiscReg(MISCREG_APIC_BASE, 0xfee00900);
445
446 tc->setMiscReg(MISCREG_TSG_BASE, GDTVirtAddr);
447 tc->setMiscReg(MISCREG_TSG_LIMIT, 0xffff);
448
449 tc->setMiscReg(MISCREG_IDTR_BASE, IDTVirtAddr);
450 tc->setMiscReg(MISCREG_IDTR_LIMIT, 0xffff);
451
452 /* enabling syscall and sysret */
453 RegVal star = ((RegVal)sret << 48) | ((RegVal)scall << 32);
454 tc->setMiscReg(MISCREG_STAR, star);
455 RegVal lstar = (RegVal)syscallCodeVirtAddr;
456 tc->setMiscReg(MISCREG_LSTAR, lstar);
457 RegVal sfmask = (1 << 8) | (1 << 10); // TF | DF
458 tc->setMiscReg(MISCREG_SF_MASK, sfmask);
459 }
460
461 /* Set up the content of the TSS and write it to physical memory. */
462
463 struct {
464 uint32_t reserved0; // +00h
465 uint32_t RSP0_low; // +04h
466 uint32_t RSP0_high; // +08h
467 uint32_t RSP1_low; // +0Ch
468 uint32_t RSP1_high; // +10h
469 uint32_t RSP2_low; // +14h
470 uint32_t RSP2_high; // +18h
471 uint32_t reserved1; // +1Ch
472 uint32_t reserved2; // +20h
473 uint32_t IST1_low; // +24h
474 uint32_t IST1_high; // +28h
475 uint32_t IST2_low; // +2Ch
476 uint32_t IST2_high; // +30h
477 uint32_t IST3_low; // +34h
478 uint32_t IST3_high; // +38h
479 uint32_t IST4_low; // +3Ch
480 uint32_t IST4_high; // +40h
481 uint32_t IST5_low; // +44h
482 uint32_t IST5_high; // +48h
483 uint32_t IST6_low; // +4Ch
484 uint32_t IST6_high; // +50h
485 uint32_t IST7_low; // +54h
486 uint32_t IST7_high; // +58h
487 uint32_t reserved3; // +5Ch
488 uint32_t reserved4; // +60h
489 uint16_t reserved5; // +64h
490 uint16_t IO_MapBase; // +66h
491 } tss;
492
493 /** setting Interrupt Stack Table */
494 uint64_t IST_start = ISTVirtAddr + PageBytes;
495 tss.IST1_low = IST_start;
496 tss.IST1_high = IST_start >> 32;
497 tss.RSP0_low = tss.IST1_low;
498 tss.RSP0_high = tss.IST1_high;
499 tss.RSP1_low = tss.IST1_low;
500 tss.RSP1_high = tss.IST1_high;
501 tss.RSP2_low = tss.IST1_low;
502 tss.RSP2_high = tss.IST1_high;
503 physProxy.writeBlob(tssPhysAddr, (uint8_t *)(&tss), sizeof(tss));
504
505 /* Setting IDT gates */
506 GateDescriptorLow PFGateLow = 0;
507 PFGateLow.offsetHigh = bits(PFHandlerVirtAddr, 31, 16);
508 PFGateLow.offsetLow = bits(PFHandlerVirtAddr, 15, 0);
509 PFGateLow.selector = csLowPL;
510 PFGateLow.p = 1;
511 PFGateLow.dpl = 0;
512 PFGateLow.type = 0xe; // gate interrupt type
513 PFGateLow.IST = 0; // setting IST to 0 and using RSP0
514
515 GateDescriptorHigh PFGateHigh = 0;
516 PFGateHigh.offset = bits(PFHandlerVirtAddr, 63, 32);
517
518 struct {
519 uint64_t low;
520 uint64_t high;
521 } PFGate = {PFGateLow, PFGateHigh};
522
523 physProxy.writeBlob(idtPhysAddr + 0xE0,
524 (uint8_t *)(&PFGate), sizeof(PFGate));
525
526 /* System call handler */
527 uint8_t syscallBlob[] = {
528 // mov %rax, (0xffffc90000005600)
529 0x48, 0xa3, 0x00, 0x60, 0x00,
530 0x00, 0x00, 0xc9, 0xff, 0xff,
531 // sysret
532 0x48, 0x0f, 0x07
533 };
534
535 physProxy.writeBlob(syscallCodePhysAddr,
536 syscallBlob, sizeof(syscallBlob));
537
538 /** Page fault handler */
539 uint8_t faultBlob[] = {
540 // mov %rax, (0xffffc90000005700)
541 0x48, 0xa3, 0x00, 0x61, 0x00,
542 0x00, 0x00, 0xc9, 0xff, 0xff,
543 // add $0x8, %rsp # skip error
544 0x48, 0x83, 0xc4, 0x08,
545 // iretq
546 0x48, 0xcf
547 };
548
549 physProxy.writeBlob(pfHandlerPhysAddr, faultBlob, sizeof(faultBlob));
550
551 /* Syscall handler */
552 pTable->map(syscallCodeVirtAddr, syscallCodePhysAddr,
553 PageBytes, false);
554 /* GDT */
555 pTable->map(GDTVirtAddr, gdtPhysAddr, PageBytes, false);
556 /* IDT */
557 pTable->map(IDTVirtAddr, idtPhysAddr, PageBytes, false);
558 /* TSS */
559 pTable->map(TSSVirtAddr, tssPhysAddr, PageBytes, false);
560 /* IST */
561 pTable->map(ISTVirtAddr, istPhysAddr, PageBytes, false);
562 /* PF handler */
563 pTable->map(PFHandlerVirtAddr, pfHandlerPhysAddr, PageBytes, false);
564 /* MMIO region for m5ops */
565 pTable->map(MMIORegionVirtAddr, MMIORegionPhysAddr,
566 16 * PageBytes, false);
567 } else {
568 for (int i = 0; i < contextIds.size(); i++) {
569 ThreadContext * tc = system->getThreadContext(contextIds[i]);
570
571 SegAttr dataAttr = 0;
572 dataAttr.dpl = 3;
573 dataAttr.unusable = 0;
574 dataAttr.defaultSize = 1;
575 dataAttr.longMode = 1;
576 dataAttr.avl = 0;
577 dataAttr.granularity = 1;
578 dataAttr.present = 1;
579 dataAttr.type = 3;
580 dataAttr.writable = 1;
581 dataAttr.readable = 1;
582 dataAttr.expandDown = 0;
583 dataAttr.system = 1;
584
585 // Initialize the segment registers.
586 for (int seg = 0; seg < NUM_SEGMENTREGS; seg++) {
587 tc->setMiscRegNoEffect(MISCREG_SEG_BASE(seg), 0);
588 tc->setMiscRegNoEffect(MISCREG_SEG_EFF_BASE(seg), 0);
589 tc->setMiscRegNoEffect(MISCREG_SEG_ATTR(seg), dataAttr);
590 }
591
592 SegAttr csAttr = 0;
593 csAttr.dpl = 3;
594 csAttr.unusable = 0;
595 csAttr.defaultSize = 0;
596 csAttr.longMode = 1;
597 csAttr.avl = 0;
598 csAttr.granularity = 1;
599 csAttr.present = 1;
600 csAttr.type = 10;
601 csAttr.writable = 0;
602 csAttr.readable = 1;
603 csAttr.expandDown = 0;
604 csAttr.system = 1;
605
606 tc->setMiscRegNoEffect(MISCREG_CS_ATTR, csAttr);
607
608 Efer efer = 0;
609 efer.sce = 1; // Enable system call extensions.
610 efer.lme = 1; // Enable long mode.
611 efer.lma = 1; // Activate long mode.
612 efer.nxe = 1; // Enable nx support.
613 efer.svme = 0; // Disable svm support for now. It isn't implemented.
614 efer.ffxsr = 1; // Turn on fast fxsave and fxrstor.
615 tc->setMiscReg(MISCREG_EFER, efer);
616
617 // Set up the registers that describe the operating mode.
618 CR0 cr0 = 0;
619 cr0.pg = 1; // Turn on paging.
620 cr0.cd = 0; // Don't disable caching.
621 cr0.nw = 0; // This is bit is defined to be ignored.
622 cr0.am = 0; // No alignment checking
623 cr0.wp = 0; // Supervisor mode can write read only pages
624 cr0.ne = 1;
625 cr0.et = 1; // This should always be 1
626 cr0.ts = 0; // We don't do task switching, so causing fp exceptions
627 // would be pointless.
628 cr0.em = 0; // Allow x87 instructions to execute natively.
629 cr0.mp = 1; // This doesn't really matter, but the manual suggests
630 // setting it to one.
631 cr0.pe = 1; // We're definitely in protected mode.
632 tc->setMiscReg(MISCREG_CR0, cr0);
633
634 tc->setMiscReg(MISCREG_MXCSR, 0x1f80);
635 }
636 }
637}
638
639void
640I386Process::initState()
641{
642 X86Process::initState();
643
644 argsInit(PageBytes);
645
646 /*
647 * Set up a GDT for this process. The whole GDT wouldn't really be for
648 * this process, but the only parts we care about are.
649 */
650 allocateMem(_gdtStart, _gdtSize);
651 uint64_t zero = 0;
652 assert(_gdtSize % sizeof(zero) == 0);
653 for (Addr gdtCurrent = _gdtStart;
654 gdtCurrent < _gdtStart + _gdtSize; gdtCurrent += sizeof(zero)) {
655 initVirtMem.write(gdtCurrent, zero);
656 }
657
658 // Set up the vsyscall page for this process.
659 allocateMem(vsyscallPage.base, vsyscallPage.size);
660 uint8_t vsyscallBlob[] = {
661 0x51, // push %ecx
662 0x52, // push %edp
663 0x55, // push %ebp
664 0x89, 0xe5, // mov %esp, %ebp
665 0x0f, 0x34 // sysenter
666 };
667 initVirtMem.writeBlob(vsyscallPage.base + vsyscallPage.vsyscallOffset,
668 vsyscallBlob, sizeof(vsyscallBlob));
669
670 uint8_t vsysexitBlob[] = {
671 0x5d, // pop %ebp
672 0x5a, // pop %edx
673 0x59, // pop %ecx
674 0xc3 // ret
675 };
676 initVirtMem.writeBlob(vsyscallPage.base + vsyscallPage.vsysexitOffset,
677 vsysexitBlob, sizeof(vsysexitBlob));
678
679 for (int i = 0; i < contextIds.size(); i++) {
680 ThreadContext * tc = system->getThreadContext(contextIds[i]);
681
682 SegAttr dataAttr = 0;
683 dataAttr.dpl = 3;
684 dataAttr.unusable = 0;
685 dataAttr.defaultSize = 1;
686 dataAttr.longMode = 0;
687 dataAttr.avl = 0;
688 dataAttr.granularity = 1;
689 dataAttr.present = 1;
690 dataAttr.type = 3;
691 dataAttr.writable = 1;
692 dataAttr.readable = 1;
693 dataAttr.expandDown = 0;
694 dataAttr.system = 1;
695
696 // Initialize the segment registers.
697 for (int seg = 0; seg < NUM_SEGMENTREGS; seg++) {
698 tc->setMiscRegNoEffect(MISCREG_SEG_BASE(seg), 0);
699 tc->setMiscRegNoEffect(MISCREG_SEG_EFF_BASE(seg), 0);
700 tc->setMiscRegNoEffect(MISCREG_SEG_ATTR(seg), dataAttr);
701 tc->setMiscRegNoEffect(MISCREG_SEG_SEL(seg), 0xB);
702 tc->setMiscRegNoEffect(MISCREG_SEG_LIMIT(seg), (uint32_t)(-1));
703 }
704
705 SegAttr csAttr = 0;
706 csAttr.dpl = 3;
707 csAttr.unusable = 0;
708 csAttr.defaultSize = 1;
709 csAttr.longMode = 0;
710 csAttr.avl = 0;
711 csAttr.granularity = 1;
712 csAttr.present = 1;
713 csAttr.type = 0xa;
714 csAttr.writable = 0;
715 csAttr.readable = 1;
716 csAttr.expandDown = 0;
717 csAttr.system = 1;
718
719 tc->setMiscRegNoEffect(MISCREG_CS_ATTR, csAttr);
720
721 tc->setMiscRegNoEffect(MISCREG_TSG_BASE, _gdtStart);
722 tc->setMiscRegNoEffect(MISCREG_TSG_EFF_BASE, _gdtStart);
723 tc->setMiscRegNoEffect(MISCREG_TSG_LIMIT, _gdtStart + _gdtSize - 1);
724
725 // Set the LDT selector to 0 to deactivate it.
726 tc->setMiscRegNoEffect(MISCREG_TSL, 0);
727
728 Efer efer = 0;
729 efer.sce = 1; // Enable system call extensions.
730 efer.lme = 1; // Enable long mode.
731 efer.lma = 0; // Deactivate long mode.
732 efer.nxe = 1; // Enable nx support.
733 efer.svme = 0; // Disable svm support for now. It isn't implemented.
734 efer.ffxsr = 1; // Turn on fast fxsave and fxrstor.
735 tc->setMiscReg(MISCREG_EFER, efer);
736
737 // Set up the registers that describe the operating mode.
738 CR0 cr0 = 0;
739 cr0.pg = 1; // Turn on paging.
740 cr0.cd = 0; // Don't disable caching.
741 cr0.nw = 0; // This is bit is defined to be ignored.
742 cr0.am = 0; // No alignment checking
743 cr0.wp = 0; // Supervisor mode can write read only pages
744 cr0.ne = 1;
745 cr0.et = 1; // This should always be 1
746 cr0.ts = 0; // We don't do task switching, so causing fp exceptions
747 // would be pointless.
748 cr0.em = 0; // Allow x87 instructions to execute natively.
749 cr0.mp = 1; // This doesn't really matter, but the manual suggests
750 // setting it to one.
751 cr0.pe = 1; // We're definitely in protected mode.
752 tc->setMiscReg(MISCREG_CR0, cr0);
753
754 tc->setMiscReg(MISCREG_MXCSR, 0x1f80);
755 }
756}
757
758template<class IntType>
759void
760X86Process::argsInit(int pageSize,
761 std::vector<AuxVector<IntType> > extraAuxvs)
762{
763 int intSize = sizeof(IntType);
764
1/*
2 * Copyright (c) 2014 Advanced Micro Devices, Inc.
3 * Copyright (c) 2007 The Hewlett-Packard Development Company
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2003-2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Gabe Black
42 * Ali Saidi
43 */
44
45#include "arch/x86/process.hh"
46
47#include <string>
48#include <vector>
49
50#include "arch/x86/isa_traits.hh"
51#include "arch/x86/regs/misc.hh"
52#include "arch/x86/regs/segment.hh"
53#include "arch/x86/system.hh"
54#include "arch/x86/types.hh"
55#include "base/loader/elf_object.hh"
56#include "base/loader/object_file.hh"
57#include "base/logging.hh"
58#include "base/trace.hh"
59#include "cpu/thread_context.hh"
60#include "debug/Stack.hh"
61#include "mem/multi_level_page_table.hh"
62#include "mem/page_table.hh"
63#include "params/Process.hh"
64#include "sim/aux_vector.hh"
65#include "sim/process_impl.hh"
66#include "sim/syscall_desc.hh"
67#include "sim/syscall_return.hh"
68#include "sim/system.hh"
69
70using namespace std;
71using namespace X86ISA;
72
73static const int ArgumentReg[] = {
74 INTREG_RDI,
75 INTREG_RSI,
76 INTREG_RDX,
77 // This argument register is r10 for syscalls and rcx for C.
78 INTREG_R10W,
79 // INTREG_RCX,
80 INTREG_R8W,
81 INTREG_R9W
82};
83
84static const int NumArgumentRegs M5_VAR_USED =
85 sizeof(ArgumentReg) / sizeof(const int);
86
87static const int ArgumentReg32[] = {
88 INTREG_EBX,
89 INTREG_ECX,
90 INTREG_EDX,
91 INTREG_ESI,
92 INTREG_EDI,
93 INTREG_EBP
94};
95
96static const int NumArgumentRegs32 M5_VAR_USED =
97 sizeof(ArgumentReg) / sizeof(const int);
98
99template class MultiLevelPageTable<LongModePTE<47, 39>,
100 LongModePTE<38, 30>,
101 LongModePTE<29, 21>,
102 LongModePTE<20, 12> >;
103typedef MultiLevelPageTable<LongModePTE<47, 39>,
104 LongModePTE<38, 30>,
105 LongModePTE<29, 21>,
106 LongModePTE<20, 12> > ArchPageTable;
107
108X86Process::X86Process(ProcessParams *params, ObjectFile *objFile,
109 SyscallDesc *_syscallDescs, int _numSyscallDescs)
110 : Process(params, params->useArchPT ?
111 static_cast<EmulationPageTable *>(
112 new ArchPageTable(params->name, params->pid,
113 params->system, PageBytes)) :
114 new EmulationPageTable(params->name, params->pid,
115 PageBytes),
116 objFile),
117 syscallDescs(_syscallDescs), numSyscallDescs(_numSyscallDescs)
118{
119}
120
121void X86Process::clone(ThreadContext *old_tc, ThreadContext *new_tc,
122 Process *p, RegVal flags)
123{
124 Process::clone(old_tc, new_tc, p, flags);
125 X86Process *process = (X86Process*)p;
126 *process = *this;
127}
128
129X86_64Process::X86_64Process(ProcessParams *params, ObjectFile *objFile,
130 SyscallDesc *_syscallDescs, int _numSyscallDescs)
131 : X86Process(params, objFile, _syscallDescs, _numSyscallDescs)
132{
133
134 vsyscallPage.base = 0xffffffffff600000ULL;
135 vsyscallPage.size = PageBytes;
136 vsyscallPage.vtimeOffset = 0x400;
137 vsyscallPage.vgettimeofdayOffset = 0x0;
138
139 Addr brk_point = roundUp(objFile->dataBase() + objFile->dataSize() +
140 objFile->bssSize(), PageBytes);
141 Addr stack_base = 0x7FFFFFFFF000ULL;
142 Addr max_stack_size = 8 * 1024 * 1024;
143 Addr next_thread_stack_base = stack_base - max_stack_size;
144 Addr mmap_end = 0x7FFFF7FFF000ULL;
145
146 memState = make_shared<MemState>(brk_point, stack_base, max_stack_size,
147 next_thread_stack_base, mmap_end);
148}
149
150void
151I386Process::syscall(int64_t callnum, ThreadContext *tc, Fault *fault)
152{
153 TheISA::PCState pc = tc->pcState();
154 Addr eip = pc.pc();
155 if (eip >= vsyscallPage.base &&
156 eip < vsyscallPage.base + vsyscallPage.size) {
157 pc.npc(vsyscallPage.base + vsyscallPage.vsysexitOffset);
158 tc->pcState(pc);
159 }
160 X86Process::syscall(callnum, tc, fault);
161}
162
163
164I386Process::I386Process(ProcessParams *params, ObjectFile *objFile,
165 SyscallDesc *_syscallDescs, int _numSyscallDescs)
166 : X86Process(params, objFile, _syscallDescs, _numSyscallDescs)
167{
168 if (kvmInSE)
169 panic("KVM CPU model does not support 32 bit processes");
170
171 _gdtStart = ULL(0xffffd000);
172 _gdtSize = PageBytes;
173
174 vsyscallPage.base = 0xffffe000ULL;
175 vsyscallPage.size = PageBytes;
176 vsyscallPage.vsyscallOffset = 0x400;
177 vsyscallPage.vsysexitOffset = 0x410;
178
179 Addr brk_point = roundUp(objFile->dataBase() + objFile->dataSize() +
180 objFile->bssSize(), PageBytes);
181 Addr stack_base = _gdtStart;
182 Addr max_stack_size = 8 * 1024 * 1024;
183 Addr next_thread_stack_base = stack_base - max_stack_size;
184 Addr mmap_end = 0xB7FFF000ULL;
185
186 memState = make_shared<MemState>(brk_point, stack_base, max_stack_size,
187 next_thread_stack_base, mmap_end);
188}
189
190SyscallDesc*
191X86Process::getDesc(int callnum)
192{
193 if (callnum < 0 || callnum >= numSyscallDescs)
194 return NULL;
195 return &syscallDescs[callnum];
196}
197
198void
199X86_64Process::initState()
200{
201 X86Process::initState();
202
203 if (useForClone)
204 return;
205
206 argsInit(PageBytes);
207
208 // Set up the vsyscall page for this process.
209 allocateMem(vsyscallPage.base, vsyscallPage.size);
210 uint8_t vtimeBlob[] = {
211 0x48,0xc7,0xc0,0xc9,0x00,0x00,0x00, // mov $0xc9,%rax
212 0x0f,0x05, // syscall
213 0xc3 // retq
214 };
215 initVirtMem.writeBlob(vsyscallPage.base + vsyscallPage.vtimeOffset,
216 vtimeBlob, sizeof(vtimeBlob));
217
218 uint8_t vgettimeofdayBlob[] = {
219 0x48,0xc7,0xc0,0x60,0x00,0x00,0x00, // mov $0x60,%rax
220 0x0f,0x05, // syscall
221 0xc3 // retq
222 };
223 initVirtMem.writeBlob(vsyscallPage.base + vsyscallPage.vgettimeofdayOffset,
224 vgettimeofdayBlob, sizeof(vgettimeofdayBlob));
225
226 if (kvmInSE) {
227 PortProxy physProxy = system->physProxy;
228
229 Addr syscallCodePhysAddr = system->allocPhysPages(1);
230 Addr gdtPhysAddr = system->allocPhysPages(1);
231 Addr idtPhysAddr = system->allocPhysPages(1);
232 Addr istPhysAddr = system->allocPhysPages(1);
233 Addr tssPhysAddr = system->allocPhysPages(1);
234 Addr pfHandlerPhysAddr = system->allocPhysPages(1);
235
236 /*
237 * Set up the gdt.
238 */
239 uint8_t numGDTEntries = 0;
240 uint64_t nullDescriptor = 0;
241 physProxy.writeBlob(gdtPhysAddr + numGDTEntries * 8,
242 (uint8_t *)(&nullDescriptor), 8);
243 numGDTEntries++;
244
245 SegDescriptor initDesc = 0;
246 initDesc.type.codeOrData = 0; // code or data type
247 initDesc.type.c = 0; // conforming
248 initDesc.type.r = 1; // readable
249 initDesc.dpl = 0; // privilege
250 initDesc.p = 1; // present
251 initDesc.l = 1; // longmode - 64 bit
252 initDesc.d = 0; // operand size
253 initDesc.s = 1; // system segment
254 initDesc.limit = 0xFFFFFFFF;
255 initDesc.base = 0;
256
257 //64 bit code segment
258 SegDescriptor csLowPLDesc = initDesc;
259 csLowPLDesc.type.codeOrData = 1;
260 csLowPLDesc.dpl = 0;
261 uint64_t csLowPLDescVal = csLowPLDesc;
262 physProxy.writeBlob(gdtPhysAddr + numGDTEntries * 8,
263 (uint8_t *)(&csLowPLDescVal), 8);
264
265 numGDTEntries++;
266
267 SegSelector csLowPL = 0;
268 csLowPL.si = numGDTEntries - 1;
269 csLowPL.rpl = 0;
270
271 //64 bit data segment
272 SegDescriptor dsLowPLDesc = initDesc;
273 dsLowPLDesc.type.codeOrData = 0;
274 dsLowPLDesc.dpl = 0;
275 uint64_t dsLowPLDescVal = dsLowPLDesc;
276 physProxy.writeBlob(gdtPhysAddr + numGDTEntries * 8,
277 (uint8_t *)(&dsLowPLDescVal), 8);
278
279 numGDTEntries++;
280
281 SegSelector dsLowPL = 0;
282 dsLowPL.si = numGDTEntries - 1;
283 dsLowPL.rpl = 0;
284
285 //64 bit data segment
286 SegDescriptor dsDesc = initDesc;
287 dsDesc.type.codeOrData = 0;
288 dsDesc.dpl = 3;
289 uint64_t dsDescVal = dsDesc;
290 physProxy.writeBlob(gdtPhysAddr + numGDTEntries * 8,
291 (uint8_t *)(&dsDescVal), 8);
292
293 numGDTEntries++;
294
295 SegSelector ds = 0;
296 ds.si = numGDTEntries - 1;
297 ds.rpl = 3;
298
299 //64 bit code segment
300 SegDescriptor csDesc = initDesc;
301 csDesc.type.codeOrData = 1;
302 csDesc.dpl = 3;
303 uint64_t csDescVal = csDesc;
304 physProxy.writeBlob(gdtPhysAddr + numGDTEntries * 8,
305 (uint8_t *)(&csDescVal), 8);
306
307 numGDTEntries++;
308
309 SegSelector cs = 0;
310 cs.si = numGDTEntries - 1;
311 cs.rpl = 3;
312
313 SegSelector scall = 0;
314 scall.si = csLowPL.si;
315 scall.rpl = 0;
316
317 SegSelector sret = 0;
318 sret.si = dsLowPL.si;
319 sret.rpl = 3;
320
321 /* In long mode the TSS has been extended to 16 Bytes */
322 TSSlow TSSDescLow = 0;
323 TSSDescLow.type = 0xB;
324 TSSDescLow.dpl = 0; // Privelege level 0
325 TSSDescLow.p = 1; // Present
326 TSSDescLow.limit = 0xFFFFFFFF;
327 TSSDescLow.base = bits(TSSVirtAddr, 31, 0);
328
329 TSShigh TSSDescHigh = 0;
330 TSSDescHigh.base = bits(TSSVirtAddr, 63, 32);
331
332 struct TSSDesc {
333 uint64_t low;
334 uint64_t high;
335 } tssDescVal = {TSSDescLow, TSSDescHigh};
336
337 physProxy.writeBlob(gdtPhysAddr + numGDTEntries * 8,
338 (uint8_t *)(&tssDescVal), sizeof(tssDescVal));
339
340 numGDTEntries++;
341
342 SegSelector tssSel = 0;
343 tssSel.si = numGDTEntries - 1;
344
345 uint64_t tss_base_addr = (TSSDescHigh.base << 32) | TSSDescLow.base;
346 uint64_t tss_limit = TSSDescLow.limit;
347
348 SegAttr tss_attr = 0;
349
350 tss_attr.type = TSSDescLow.type;
351 tss_attr.dpl = TSSDescLow.dpl;
352 tss_attr.present = TSSDescLow.p;
353 tss_attr.granularity = TSSDescLow.g;
354 tss_attr.unusable = 0;
355
356 for (int i = 0; i < contextIds.size(); i++) {
357 ThreadContext * tc = system->getThreadContext(contextIds[i]);
358
359 tc->setMiscReg(MISCREG_CS, cs);
360 tc->setMiscReg(MISCREG_DS, ds);
361 tc->setMiscReg(MISCREG_ES, ds);
362 tc->setMiscReg(MISCREG_FS, ds);
363 tc->setMiscReg(MISCREG_GS, ds);
364 tc->setMiscReg(MISCREG_SS, ds);
365
366 // LDT
367 tc->setMiscReg(MISCREG_TSL, 0);
368 SegAttr tslAttr = 0;
369 tslAttr.present = 1;
370 tslAttr.type = 2;
371 tc->setMiscReg(MISCREG_TSL_ATTR, tslAttr);
372
373 tc->setMiscReg(MISCREG_TSG_BASE, GDTVirtAddr);
374 tc->setMiscReg(MISCREG_TSG_LIMIT, 8 * numGDTEntries - 1);
375
376 tc->setMiscReg(MISCREG_TR, tssSel);
377 tc->setMiscReg(MISCREG_TR_BASE, tss_base_addr);
378 tc->setMiscReg(MISCREG_TR_EFF_BASE, 0);
379 tc->setMiscReg(MISCREG_TR_LIMIT, tss_limit);
380 tc->setMiscReg(MISCREG_TR_ATTR, tss_attr);
381
382 //Start using longmode segments.
383 installSegDesc(tc, SEGMENT_REG_CS, csDesc, true);
384 installSegDesc(tc, SEGMENT_REG_DS, dsDesc, true);
385 installSegDesc(tc, SEGMENT_REG_ES, dsDesc, true);
386 installSegDesc(tc, SEGMENT_REG_FS, dsDesc, true);
387 installSegDesc(tc, SEGMENT_REG_GS, dsDesc, true);
388 installSegDesc(tc, SEGMENT_REG_SS, dsDesc, true);
389
390 Efer efer = 0;
391 efer.sce = 1; // Enable system call extensions.
392 efer.lme = 1; // Enable long mode.
393 efer.lma = 1; // Activate long mode.
394 efer.nxe = 0; // Enable nx support.
395 efer.svme = 1; // Enable svm support for now.
396 efer.ffxsr = 0; // Turn on fast fxsave and fxrstor.
397 tc->setMiscReg(MISCREG_EFER, efer);
398
399 //Set up the registers that describe the operating mode.
400 CR0 cr0 = 0;
401 cr0.pg = 1; // Turn on paging.
402 cr0.cd = 0; // Don't disable caching.
403 cr0.nw = 0; // This is bit is defined to be ignored.
404 cr0.am = 1; // No alignment checking
405 cr0.wp = 1; // Supervisor mode can write read only pages
406 cr0.ne = 1;
407 cr0.et = 1; // This should always be 1
408 cr0.ts = 0; // We don't do task switching, so causing fp exceptions
409 // would be pointless.
410 cr0.em = 0; // Allow x87 instructions to execute natively.
411 cr0.mp = 1; // This doesn't really matter, but the manual suggests
412 // setting it to one.
413 cr0.pe = 1; // We're definitely in protected mode.
414 tc->setMiscReg(MISCREG_CR0, cr0);
415
416 CR0 cr2 = 0;
417 tc->setMiscReg(MISCREG_CR2, cr2);
418
419 CR3 cr3 = dynamic_cast<ArchPageTable *>(pTable)->basePtr();
420 tc->setMiscReg(MISCREG_CR3, cr3);
421
422 CR4 cr4 = 0;
423 //Turn on pae.
424 cr4.osxsave = 1; // Enable XSAVE and Proc Extended States
425 cr4.osxmmexcpt = 1; // Operating System Unmasked Exception
426 cr4.osfxsr = 1; // Operating System FXSave/FSRSTOR Support
427 cr4.pce = 0; // Performance-Monitoring Counter Enable
428 cr4.pge = 0; // Page-Global Enable
429 cr4.mce = 0; // Machine Check Enable
430 cr4.pae = 1; // Physical-Address Extension
431 cr4.pse = 0; // Page Size Extensions
432 cr4.de = 0; // Debugging Extensions
433 cr4.tsd = 0; // Time Stamp Disable
434 cr4.pvi = 0; // Protected-Mode Virtual Interrupts
435 cr4.vme = 0; // Virtual-8086 Mode Extensions
436
437 tc->setMiscReg(MISCREG_CR4, cr4);
438
439 CR4 cr8 = 0;
440 tc->setMiscReg(MISCREG_CR8, cr8);
441
442 tc->setMiscReg(MISCREG_MXCSR, 0x1f80);
443
444 tc->setMiscReg(MISCREG_APIC_BASE, 0xfee00900);
445
446 tc->setMiscReg(MISCREG_TSG_BASE, GDTVirtAddr);
447 tc->setMiscReg(MISCREG_TSG_LIMIT, 0xffff);
448
449 tc->setMiscReg(MISCREG_IDTR_BASE, IDTVirtAddr);
450 tc->setMiscReg(MISCREG_IDTR_LIMIT, 0xffff);
451
452 /* enabling syscall and sysret */
453 RegVal star = ((RegVal)sret << 48) | ((RegVal)scall << 32);
454 tc->setMiscReg(MISCREG_STAR, star);
455 RegVal lstar = (RegVal)syscallCodeVirtAddr;
456 tc->setMiscReg(MISCREG_LSTAR, lstar);
457 RegVal sfmask = (1 << 8) | (1 << 10); // TF | DF
458 tc->setMiscReg(MISCREG_SF_MASK, sfmask);
459 }
460
461 /* Set up the content of the TSS and write it to physical memory. */
462
463 struct {
464 uint32_t reserved0; // +00h
465 uint32_t RSP0_low; // +04h
466 uint32_t RSP0_high; // +08h
467 uint32_t RSP1_low; // +0Ch
468 uint32_t RSP1_high; // +10h
469 uint32_t RSP2_low; // +14h
470 uint32_t RSP2_high; // +18h
471 uint32_t reserved1; // +1Ch
472 uint32_t reserved2; // +20h
473 uint32_t IST1_low; // +24h
474 uint32_t IST1_high; // +28h
475 uint32_t IST2_low; // +2Ch
476 uint32_t IST2_high; // +30h
477 uint32_t IST3_low; // +34h
478 uint32_t IST3_high; // +38h
479 uint32_t IST4_low; // +3Ch
480 uint32_t IST4_high; // +40h
481 uint32_t IST5_low; // +44h
482 uint32_t IST5_high; // +48h
483 uint32_t IST6_low; // +4Ch
484 uint32_t IST6_high; // +50h
485 uint32_t IST7_low; // +54h
486 uint32_t IST7_high; // +58h
487 uint32_t reserved3; // +5Ch
488 uint32_t reserved4; // +60h
489 uint16_t reserved5; // +64h
490 uint16_t IO_MapBase; // +66h
491 } tss;
492
493 /** setting Interrupt Stack Table */
494 uint64_t IST_start = ISTVirtAddr + PageBytes;
495 tss.IST1_low = IST_start;
496 tss.IST1_high = IST_start >> 32;
497 tss.RSP0_low = tss.IST1_low;
498 tss.RSP0_high = tss.IST1_high;
499 tss.RSP1_low = tss.IST1_low;
500 tss.RSP1_high = tss.IST1_high;
501 tss.RSP2_low = tss.IST1_low;
502 tss.RSP2_high = tss.IST1_high;
503 physProxy.writeBlob(tssPhysAddr, (uint8_t *)(&tss), sizeof(tss));
504
505 /* Setting IDT gates */
506 GateDescriptorLow PFGateLow = 0;
507 PFGateLow.offsetHigh = bits(PFHandlerVirtAddr, 31, 16);
508 PFGateLow.offsetLow = bits(PFHandlerVirtAddr, 15, 0);
509 PFGateLow.selector = csLowPL;
510 PFGateLow.p = 1;
511 PFGateLow.dpl = 0;
512 PFGateLow.type = 0xe; // gate interrupt type
513 PFGateLow.IST = 0; // setting IST to 0 and using RSP0
514
515 GateDescriptorHigh PFGateHigh = 0;
516 PFGateHigh.offset = bits(PFHandlerVirtAddr, 63, 32);
517
518 struct {
519 uint64_t low;
520 uint64_t high;
521 } PFGate = {PFGateLow, PFGateHigh};
522
523 physProxy.writeBlob(idtPhysAddr + 0xE0,
524 (uint8_t *)(&PFGate), sizeof(PFGate));
525
526 /* System call handler */
527 uint8_t syscallBlob[] = {
528 // mov %rax, (0xffffc90000005600)
529 0x48, 0xa3, 0x00, 0x60, 0x00,
530 0x00, 0x00, 0xc9, 0xff, 0xff,
531 // sysret
532 0x48, 0x0f, 0x07
533 };
534
535 physProxy.writeBlob(syscallCodePhysAddr,
536 syscallBlob, sizeof(syscallBlob));
537
538 /** Page fault handler */
539 uint8_t faultBlob[] = {
540 // mov %rax, (0xffffc90000005700)
541 0x48, 0xa3, 0x00, 0x61, 0x00,
542 0x00, 0x00, 0xc9, 0xff, 0xff,
543 // add $0x8, %rsp # skip error
544 0x48, 0x83, 0xc4, 0x08,
545 // iretq
546 0x48, 0xcf
547 };
548
549 physProxy.writeBlob(pfHandlerPhysAddr, faultBlob, sizeof(faultBlob));
550
551 /* Syscall handler */
552 pTable->map(syscallCodeVirtAddr, syscallCodePhysAddr,
553 PageBytes, false);
554 /* GDT */
555 pTable->map(GDTVirtAddr, gdtPhysAddr, PageBytes, false);
556 /* IDT */
557 pTable->map(IDTVirtAddr, idtPhysAddr, PageBytes, false);
558 /* TSS */
559 pTable->map(TSSVirtAddr, tssPhysAddr, PageBytes, false);
560 /* IST */
561 pTable->map(ISTVirtAddr, istPhysAddr, PageBytes, false);
562 /* PF handler */
563 pTable->map(PFHandlerVirtAddr, pfHandlerPhysAddr, PageBytes, false);
564 /* MMIO region for m5ops */
565 pTable->map(MMIORegionVirtAddr, MMIORegionPhysAddr,
566 16 * PageBytes, false);
567 } else {
568 for (int i = 0; i < contextIds.size(); i++) {
569 ThreadContext * tc = system->getThreadContext(contextIds[i]);
570
571 SegAttr dataAttr = 0;
572 dataAttr.dpl = 3;
573 dataAttr.unusable = 0;
574 dataAttr.defaultSize = 1;
575 dataAttr.longMode = 1;
576 dataAttr.avl = 0;
577 dataAttr.granularity = 1;
578 dataAttr.present = 1;
579 dataAttr.type = 3;
580 dataAttr.writable = 1;
581 dataAttr.readable = 1;
582 dataAttr.expandDown = 0;
583 dataAttr.system = 1;
584
585 // Initialize the segment registers.
586 for (int seg = 0; seg < NUM_SEGMENTREGS; seg++) {
587 tc->setMiscRegNoEffect(MISCREG_SEG_BASE(seg), 0);
588 tc->setMiscRegNoEffect(MISCREG_SEG_EFF_BASE(seg), 0);
589 tc->setMiscRegNoEffect(MISCREG_SEG_ATTR(seg), dataAttr);
590 }
591
592 SegAttr csAttr = 0;
593 csAttr.dpl = 3;
594 csAttr.unusable = 0;
595 csAttr.defaultSize = 0;
596 csAttr.longMode = 1;
597 csAttr.avl = 0;
598 csAttr.granularity = 1;
599 csAttr.present = 1;
600 csAttr.type = 10;
601 csAttr.writable = 0;
602 csAttr.readable = 1;
603 csAttr.expandDown = 0;
604 csAttr.system = 1;
605
606 tc->setMiscRegNoEffect(MISCREG_CS_ATTR, csAttr);
607
608 Efer efer = 0;
609 efer.sce = 1; // Enable system call extensions.
610 efer.lme = 1; // Enable long mode.
611 efer.lma = 1; // Activate long mode.
612 efer.nxe = 1; // Enable nx support.
613 efer.svme = 0; // Disable svm support for now. It isn't implemented.
614 efer.ffxsr = 1; // Turn on fast fxsave and fxrstor.
615 tc->setMiscReg(MISCREG_EFER, efer);
616
617 // Set up the registers that describe the operating mode.
618 CR0 cr0 = 0;
619 cr0.pg = 1; // Turn on paging.
620 cr0.cd = 0; // Don't disable caching.
621 cr0.nw = 0; // This is bit is defined to be ignored.
622 cr0.am = 0; // No alignment checking
623 cr0.wp = 0; // Supervisor mode can write read only pages
624 cr0.ne = 1;
625 cr0.et = 1; // This should always be 1
626 cr0.ts = 0; // We don't do task switching, so causing fp exceptions
627 // would be pointless.
628 cr0.em = 0; // Allow x87 instructions to execute natively.
629 cr0.mp = 1; // This doesn't really matter, but the manual suggests
630 // setting it to one.
631 cr0.pe = 1; // We're definitely in protected mode.
632 tc->setMiscReg(MISCREG_CR0, cr0);
633
634 tc->setMiscReg(MISCREG_MXCSR, 0x1f80);
635 }
636 }
637}
638
639void
640I386Process::initState()
641{
642 X86Process::initState();
643
644 argsInit(PageBytes);
645
646 /*
647 * Set up a GDT for this process. The whole GDT wouldn't really be for
648 * this process, but the only parts we care about are.
649 */
650 allocateMem(_gdtStart, _gdtSize);
651 uint64_t zero = 0;
652 assert(_gdtSize % sizeof(zero) == 0);
653 for (Addr gdtCurrent = _gdtStart;
654 gdtCurrent < _gdtStart + _gdtSize; gdtCurrent += sizeof(zero)) {
655 initVirtMem.write(gdtCurrent, zero);
656 }
657
658 // Set up the vsyscall page for this process.
659 allocateMem(vsyscallPage.base, vsyscallPage.size);
660 uint8_t vsyscallBlob[] = {
661 0x51, // push %ecx
662 0x52, // push %edp
663 0x55, // push %ebp
664 0x89, 0xe5, // mov %esp, %ebp
665 0x0f, 0x34 // sysenter
666 };
667 initVirtMem.writeBlob(vsyscallPage.base + vsyscallPage.vsyscallOffset,
668 vsyscallBlob, sizeof(vsyscallBlob));
669
670 uint8_t vsysexitBlob[] = {
671 0x5d, // pop %ebp
672 0x5a, // pop %edx
673 0x59, // pop %ecx
674 0xc3 // ret
675 };
676 initVirtMem.writeBlob(vsyscallPage.base + vsyscallPage.vsysexitOffset,
677 vsysexitBlob, sizeof(vsysexitBlob));
678
679 for (int i = 0; i < contextIds.size(); i++) {
680 ThreadContext * tc = system->getThreadContext(contextIds[i]);
681
682 SegAttr dataAttr = 0;
683 dataAttr.dpl = 3;
684 dataAttr.unusable = 0;
685 dataAttr.defaultSize = 1;
686 dataAttr.longMode = 0;
687 dataAttr.avl = 0;
688 dataAttr.granularity = 1;
689 dataAttr.present = 1;
690 dataAttr.type = 3;
691 dataAttr.writable = 1;
692 dataAttr.readable = 1;
693 dataAttr.expandDown = 0;
694 dataAttr.system = 1;
695
696 // Initialize the segment registers.
697 for (int seg = 0; seg < NUM_SEGMENTREGS; seg++) {
698 tc->setMiscRegNoEffect(MISCREG_SEG_BASE(seg), 0);
699 tc->setMiscRegNoEffect(MISCREG_SEG_EFF_BASE(seg), 0);
700 tc->setMiscRegNoEffect(MISCREG_SEG_ATTR(seg), dataAttr);
701 tc->setMiscRegNoEffect(MISCREG_SEG_SEL(seg), 0xB);
702 tc->setMiscRegNoEffect(MISCREG_SEG_LIMIT(seg), (uint32_t)(-1));
703 }
704
705 SegAttr csAttr = 0;
706 csAttr.dpl = 3;
707 csAttr.unusable = 0;
708 csAttr.defaultSize = 1;
709 csAttr.longMode = 0;
710 csAttr.avl = 0;
711 csAttr.granularity = 1;
712 csAttr.present = 1;
713 csAttr.type = 0xa;
714 csAttr.writable = 0;
715 csAttr.readable = 1;
716 csAttr.expandDown = 0;
717 csAttr.system = 1;
718
719 tc->setMiscRegNoEffect(MISCREG_CS_ATTR, csAttr);
720
721 tc->setMiscRegNoEffect(MISCREG_TSG_BASE, _gdtStart);
722 tc->setMiscRegNoEffect(MISCREG_TSG_EFF_BASE, _gdtStart);
723 tc->setMiscRegNoEffect(MISCREG_TSG_LIMIT, _gdtStart + _gdtSize - 1);
724
725 // Set the LDT selector to 0 to deactivate it.
726 tc->setMiscRegNoEffect(MISCREG_TSL, 0);
727
728 Efer efer = 0;
729 efer.sce = 1; // Enable system call extensions.
730 efer.lme = 1; // Enable long mode.
731 efer.lma = 0; // Deactivate long mode.
732 efer.nxe = 1; // Enable nx support.
733 efer.svme = 0; // Disable svm support for now. It isn't implemented.
734 efer.ffxsr = 1; // Turn on fast fxsave and fxrstor.
735 tc->setMiscReg(MISCREG_EFER, efer);
736
737 // Set up the registers that describe the operating mode.
738 CR0 cr0 = 0;
739 cr0.pg = 1; // Turn on paging.
740 cr0.cd = 0; // Don't disable caching.
741 cr0.nw = 0; // This is bit is defined to be ignored.
742 cr0.am = 0; // No alignment checking
743 cr0.wp = 0; // Supervisor mode can write read only pages
744 cr0.ne = 1;
745 cr0.et = 1; // This should always be 1
746 cr0.ts = 0; // We don't do task switching, so causing fp exceptions
747 // would be pointless.
748 cr0.em = 0; // Allow x87 instructions to execute natively.
749 cr0.mp = 1; // This doesn't really matter, but the manual suggests
750 // setting it to one.
751 cr0.pe = 1; // We're definitely in protected mode.
752 tc->setMiscReg(MISCREG_CR0, cr0);
753
754 tc->setMiscReg(MISCREG_MXCSR, 0x1f80);
755 }
756}
757
758template<class IntType>
759void
760X86Process::argsInit(int pageSize,
761 std::vector<AuxVector<IntType> > extraAuxvs)
762{
763 int intSize = sizeof(IntType);
764
765 typedef AuxVector<IntType> auxv_t;
766 std::vector<auxv_t> auxv = extraAuxvs;
765 std::vector<AuxVector<IntType>> auxv = extraAuxvs;
767
768 string filename;
769 if (argv.size() < 1)
770 filename = "";
771 else
772 filename = argv[0];
773
774 // We want 16 byte alignment
775 uint64_t align = 16;
776
777 // Patch the ld_bias for dynamic executables.
778 updateBias();
779
780 // load object file into target memory
781 objFile->loadSections(initVirtMem);
782
783 enum X86CpuFeature {
784 X86_OnboardFPU = 1 << 0,
785 X86_VirtualModeExtensions = 1 << 1,
786 X86_DebuggingExtensions = 1 << 2,
787 X86_PageSizeExtensions = 1 << 3,
788
789 X86_TimeStampCounter = 1 << 4,
790 X86_ModelSpecificRegisters = 1 << 5,
791 X86_PhysicalAddressExtensions = 1 << 6,
792 X86_MachineCheckExtensions = 1 << 7,
793
794 X86_CMPXCHG8Instruction = 1 << 8,
795 X86_OnboardAPIC = 1 << 9,
796 X86_SYSENTER_SYSEXIT = 1 << 11,
797
798 X86_MemoryTypeRangeRegisters = 1 << 12,
799 X86_PageGlobalEnable = 1 << 13,
800 X86_MachineCheckArchitecture = 1 << 14,
801 X86_CMOVInstruction = 1 << 15,
802
803 X86_PageAttributeTable = 1 << 16,
804 X86_36BitPSEs = 1 << 17,
805 X86_ProcessorSerialNumber = 1 << 18,
806 X86_CLFLUSHInstruction = 1 << 19,
807
808 X86_DebugTraceStore = 1 << 21,
809 X86_ACPIViaMSR = 1 << 22,
810 X86_MultimediaExtensions = 1 << 23,
811
812 X86_FXSAVE_FXRSTOR = 1 << 24,
813 X86_StreamingSIMDExtensions = 1 << 25,
814 X86_StreamingSIMDExtensions2 = 1 << 26,
815 X86_CPUSelfSnoop = 1 << 27,
816
817 X86_HyperThreading = 1 << 28,
818 X86_AutomaticClockControl = 1 << 29,
819 X86_IA64Processor = 1 << 30
820 };
821
822 // Setup the auxiliary vectors. These will already have endian
823 // conversion. Auxiliary vectors are loaded only for elf formatted
824 // executables; the auxv is responsible for passing information from
825 // the OS to the interpreter.
826 ElfObject * elfObject = dynamic_cast<ElfObject *>(objFile);
827 if (elfObject) {
828 uint64_t features =
829 X86_OnboardFPU |
830 X86_VirtualModeExtensions |
831 X86_DebuggingExtensions |
832 X86_PageSizeExtensions |
833 X86_TimeStampCounter |
834 X86_ModelSpecificRegisters |
835 X86_PhysicalAddressExtensions |
836 X86_MachineCheckExtensions |
837 X86_CMPXCHG8Instruction |
838 X86_OnboardAPIC |
839 X86_SYSENTER_SYSEXIT |
840 X86_MemoryTypeRangeRegisters |
841 X86_PageGlobalEnable |
842 X86_MachineCheckArchitecture |
843 X86_CMOVInstruction |
844 X86_PageAttributeTable |
845 X86_36BitPSEs |
846// X86_ProcessorSerialNumber |
847 X86_CLFLUSHInstruction |
848// X86_DebugTraceStore |
849// X86_ACPIViaMSR |
850 X86_MultimediaExtensions |
851 X86_FXSAVE_FXRSTOR |
852 X86_StreamingSIMDExtensions |
853 X86_StreamingSIMDExtensions2 |
854// X86_CPUSelfSnoop |
855// X86_HyperThreading |
856// X86_AutomaticClockControl |
857// X86_IA64Processor |
858 0;
859
860 // Bits which describe the system hardware capabilities
861 // XXX Figure out what these should be
766
767 string filename;
768 if (argv.size() < 1)
769 filename = "";
770 else
771 filename = argv[0];
772
773 // We want 16 byte alignment
774 uint64_t align = 16;
775
776 // Patch the ld_bias for dynamic executables.
777 updateBias();
778
779 // load object file into target memory
780 objFile->loadSections(initVirtMem);
781
782 enum X86CpuFeature {
783 X86_OnboardFPU = 1 << 0,
784 X86_VirtualModeExtensions = 1 << 1,
785 X86_DebuggingExtensions = 1 << 2,
786 X86_PageSizeExtensions = 1 << 3,
787
788 X86_TimeStampCounter = 1 << 4,
789 X86_ModelSpecificRegisters = 1 << 5,
790 X86_PhysicalAddressExtensions = 1 << 6,
791 X86_MachineCheckExtensions = 1 << 7,
792
793 X86_CMPXCHG8Instruction = 1 << 8,
794 X86_OnboardAPIC = 1 << 9,
795 X86_SYSENTER_SYSEXIT = 1 << 11,
796
797 X86_MemoryTypeRangeRegisters = 1 << 12,
798 X86_PageGlobalEnable = 1 << 13,
799 X86_MachineCheckArchitecture = 1 << 14,
800 X86_CMOVInstruction = 1 << 15,
801
802 X86_PageAttributeTable = 1 << 16,
803 X86_36BitPSEs = 1 << 17,
804 X86_ProcessorSerialNumber = 1 << 18,
805 X86_CLFLUSHInstruction = 1 << 19,
806
807 X86_DebugTraceStore = 1 << 21,
808 X86_ACPIViaMSR = 1 << 22,
809 X86_MultimediaExtensions = 1 << 23,
810
811 X86_FXSAVE_FXRSTOR = 1 << 24,
812 X86_StreamingSIMDExtensions = 1 << 25,
813 X86_StreamingSIMDExtensions2 = 1 << 26,
814 X86_CPUSelfSnoop = 1 << 27,
815
816 X86_HyperThreading = 1 << 28,
817 X86_AutomaticClockControl = 1 << 29,
818 X86_IA64Processor = 1 << 30
819 };
820
821 // Setup the auxiliary vectors. These will already have endian
822 // conversion. Auxiliary vectors are loaded only for elf formatted
823 // executables; the auxv is responsible for passing information from
824 // the OS to the interpreter.
825 ElfObject * elfObject = dynamic_cast<ElfObject *>(objFile);
826 if (elfObject) {
827 uint64_t features =
828 X86_OnboardFPU |
829 X86_VirtualModeExtensions |
830 X86_DebuggingExtensions |
831 X86_PageSizeExtensions |
832 X86_TimeStampCounter |
833 X86_ModelSpecificRegisters |
834 X86_PhysicalAddressExtensions |
835 X86_MachineCheckExtensions |
836 X86_CMPXCHG8Instruction |
837 X86_OnboardAPIC |
838 X86_SYSENTER_SYSEXIT |
839 X86_MemoryTypeRangeRegisters |
840 X86_PageGlobalEnable |
841 X86_MachineCheckArchitecture |
842 X86_CMOVInstruction |
843 X86_PageAttributeTable |
844 X86_36BitPSEs |
845// X86_ProcessorSerialNumber |
846 X86_CLFLUSHInstruction |
847// X86_DebugTraceStore |
848// X86_ACPIViaMSR |
849 X86_MultimediaExtensions |
850 X86_FXSAVE_FXRSTOR |
851 X86_StreamingSIMDExtensions |
852 X86_StreamingSIMDExtensions2 |
853// X86_CPUSelfSnoop |
854// X86_HyperThreading |
855// X86_AutomaticClockControl |
856// X86_IA64Processor |
857 0;
858
859 // Bits which describe the system hardware capabilities
860 // XXX Figure out what these should be
862 auxv.push_back(auxv_t(M5_AT_HWCAP, features));
861 auxv.emplace_back(M5_AT_HWCAP, features);
863 // The system page size
862 // The system page size
864 auxv.push_back(auxv_t(M5_AT_PAGESZ, X86ISA::PageBytes));
863 auxv.emplace_back(M5_AT_PAGESZ, X86ISA::PageBytes);
865 // Frequency at which times() increments
866 // Defined to be 100 in the kernel source.
864 // Frequency at which times() increments
865 // Defined to be 100 in the kernel source.
867 auxv.push_back(auxv_t(M5_AT_CLKTCK, 100));
866 auxv.emplace_back(M5_AT_CLKTCK, 100);
868 // This is the virtual address of the program header tables if they
869 // appear in the executable image.
867 // This is the virtual address of the program header tables if they
868 // appear in the executable image.
870 auxv.push_back(auxv_t(M5_AT_PHDR, elfObject->programHeaderTable()));
869 auxv.emplace_back(M5_AT_PHDR, elfObject->programHeaderTable());
871 // This is the size of a program header entry from the elf file.
870 // This is the size of a program header entry from the elf file.
872 auxv.push_back(auxv_t(M5_AT_PHENT, elfObject->programHeaderSize()));
871 auxv.emplace_back(M5_AT_PHENT, elfObject->programHeaderSize());
873 // This is the number of program headers from the original elf file.
872 // This is the number of program headers from the original elf file.
874 auxv.push_back(auxv_t(M5_AT_PHNUM, elfObject->programHeaderCount()));
873 auxv.emplace_back(M5_AT_PHNUM, elfObject->programHeaderCount());
875 // This is the base address of the ELF interpreter; it should be
876 // zero for static executables or contain the base address for
877 // dynamic executables.
874 // This is the base address of the ELF interpreter; it should be
875 // zero for static executables or contain the base address for
876 // dynamic executables.
878 auxv.push_back(auxv_t(M5_AT_BASE, getBias()));
877 auxv.emplace_back(M5_AT_BASE, getBias());
879 // XXX Figure out what this should be.
878 // XXX Figure out what this should be.
880 auxv.push_back(auxv_t(M5_AT_FLAGS, 0));
879 auxv.emplace_back(M5_AT_FLAGS, 0);
881 // The entry point to the program
880 // The entry point to the program
882 auxv.push_back(auxv_t(M5_AT_ENTRY, objFile->entryPoint()));
881 auxv.emplace_back(M5_AT_ENTRY, objFile->entryPoint());
883 // Different user and group IDs
882 // Different user and group IDs
884 auxv.push_back(auxv_t(M5_AT_UID, uid()));
885 auxv.push_back(auxv_t(M5_AT_EUID, euid()));
886 auxv.push_back(auxv_t(M5_AT_GID, gid()));
887 auxv.push_back(auxv_t(M5_AT_EGID, egid()));
883 auxv.emplace_back(M5_AT_UID, uid());
884 auxv.emplace_back(M5_AT_EUID, euid());
885 auxv.emplace_back(M5_AT_GID, gid());
886 auxv.emplace_back(M5_AT_EGID, egid());
888 // Whether to enable "secure mode" in the executable
887 // Whether to enable "secure mode" in the executable
889 auxv.push_back(auxv_t(M5_AT_SECURE, 0));
888 auxv.emplace_back(M5_AT_SECURE, 0);
890 // The address of 16 "random" bytes.
889 // The address of 16 "random" bytes.
891 auxv.push_back(auxv_t(M5_AT_RANDOM, 0));
890 auxv.emplace_back(M5_AT_RANDOM, 0);
892 // The name of the program
891 // The name of the program
893 auxv.push_back(auxv_t(M5_AT_EXECFN, 0));
892 auxv.emplace_back(M5_AT_EXECFN, 0);
894 // The platform string
893 // The platform string
895 auxv.push_back(auxv_t(M5_AT_PLATFORM, 0));
894 auxv.emplace_back(M5_AT_PLATFORM, 0);
896 }
897
898 // Figure out how big the initial stack needs to be
899
900 // A sentry NULL void pointer at the top of the stack.
901 int sentry_size = intSize;
902
903 // This is the name of the file which is present on the initial stack
904 // It's purpose is to let the user space linker examine the original file.
905 int file_name_size = filename.size() + 1;
906
907 const int numRandomBytes = 16;
908 int aux_data_size = numRandomBytes;
909
910 string platform = "x86_64";
911 aux_data_size += platform.size() + 1;
912
913 int env_data_size = 0;
914 for (int i = 0; i < envp.size(); ++i)
915 env_data_size += envp[i].size() + 1;
916 int arg_data_size = 0;
917 for (int i = 0; i < argv.size(); ++i)
918 arg_data_size += argv[i].size() + 1;
919
920 // The info_block needs to be padded so its size is a multiple of the
921 // alignment mask. Also, it appears that there needs to be at least some
922 // padding, so if the size is already a multiple, we need to increase it
923 // anyway.
924 int base_info_block_size =
925 sentry_size + file_name_size + env_data_size + arg_data_size;
926
927 int info_block_size = roundUp(base_info_block_size, align);
928
929 int info_block_padding = info_block_size - base_info_block_size;
930
931 // Each auxiliary vector is two 8 byte words
932 int aux_array_size = intSize * 2 * (auxv.size() + 1);
933
934 int envp_array_size = intSize * (envp.size() + 1);
935 int argv_array_size = intSize * (argv.size() + 1);
936
937 int argc_size = intSize;
938
939 // Figure out the size of the contents of the actual initial frame
940 int frame_size =
941 aux_array_size +
942 envp_array_size +
943 argv_array_size +
944 argc_size;
945
946 // There needs to be padding after the auxiliary vector data so that the
947 // very bottom of the stack is aligned properly.
948 int partial_size = frame_size + aux_data_size;
949 int aligned_partial_size = roundUp(partial_size, align);
950 int aux_padding = aligned_partial_size - partial_size;
951
952 int space_needed =
953 info_block_size +
954 aux_data_size +
955 aux_padding +
956 frame_size;
957
958 Addr stack_base = memState->getStackBase();
959
960 Addr stack_min = stack_base - space_needed;
961 stack_min = roundDown(stack_min, align);
962
963 unsigned stack_size = stack_base - stack_min;
964 stack_size = roundUp(stack_size, pageSize);
965 memState->setStackSize(stack_size);
966
967 // map memory
968 Addr stack_end = roundDown(stack_base - stack_size, pageSize);
969
970 DPRINTF(Stack, "Mapping the stack: 0x%x %dB\n", stack_end, stack_size);
971 allocateMem(stack_end, stack_size);
972
973 // map out initial stack contents
974 IntType sentry_base = stack_base - sentry_size;
975 IntType file_name_base = sentry_base - file_name_size;
976 IntType env_data_base = file_name_base - env_data_size;
977 IntType arg_data_base = env_data_base - arg_data_size;
978 IntType aux_data_base = arg_data_base - info_block_padding - aux_data_size;
979 IntType auxv_array_base = aux_data_base - aux_array_size - aux_padding;
980 IntType envp_array_base = auxv_array_base - envp_array_size;
981 IntType argv_array_base = envp_array_base - argv_array_size;
982 IntType argc_base = argv_array_base - argc_size;
983
984 DPRINTF(Stack, "The addresses of items on the initial stack:\n");
985 DPRINTF(Stack, "0x%x - file name\n", file_name_base);
986 DPRINTF(Stack, "0x%x - env data\n", env_data_base);
987 DPRINTF(Stack, "0x%x - arg data\n", arg_data_base);
988 DPRINTF(Stack, "0x%x - aux data\n", aux_data_base);
989 DPRINTF(Stack, "0x%x - auxv array\n", auxv_array_base);
990 DPRINTF(Stack, "0x%x - envp array\n", envp_array_base);
991 DPRINTF(Stack, "0x%x - argv array\n", argv_array_base);
992 DPRINTF(Stack, "0x%x - argc \n", argc_base);
993 DPRINTF(Stack, "0x%x - stack min\n", stack_min);
994
995 // write contents to stack
996
997 // figure out argc
998 IntType argc = argv.size();
999 IntType guestArgc = X86ISA::htog(argc);
1000
1001 // Write out the sentry void *
1002 IntType sentry_NULL = 0;
1003 initVirtMem.writeBlob(sentry_base, (uint8_t*)&sentry_NULL, sentry_size);
1004
1005 // Write the file name
1006 initVirtMem.writeString(file_name_base, filename.c_str());
1007
1008 // Fix up the aux vectors which point to data
895 }
896
897 // Figure out how big the initial stack needs to be
898
899 // A sentry NULL void pointer at the top of the stack.
900 int sentry_size = intSize;
901
902 // This is the name of the file which is present on the initial stack
903 // It's purpose is to let the user space linker examine the original file.
904 int file_name_size = filename.size() + 1;
905
906 const int numRandomBytes = 16;
907 int aux_data_size = numRandomBytes;
908
909 string platform = "x86_64";
910 aux_data_size += platform.size() + 1;
911
912 int env_data_size = 0;
913 for (int i = 0; i < envp.size(); ++i)
914 env_data_size += envp[i].size() + 1;
915 int arg_data_size = 0;
916 for (int i = 0; i < argv.size(); ++i)
917 arg_data_size += argv[i].size() + 1;
918
919 // The info_block needs to be padded so its size is a multiple of the
920 // alignment mask. Also, it appears that there needs to be at least some
921 // padding, so if the size is already a multiple, we need to increase it
922 // anyway.
923 int base_info_block_size =
924 sentry_size + file_name_size + env_data_size + arg_data_size;
925
926 int info_block_size = roundUp(base_info_block_size, align);
927
928 int info_block_padding = info_block_size - base_info_block_size;
929
930 // Each auxiliary vector is two 8 byte words
931 int aux_array_size = intSize * 2 * (auxv.size() + 1);
932
933 int envp_array_size = intSize * (envp.size() + 1);
934 int argv_array_size = intSize * (argv.size() + 1);
935
936 int argc_size = intSize;
937
938 // Figure out the size of the contents of the actual initial frame
939 int frame_size =
940 aux_array_size +
941 envp_array_size +
942 argv_array_size +
943 argc_size;
944
945 // There needs to be padding after the auxiliary vector data so that the
946 // very bottom of the stack is aligned properly.
947 int partial_size = frame_size + aux_data_size;
948 int aligned_partial_size = roundUp(partial_size, align);
949 int aux_padding = aligned_partial_size - partial_size;
950
951 int space_needed =
952 info_block_size +
953 aux_data_size +
954 aux_padding +
955 frame_size;
956
957 Addr stack_base = memState->getStackBase();
958
959 Addr stack_min = stack_base - space_needed;
960 stack_min = roundDown(stack_min, align);
961
962 unsigned stack_size = stack_base - stack_min;
963 stack_size = roundUp(stack_size, pageSize);
964 memState->setStackSize(stack_size);
965
966 // map memory
967 Addr stack_end = roundDown(stack_base - stack_size, pageSize);
968
969 DPRINTF(Stack, "Mapping the stack: 0x%x %dB\n", stack_end, stack_size);
970 allocateMem(stack_end, stack_size);
971
972 // map out initial stack contents
973 IntType sentry_base = stack_base - sentry_size;
974 IntType file_name_base = sentry_base - file_name_size;
975 IntType env_data_base = file_name_base - env_data_size;
976 IntType arg_data_base = env_data_base - arg_data_size;
977 IntType aux_data_base = arg_data_base - info_block_padding - aux_data_size;
978 IntType auxv_array_base = aux_data_base - aux_array_size - aux_padding;
979 IntType envp_array_base = auxv_array_base - envp_array_size;
980 IntType argv_array_base = envp_array_base - argv_array_size;
981 IntType argc_base = argv_array_base - argc_size;
982
983 DPRINTF(Stack, "The addresses of items on the initial stack:\n");
984 DPRINTF(Stack, "0x%x - file name\n", file_name_base);
985 DPRINTF(Stack, "0x%x - env data\n", env_data_base);
986 DPRINTF(Stack, "0x%x - arg data\n", arg_data_base);
987 DPRINTF(Stack, "0x%x - aux data\n", aux_data_base);
988 DPRINTF(Stack, "0x%x - auxv array\n", auxv_array_base);
989 DPRINTF(Stack, "0x%x - envp array\n", envp_array_base);
990 DPRINTF(Stack, "0x%x - argv array\n", argv_array_base);
991 DPRINTF(Stack, "0x%x - argc \n", argc_base);
992 DPRINTF(Stack, "0x%x - stack min\n", stack_min);
993
994 // write contents to stack
995
996 // figure out argc
997 IntType argc = argv.size();
998 IntType guestArgc = X86ISA::htog(argc);
999
1000 // Write out the sentry void *
1001 IntType sentry_NULL = 0;
1002 initVirtMem.writeBlob(sentry_base, (uint8_t*)&sentry_NULL, sentry_size);
1003
1004 // Write the file name
1005 initVirtMem.writeString(file_name_base, filename.c_str());
1006
1007 // Fix up the aux vectors which point to data
1009 assert(auxv[auxv.size() - 3].getHostAuxType() == M5_AT_RANDOM);
1010 auxv[auxv.size() - 3].setAuxVal(aux_data_base);
1011 assert(auxv[auxv.size() - 2].getHostAuxType() == M5_AT_EXECFN);
1012 auxv[auxv.size() - 2].setAuxVal(argv_array_base);
1013 assert(auxv[auxv.size() - 1].getHostAuxType() == M5_AT_PLATFORM);
1014 auxv[auxv.size() - 1].setAuxVal(aux_data_base + numRandomBytes);
1008 assert(auxv[auxv.size() - 3].type == M5_AT_RANDOM);
1009 auxv[auxv.size() - 3].val = aux_data_base;
1010 assert(auxv[auxv.size() - 2].type == M5_AT_EXECFN);
1011 auxv[auxv.size() - 2].val = argv_array_base;
1012 assert(auxv[auxv.size() - 1].type == M5_AT_PLATFORM);
1013 auxv[auxv.size() - 1].val = aux_data_base + numRandomBytes;
1015
1016
1017 // Copy the aux stuff
1014
1015
1016 // Copy the aux stuff
1018 for (int x = 0; x < auxv.size(); x++) {
1019 initVirtMem.writeBlob(auxv_array_base + x * 2 * intSize,
1020 (uint8_t*)&(auxv[x].getAuxType()),
1021 intSize);
1022 initVirtMem.writeBlob(auxv_array_base + (x * 2 + 1) * intSize,
1023 (uint8_t*)&(auxv[x].getAuxVal()),
1024 intSize);
1017 Addr auxv_array_end = auxv_array_base;
1018 for (const auto &aux: auxv) {
1019 initVirtMem.write(auxv_array_end, aux, GuestByteOrder);
1020 auxv_array_end += sizeof(aux);
1025 }
1026 // Write out the terminating zeroed auxiliary vector
1021 }
1022 // Write out the terminating zeroed auxiliary vector
1027 const uint64_t zero = 0;
1028 initVirtMem.writeBlob(auxv_array_base + auxv.size() * 2 * intSize,
1029 (uint8_t*)&zero, intSize);
1030 initVirtMem.writeBlob(auxv_array_base + (auxv.size() * 2 + 1) * intSize,
1031 (uint8_t*)&zero, intSize);
1023 const AuxVector<uint64_t> zero(0, 0);
1024 initVirtMem.write(auxv_array_end, zero);
1025 auxv_array_end += sizeof(zero);
1032
1033 initVirtMem.writeString(aux_data_base, platform.c_str());
1034
1035 copyStringArray(envp, envp_array_base, env_data_base, initVirtMem);
1036 copyStringArray(argv, argv_array_base, arg_data_base, initVirtMem);
1037
1038 initVirtMem.writeBlob(argc_base, (uint8_t*)&guestArgc, intSize);
1039
1040 ThreadContext *tc = system->getThreadContext(contextIds[0]);
1041 // Set the stack pointer register
1042 tc->setIntReg(StackPointerReg, stack_min);
1043
1044 // There doesn't need to be any segment base added in since we're dealing
1045 // with the flat segmentation model.
1046 tc->pcState(getStartPC());
1047
1048 // Align the "stack_min" to a page boundary.
1049 memState->setStackMin(roundDown(stack_min, pageSize));
1050}
1051
1052void
1053X86_64Process::argsInit(int pageSize)
1054{
1055 std::vector<AuxVector<uint64_t> > extraAuxvs;
1026
1027 initVirtMem.writeString(aux_data_base, platform.c_str());
1028
1029 copyStringArray(envp, envp_array_base, env_data_base, initVirtMem);
1030 copyStringArray(argv, argv_array_base, arg_data_base, initVirtMem);
1031
1032 initVirtMem.writeBlob(argc_base, (uint8_t*)&guestArgc, intSize);
1033
1034 ThreadContext *tc = system->getThreadContext(contextIds[0]);
1035 // Set the stack pointer register
1036 tc->setIntReg(StackPointerReg, stack_min);
1037
1038 // There doesn't need to be any segment base added in since we're dealing
1039 // with the flat segmentation model.
1040 tc->pcState(getStartPC());
1041
1042 // Align the "stack_min" to a page boundary.
1043 memState->setStackMin(roundDown(stack_min, pageSize));
1044}
1045
1046void
1047X86_64Process::argsInit(int pageSize)
1048{
1049 std::vector<AuxVector<uint64_t> > extraAuxvs;
1056 extraAuxvs.push_back(AuxVector<uint64_t>(M5_AT_SYSINFO_EHDR,
1057 vsyscallPage.base));
1050 extraAuxvs.emplace_back(M5_AT_SYSINFO_EHDR, vsyscallPage.base);
1058 X86Process::argsInit<uint64_t>(pageSize, extraAuxvs);
1059}
1060
1061void
1062I386Process::argsInit(int pageSize)
1063{
1064 std::vector<AuxVector<uint32_t> > extraAuxvs;
1065 //Tell the binary where the vsyscall part of the vsyscall page is.
1051 X86Process::argsInit<uint64_t>(pageSize, extraAuxvs);
1052}
1053
1054void
1055I386Process::argsInit(int pageSize)
1056{
1057 std::vector<AuxVector<uint32_t> > extraAuxvs;
1058 //Tell the binary where the vsyscall part of the vsyscall page is.
1066 extraAuxvs.push_back(AuxVector<uint32_t>(M5_AT_SYSINFO,
1067 vsyscallPage.base + vsyscallPage.vsyscallOffset));
1068 extraAuxvs.push_back(AuxVector<uint32_t>(M5_AT_SYSINFO_EHDR,
1069 vsyscallPage.base));
1059 extraAuxvs.emplace_back(M5_AT_SYSINFO,
1060 vsyscallPage.base + vsyscallPage.vsyscallOffset);
1061 extraAuxvs.emplace_back(M5_AT_SYSINFO_EHDR, vsyscallPage.base);
1070 X86Process::argsInit<uint32_t>(pageSize, extraAuxvs);
1071}
1072
1073void
1074X86Process::setSyscallReturn(ThreadContext *tc, SyscallReturn retval)
1075{
1076 tc->setIntReg(INTREG_RAX, retval.encodedValue());
1077}
1078
1079RegVal
1080X86_64Process::getSyscallArg(ThreadContext *tc, int &i)
1081{
1082 assert(i < NumArgumentRegs);
1083 return tc->readIntReg(ArgumentReg[i++]);
1084}
1085
1086void
1087X86_64Process::setSyscallArg(ThreadContext *tc, int i, RegVal val)
1088{
1089 assert(i < NumArgumentRegs);
1090 return tc->setIntReg(ArgumentReg[i], val);
1091}
1092
1093void
1094X86_64Process::clone(ThreadContext *old_tc, ThreadContext *new_tc,
1095 Process *p, RegVal flags)
1096{
1097 X86Process::clone(old_tc, new_tc, p, flags);
1098 ((X86_64Process*)p)->vsyscallPage = vsyscallPage;
1099}
1100
1101RegVal
1102I386Process::getSyscallArg(ThreadContext *tc, int &i)
1103{
1104 assert(i < NumArgumentRegs32);
1105 return tc->readIntReg(ArgumentReg32[i++]);
1106}
1107
1108RegVal
1109I386Process::getSyscallArg(ThreadContext *tc, int &i, int width)
1110{
1111 assert(width == 32 || width == 64);
1112 assert(i < NumArgumentRegs);
1113 uint64_t retVal = tc->readIntReg(ArgumentReg32[i++]) & mask(32);
1114 if (width == 64)
1115 retVal |= ((uint64_t)tc->readIntReg(ArgumentReg[i++]) << 32);
1116 return retVal;
1117}
1118
1119void
1120I386Process::setSyscallArg(ThreadContext *tc, int i, RegVal val)
1121{
1122 assert(i < NumArgumentRegs);
1123 return tc->setIntReg(ArgumentReg[i], val);
1124}
1125
1126void
1127I386Process::clone(ThreadContext *old_tc, ThreadContext *new_tc,
1128 Process *p, RegVal flags)
1129{
1130 X86Process::clone(old_tc, new_tc, p, flags);
1131 ((I386Process*)p)->vsyscallPage = vsyscallPage;
1132}
1062 X86Process::argsInit<uint32_t>(pageSize, extraAuxvs);
1063}
1064
1065void
1066X86Process::setSyscallReturn(ThreadContext *tc, SyscallReturn retval)
1067{
1068 tc->setIntReg(INTREG_RAX, retval.encodedValue());
1069}
1070
1071RegVal
1072X86_64Process::getSyscallArg(ThreadContext *tc, int &i)
1073{
1074 assert(i < NumArgumentRegs);
1075 return tc->readIntReg(ArgumentReg[i++]);
1076}
1077
1078void
1079X86_64Process::setSyscallArg(ThreadContext *tc, int i, RegVal val)
1080{
1081 assert(i < NumArgumentRegs);
1082 return tc->setIntReg(ArgumentReg[i], val);
1083}
1084
1085void
1086X86_64Process::clone(ThreadContext *old_tc, ThreadContext *new_tc,
1087 Process *p, RegVal flags)
1088{
1089 X86Process::clone(old_tc, new_tc, p, flags);
1090 ((X86_64Process*)p)->vsyscallPage = vsyscallPage;
1091}
1092
1093RegVal
1094I386Process::getSyscallArg(ThreadContext *tc, int &i)
1095{
1096 assert(i < NumArgumentRegs32);
1097 return tc->readIntReg(ArgumentReg32[i++]);
1098}
1099
1100RegVal
1101I386Process::getSyscallArg(ThreadContext *tc, int &i, int width)
1102{
1103 assert(width == 32 || width == 64);
1104 assert(i < NumArgumentRegs);
1105 uint64_t retVal = tc->readIntReg(ArgumentReg32[i++]) & mask(32);
1106 if (width == 64)
1107 retVal |= ((uint64_t)tc->readIntReg(ArgumentReg[i++]) << 32);
1108 return retVal;
1109}
1110
1111void
1112I386Process::setSyscallArg(ThreadContext *tc, int i, RegVal val)
1113{
1114 assert(i < NumArgumentRegs);
1115 return tc->setIntReg(ArgumentReg[i], val);
1116}
1117
1118void
1119I386Process::clone(ThreadContext *old_tc, ThreadContext *new_tc,
1120 Process *p, RegVal flags)
1121{
1122 X86Process::clone(old_tc, new_tc, p, flags);
1123 ((I386Process*)p)->vsyscallPage = vsyscallPage;
1124}