process.cc (12431:000549e1f497) process.cc (12432:2480d8b432f5)
1/*
2 * Copyright (c) 2014 Advanced Micro Devices, Inc.
3 * Copyright (c) 2007 The Hewlett-Packard Development Company
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2003-2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Gabe Black
42 * Ali Saidi
43 */
44
45#include "arch/x86/process.hh"
46
47#include <string>
48#include <vector>
49
50#include "arch/x86/isa_traits.hh"
51#include "arch/x86/regs/misc.hh"
52#include "arch/x86/regs/segment.hh"
53#include "arch/x86/system.hh"
54#include "arch/x86/types.hh"
55#include "base/loader/elf_object.hh"
56#include "base/loader/object_file.hh"
57#include "base/logging.hh"
58#include "base/trace.hh"
59#include "cpu/thread_context.hh"
60#include "debug/Stack.hh"
61#include "mem/multi_level_page_table.hh"
62#include "mem/page_table.hh"
63#include "params/Process.hh"
64#include "sim/aux_vector.hh"
65#include "sim/process_impl.hh"
66#include "sim/syscall_desc.hh"
67#include "sim/syscall_return.hh"
68#include "sim/system.hh"
69
70using namespace std;
71using namespace X86ISA;
72
73static const int ArgumentReg[] = {
74 INTREG_RDI,
75 INTREG_RSI,
76 INTREG_RDX,
77 // This argument register is r10 for syscalls and rcx for C.
78 INTREG_R10W,
79 // INTREG_RCX,
80 INTREG_R8W,
81 INTREG_R9W
82};
83
84static const int NumArgumentRegs M5_VAR_USED =
85 sizeof(ArgumentReg) / sizeof(const int);
86
87static const int ArgumentReg32[] = {
88 INTREG_EBX,
89 INTREG_ECX,
90 INTREG_EDX,
91 INTREG_ESI,
92 INTREG_EDI,
93 INTREG_EBP
94};
95
96static const int NumArgumentRegs32 M5_VAR_USED =
97 sizeof(ArgumentReg) / sizeof(const int);
98
99X86Process::X86Process(ProcessParams *params, ObjectFile *objFile,
100 SyscallDesc *_syscallDescs, int _numSyscallDescs)
101 : Process(params, params->useArchPT ?
102 static_cast<PageTableBase *>(
103 new ArchPageTable(params->name, params->pid,
1/*
2 * Copyright (c) 2014 Advanced Micro Devices, Inc.
3 * Copyright (c) 2007 The Hewlett-Packard Development Company
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2003-2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Gabe Black
42 * Ali Saidi
43 */
44
45#include "arch/x86/process.hh"
46
47#include <string>
48#include <vector>
49
50#include "arch/x86/isa_traits.hh"
51#include "arch/x86/regs/misc.hh"
52#include "arch/x86/regs/segment.hh"
53#include "arch/x86/system.hh"
54#include "arch/x86/types.hh"
55#include "base/loader/elf_object.hh"
56#include "base/loader/object_file.hh"
57#include "base/logging.hh"
58#include "base/trace.hh"
59#include "cpu/thread_context.hh"
60#include "debug/Stack.hh"
61#include "mem/multi_level_page_table.hh"
62#include "mem/page_table.hh"
63#include "params/Process.hh"
64#include "sim/aux_vector.hh"
65#include "sim/process_impl.hh"
66#include "sim/syscall_desc.hh"
67#include "sim/syscall_return.hh"
68#include "sim/system.hh"
69
70using namespace std;
71using namespace X86ISA;
72
73static const int ArgumentReg[] = {
74 INTREG_RDI,
75 INTREG_RSI,
76 INTREG_RDX,
77 // This argument register is r10 for syscalls and rcx for C.
78 INTREG_R10W,
79 // INTREG_RCX,
80 INTREG_R8W,
81 INTREG_R9W
82};
83
84static const int NumArgumentRegs M5_VAR_USED =
85 sizeof(ArgumentReg) / sizeof(const int);
86
87static const int ArgumentReg32[] = {
88 INTREG_EBX,
89 INTREG_ECX,
90 INTREG_EDX,
91 INTREG_ESI,
92 INTREG_EDI,
93 INTREG_EBP
94};
95
96static const int NumArgumentRegs32 M5_VAR_USED =
97 sizeof(ArgumentReg) / sizeof(const int);
98
99X86Process::X86Process(ProcessParams *params, ObjectFile *objFile,
100 SyscallDesc *_syscallDescs, int _numSyscallDescs)
101 : Process(params, params->useArchPT ?
102 static_cast<PageTableBase *>(
103 new ArchPageTable(params->name, params->pid,
104 params->system)) :
104 params->system, PageBytes)) :
105 static_cast<PageTableBase *>(
105 static_cast<PageTableBase *>(
106 new FuncPageTable(params->name, params->pid)),
106 new FuncPageTable(params->name, params->pid,
107 PageBytes)),
107 objFile),
108 syscallDescs(_syscallDescs), numSyscallDescs(_numSyscallDescs)
109{
110}
111
112void X86Process::clone(ThreadContext *old_tc, ThreadContext *new_tc,
113 Process *p, TheISA::IntReg flags)
114{
115 Process::clone(old_tc, new_tc, p, flags);
116 X86Process *process = (X86Process*)p;
117 *process = *this;
118}
119
120X86_64Process::X86_64Process(ProcessParams *params, ObjectFile *objFile,
121 SyscallDesc *_syscallDescs, int _numSyscallDescs)
122 : X86Process(params, objFile, _syscallDescs, _numSyscallDescs)
123{
124
125 vsyscallPage.base = 0xffffffffff600000ULL;
126 vsyscallPage.size = PageBytes;
127 vsyscallPage.vtimeOffset = 0x400;
128 vsyscallPage.vgettimeofdayOffset = 0x0;
129
130 Addr brk_point = roundUp(objFile->dataBase() + objFile->dataSize() +
131 objFile->bssSize(), PageBytes);
132 Addr stack_base = 0x7FFFFFFFF000ULL;
133 Addr max_stack_size = 8 * 1024 * 1024;
134 Addr next_thread_stack_base = stack_base - max_stack_size;
135 Addr mmap_end = 0x7FFFF7FFF000ULL;
136
137 memState = make_shared<MemState>(brk_point, stack_base, max_stack_size,
138 next_thread_stack_base, mmap_end);
139}
140
141void
142I386Process::syscall(int64_t callnum, ThreadContext *tc, Fault *fault)
143{
144 TheISA::PCState pc = tc->pcState();
145 Addr eip = pc.pc();
146 if (eip >= vsyscallPage.base &&
147 eip < vsyscallPage.base + vsyscallPage.size) {
148 pc.npc(vsyscallPage.base + vsyscallPage.vsysexitOffset);
149 tc->pcState(pc);
150 }
151 X86Process::syscall(callnum, tc, fault);
152}
153
154
155I386Process::I386Process(ProcessParams *params, ObjectFile *objFile,
156 SyscallDesc *_syscallDescs, int _numSyscallDescs)
157 : X86Process(params, objFile, _syscallDescs, _numSyscallDescs)
158{
159 _gdtStart = ULL(0xffffd000);
160 _gdtSize = PageBytes;
161
162 vsyscallPage.base = 0xffffe000ULL;
163 vsyscallPage.size = PageBytes;
164 vsyscallPage.vsyscallOffset = 0x400;
165 vsyscallPage.vsysexitOffset = 0x410;
166
167 Addr brk_point = roundUp(objFile->dataBase() + objFile->dataSize() +
168 objFile->bssSize(), PageBytes);
169 Addr stack_base = _gdtStart;
170 Addr max_stack_size = 8 * 1024 * 1024;
171 Addr next_thread_stack_base = stack_base - max_stack_size;
172 Addr mmap_end = 0xB7FFF000ULL;
173
174 memState = make_shared<MemState>(brk_point, stack_base, max_stack_size,
175 next_thread_stack_base, mmap_end);
176}
177
178SyscallDesc*
179X86Process::getDesc(int callnum)
180{
181 if (callnum < 0 || callnum >= numSyscallDescs)
182 return NULL;
183 return &syscallDescs[callnum];
184}
185
186void
187X86_64Process::initState()
188{
189 X86Process::initState();
190
191 argsInit(PageBytes);
192
193 // Set up the vsyscall page for this process.
194 allocateMem(vsyscallPage.base, vsyscallPage.size);
195 uint8_t vtimeBlob[] = {
196 0x48,0xc7,0xc0,0xc9,0x00,0x00,0x00, // mov $0xc9,%rax
197 0x0f,0x05, // syscall
198 0xc3 // retq
199 };
200 initVirtMem.writeBlob(vsyscallPage.base + vsyscallPage.vtimeOffset,
201 vtimeBlob, sizeof(vtimeBlob));
202
203 uint8_t vgettimeofdayBlob[] = {
204 0x48,0xc7,0xc0,0x60,0x00,0x00,0x00, // mov $0x60,%rax
205 0x0f,0x05, // syscall
206 0xc3 // retq
207 };
208 initVirtMem.writeBlob(vsyscallPage.base + vsyscallPage.vgettimeofdayOffset,
209 vgettimeofdayBlob, sizeof(vgettimeofdayBlob));
210
211 if (kvmInSE) {
212 PortProxy physProxy = system->physProxy;
213
214 /*
215 * Set up the gdt.
216 */
217 uint8_t numGDTEntries = 0;
218 uint64_t nullDescriptor = 0;
219 physProxy.writeBlob(GDTPhysAddr + numGDTEntries * 8,
220 (uint8_t *)(&nullDescriptor), 8);
221 numGDTEntries++;
222
223 SegDescriptor initDesc = 0;
224 initDesc.type.codeOrData = 0; // code or data type
225 initDesc.type.c = 0; // conforming
226 initDesc.type.r = 1; // readable
227 initDesc.dpl = 0; // privilege
228 initDesc.p = 1; // present
229 initDesc.l = 1; // longmode - 64 bit
230 initDesc.d = 0; // operand size
231 initDesc.g = 1; // granularity
232 initDesc.s = 1; // system segment
233 initDesc.limitHigh = 0xFFFF;
234 initDesc.limitLow = 0xF;
235 initDesc.baseHigh = 0x0;
236 initDesc.baseLow = 0x0;
237
238 //64 bit code segment
239 SegDescriptor csLowPLDesc = initDesc;
240 csLowPLDesc.type.codeOrData = 1;
241 csLowPLDesc.dpl = 0;
242 uint64_t csLowPLDescVal = csLowPLDesc;
243 physProxy.writeBlob(GDTPhysAddr + numGDTEntries * 8,
244 (uint8_t *)(&csLowPLDescVal), 8);
245
246 numGDTEntries++;
247
248 SegSelector csLowPL = 0;
249 csLowPL.si = numGDTEntries - 1;
250 csLowPL.rpl = 0;
251
252 //64 bit data segment
253 SegDescriptor dsLowPLDesc = initDesc;
254 dsLowPLDesc.type.codeOrData = 0;
255 dsLowPLDesc.dpl = 0;
256 uint64_t dsLowPLDescVal = dsLowPLDesc;
257 physProxy.writeBlob(GDTPhysAddr + numGDTEntries * 8,
258 (uint8_t *)(&dsLowPLDescVal), 8);
259
260 numGDTEntries++;
261
262 SegSelector dsLowPL = 0;
263 dsLowPL.si = numGDTEntries - 1;
264 dsLowPL.rpl = 0;
265
266 //64 bit data segment
267 SegDescriptor dsDesc = initDesc;
268 dsDesc.type.codeOrData = 0;
269 dsDesc.dpl = 3;
270 uint64_t dsDescVal = dsDesc;
271 physProxy.writeBlob(GDTPhysAddr + numGDTEntries * 8,
272 (uint8_t *)(&dsDescVal), 8);
273
274 numGDTEntries++;
275
276 SegSelector ds = 0;
277 ds.si = numGDTEntries - 1;
278 ds.rpl = 3;
279
280 //64 bit code segment
281 SegDescriptor csDesc = initDesc;
282 csDesc.type.codeOrData = 1;
283 csDesc.dpl = 3;
284 uint64_t csDescVal = csDesc;
285 physProxy.writeBlob(GDTPhysAddr + numGDTEntries * 8,
286 (uint8_t *)(&csDescVal), 8);
287
288 numGDTEntries++;
289
290 SegSelector cs = 0;
291 cs.si = numGDTEntries - 1;
292 cs.rpl = 3;
293
294 SegSelector scall = 0;
295 scall.si = csLowPL.si;
296 scall.rpl = 0;
297
298 SegSelector sret = 0;
299 sret.si = dsLowPL.si;
300 sret.rpl = 3;
301
302 /* In long mode the TSS has been extended to 16 Bytes */
303 TSSlow TSSDescLow = 0;
304 TSSDescLow.type = 0xB;
305 TSSDescLow.dpl = 0; // Privelege level 0
306 TSSDescLow.p = 1; // Present
307 TSSDescLow.g = 1; // Page granularity
308 TSSDescLow.limitHigh = 0xF;
309 TSSDescLow.limitLow = 0xFFFF;
310 TSSDescLow.baseLow = bits(TSSVirtAddr, 23, 0);
311 TSSDescLow.baseHigh = bits(TSSVirtAddr, 31, 24);
312
313 TSShigh TSSDescHigh = 0;
314 TSSDescHigh.base = bits(TSSVirtAddr, 63, 32);
315
316 struct TSSDesc {
317 uint64_t low;
318 uint64_t high;
319 } tssDescVal = {TSSDescLow, TSSDescHigh};
320
321 physProxy.writeBlob(GDTPhysAddr + numGDTEntries * 8,
322 (uint8_t *)(&tssDescVal), sizeof(tssDescVal));
323
324 numGDTEntries++;
325
326 SegSelector tssSel = 0;
327 tssSel.si = numGDTEntries - 1;
328
329 uint64_t tss_base_addr = (TSSDescHigh.base << 32) |
330 (TSSDescLow.baseHigh << 24) |
331 TSSDescLow.baseLow;
332 uint64_t tss_limit = TSSDescLow.limitLow | (TSSDescLow.limitHigh << 16);
333
334 SegAttr tss_attr = 0;
335
336 tss_attr.type = TSSDescLow.type;
337 tss_attr.dpl = TSSDescLow.dpl;
338 tss_attr.present = TSSDescLow.p;
339 tss_attr.granularity = TSSDescLow.g;
340 tss_attr.unusable = 0;
341
342 for (int i = 0; i < contextIds.size(); i++) {
343 ThreadContext * tc = system->getThreadContext(contextIds[i]);
344
345 tc->setMiscReg(MISCREG_CS, cs);
346 tc->setMiscReg(MISCREG_DS, ds);
347 tc->setMiscReg(MISCREG_ES, ds);
348 tc->setMiscReg(MISCREG_FS, ds);
349 tc->setMiscReg(MISCREG_GS, ds);
350 tc->setMiscReg(MISCREG_SS, ds);
351
352 // LDT
353 tc->setMiscReg(MISCREG_TSL, 0);
354 SegAttr tslAttr = 0;
355 tslAttr.present = 1;
356 tslAttr.type = 2;
357 tc->setMiscReg(MISCREG_TSL_ATTR, tslAttr);
358
359 tc->setMiscReg(MISCREG_TSG_BASE, GDTVirtAddr);
360 tc->setMiscReg(MISCREG_TSG_LIMIT, 8 * numGDTEntries - 1);
361
362 tc->setMiscReg(MISCREG_TR, tssSel);
363 tc->setMiscReg(MISCREG_TR_BASE, tss_base_addr);
364 tc->setMiscReg(MISCREG_TR_EFF_BASE, 0);
365 tc->setMiscReg(MISCREG_TR_LIMIT, tss_limit);
366 tc->setMiscReg(MISCREG_TR_ATTR, tss_attr);
367
368 //Start using longmode segments.
369 installSegDesc(tc, SEGMENT_REG_CS, csDesc, true);
370 installSegDesc(tc, SEGMENT_REG_DS, dsDesc, true);
371 installSegDesc(tc, SEGMENT_REG_ES, dsDesc, true);
372 installSegDesc(tc, SEGMENT_REG_FS, dsDesc, true);
373 installSegDesc(tc, SEGMENT_REG_GS, dsDesc, true);
374 installSegDesc(tc, SEGMENT_REG_SS, dsDesc, true);
375
376 Efer efer = 0;
377 efer.sce = 1; // Enable system call extensions.
378 efer.lme = 1; // Enable long mode.
379 efer.lma = 1; // Activate long mode.
380 efer.nxe = 0; // Enable nx support.
381 efer.svme = 1; // Enable svm support for now.
382 efer.ffxsr = 0; // Turn on fast fxsave and fxrstor.
383 tc->setMiscReg(MISCREG_EFER, efer);
384
385 //Set up the registers that describe the operating mode.
386 CR0 cr0 = 0;
387 cr0.pg = 1; // Turn on paging.
388 cr0.cd = 0; // Don't disable caching.
389 cr0.nw = 0; // This is bit is defined to be ignored.
390 cr0.am = 1; // No alignment checking
391 cr0.wp = 1; // Supervisor mode can write read only pages
392 cr0.ne = 1;
393 cr0.et = 1; // This should always be 1
394 cr0.ts = 0; // We don't do task switching, so causing fp exceptions
395 // would be pointless.
396 cr0.em = 0; // Allow x87 instructions to execute natively.
397 cr0.mp = 1; // This doesn't really matter, but the manual suggests
398 // setting it to one.
399 cr0.pe = 1; // We're definitely in protected mode.
400 tc->setMiscReg(MISCREG_CR0, cr0);
401
402 CR0 cr2 = 0;
403 tc->setMiscReg(MISCREG_CR2, cr2);
404
405 CR3 cr3 = pageTablePhysAddr;
406 tc->setMiscReg(MISCREG_CR3, cr3);
407
408 CR4 cr4 = 0;
409 //Turn on pae.
410 cr4.osxsave = 1; // Enable XSAVE and Proc Extended States
411 cr4.osxmmexcpt = 1; // Operating System Unmasked Exception
412 cr4.osfxsr = 1; // Operating System FXSave/FSRSTOR Support
413 cr4.pce = 0; // Performance-Monitoring Counter Enable
414 cr4.pge = 0; // Page-Global Enable
415 cr4.mce = 0; // Machine Check Enable
416 cr4.pae = 1; // Physical-Address Extension
417 cr4.pse = 0; // Page Size Extensions
418 cr4.de = 0; // Debugging Extensions
419 cr4.tsd = 0; // Time Stamp Disable
420 cr4.pvi = 0; // Protected-Mode Virtual Interrupts
421 cr4.vme = 0; // Virtual-8086 Mode Extensions
422
423 tc->setMiscReg(MISCREG_CR4, cr4);
424
425 CR4 cr8 = 0;
426 tc->setMiscReg(MISCREG_CR8, cr8);
427
428 const Addr PageMapLevel4 = pageTablePhysAddr;
429 //Point to the page tables.
430 tc->setMiscReg(MISCREG_CR3, PageMapLevel4);
431
432 tc->setMiscReg(MISCREG_MXCSR, 0x1f80);
433
434 tc->setMiscReg(MISCREG_APIC_BASE, 0xfee00900);
435
436 tc->setMiscReg(MISCREG_TSG_BASE, GDTVirtAddr);
437 tc->setMiscReg(MISCREG_TSG_LIMIT, 0xffff);
438
439 tc->setMiscReg(MISCREG_IDTR_BASE, IDTVirtAddr);
440 tc->setMiscReg(MISCREG_IDTR_LIMIT, 0xffff);
441
442 /* enabling syscall and sysret */
443 MiscReg star = ((MiscReg)sret << 48) | ((MiscReg)scall << 32);
444 tc->setMiscReg(MISCREG_STAR, star);
445 MiscReg lstar = (MiscReg)syscallCodeVirtAddr;
446 tc->setMiscReg(MISCREG_LSTAR, lstar);
447 MiscReg sfmask = (1 << 8) | (1 << 10); // TF | DF
448 tc->setMiscReg(MISCREG_SF_MASK, sfmask);
449 }
450
451 /* Set up the content of the TSS and write it to physical memory. */
452
453 struct {
454 uint32_t reserved0; // +00h
455 uint32_t RSP0_low; // +04h
456 uint32_t RSP0_high; // +08h
457 uint32_t RSP1_low; // +0Ch
458 uint32_t RSP1_high; // +10h
459 uint32_t RSP2_low; // +14h
460 uint32_t RSP2_high; // +18h
461 uint32_t reserved1; // +1Ch
462 uint32_t reserved2; // +20h
463 uint32_t IST1_low; // +24h
464 uint32_t IST1_high; // +28h
465 uint32_t IST2_low; // +2Ch
466 uint32_t IST2_high; // +30h
467 uint32_t IST3_low; // +34h
468 uint32_t IST3_high; // +38h
469 uint32_t IST4_low; // +3Ch
470 uint32_t IST4_high; // +40h
471 uint32_t IST5_low; // +44h
472 uint32_t IST5_high; // +48h
473 uint32_t IST6_low; // +4Ch
474 uint32_t IST6_high; // +50h
475 uint32_t IST7_low; // +54h
476 uint32_t IST7_high; // +58h
477 uint32_t reserved3; // +5Ch
478 uint32_t reserved4; // +60h
479 uint16_t reserved5; // +64h
480 uint16_t IO_MapBase; // +66h
481 } tss;
482
483 /** setting Interrupt Stack Table */
484 uint64_t IST_start = ISTVirtAddr + PageBytes;
485 tss.IST1_low = IST_start;
486 tss.IST1_high = IST_start >> 32;
487 tss.RSP0_low = tss.IST1_low;
488 tss.RSP0_high = tss.IST1_high;
489 tss.RSP1_low = tss.IST1_low;
490 tss.RSP1_high = tss.IST1_high;
491 tss.RSP2_low = tss.IST1_low;
492 tss.RSP2_high = tss.IST1_high;
493 physProxy.writeBlob(TSSPhysAddr, (uint8_t *)(&tss), sizeof(tss));
494
495 /* Setting IDT gates */
496 GateDescriptorLow PFGateLow = 0;
497 PFGateLow.offsetHigh = bits(PFHandlerVirtAddr, 31, 16);
498 PFGateLow.offsetLow = bits(PFHandlerVirtAddr, 15, 0);
499 PFGateLow.selector = csLowPL;
500 PFGateLow.p = 1;
501 PFGateLow.dpl = 0;
502 PFGateLow.type = 0xe; // gate interrupt type
503 PFGateLow.IST = 0; // setting IST to 0 and using RSP0
504
505 GateDescriptorHigh PFGateHigh = 0;
506 PFGateHigh.offset = bits(PFHandlerVirtAddr, 63, 32);
507
508 struct {
509 uint64_t low;
510 uint64_t high;
511 } PFGate = {PFGateLow, PFGateHigh};
512
513 physProxy.writeBlob(IDTPhysAddr + 0xE0,
514 (uint8_t *)(&PFGate), sizeof(PFGate));
515
516 /* System call handler */
517 uint8_t syscallBlob[] = {
518 // mov %rax, (0xffffc90000005600)
519 0x48, 0xa3, 0x00, 0x60, 0x00,
520 0x00, 0x00, 0xc9, 0xff, 0xff,
521 // sysret
522 0x48, 0x0f, 0x07
523 };
524
525 physProxy.writeBlob(syscallCodePhysAddr,
526 syscallBlob, sizeof(syscallBlob));
527
528 /** Page fault handler */
529 uint8_t faultBlob[] = {
530 // mov %rax, (0xffffc90000005700)
531 0x48, 0xa3, 0x00, 0x61, 0x00,
532 0x00, 0x00, 0xc9, 0xff, 0xff,
533 // add $0x8, %rsp # skip error
534 0x48, 0x83, 0xc4, 0x08,
535 // iretq
536 0x48, 0xcf
537 };
538
539 physProxy.writeBlob(PFHandlerPhysAddr, faultBlob, sizeof(faultBlob));
540
541 MultiLevelPageTable<PageTableOps> *pt =
542 dynamic_cast<MultiLevelPageTable<PageTableOps> *>(pTable);
543
544 /* Syscall handler */
545 pt->map(syscallCodeVirtAddr, syscallCodePhysAddr, PageBytes, false);
546 /* GDT */
547 pt->map(GDTVirtAddr, GDTPhysAddr, PageBytes, false);
548 /* IDT */
549 pt->map(IDTVirtAddr, IDTPhysAddr, PageBytes, false);
550 /* TSS */
551 pt->map(TSSVirtAddr, TSSPhysAddr, PageBytes, false);
552 /* IST */
553 pt->map(ISTVirtAddr, ISTPhysAddr, PageBytes, false);
554 /* PF handler */
555 pt->map(PFHandlerVirtAddr, PFHandlerPhysAddr, PageBytes, false);
556 /* MMIO region for m5ops */
557 pt->map(MMIORegionVirtAddr, MMIORegionPhysAddr, 16*PageBytes, false);
558 } else {
559 for (int i = 0; i < contextIds.size(); i++) {
560 ThreadContext * tc = system->getThreadContext(contextIds[i]);
561
562 SegAttr dataAttr = 0;
563 dataAttr.dpl = 3;
564 dataAttr.unusable = 0;
565 dataAttr.defaultSize = 1;
566 dataAttr.longMode = 1;
567 dataAttr.avl = 0;
568 dataAttr.granularity = 1;
569 dataAttr.present = 1;
570 dataAttr.type = 3;
571 dataAttr.writable = 1;
572 dataAttr.readable = 1;
573 dataAttr.expandDown = 0;
574 dataAttr.system = 1;
575
576 // Initialize the segment registers.
577 for (int seg = 0; seg < NUM_SEGMENTREGS; seg++) {
578 tc->setMiscRegNoEffect(MISCREG_SEG_BASE(seg), 0);
579 tc->setMiscRegNoEffect(MISCREG_SEG_EFF_BASE(seg), 0);
580 tc->setMiscRegNoEffect(MISCREG_SEG_ATTR(seg), dataAttr);
581 }
582
583 SegAttr csAttr = 0;
584 csAttr.dpl = 3;
585 csAttr.unusable = 0;
586 csAttr.defaultSize = 0;
587 csAttr.longMode = 1;
588 csAttr.avl = 0;
589 csAttr.granularity = 1;
590 csAttr.present = 1;
591 csAttr.type = 10;
592 csAttr.writable = 0;
593 csAttr.readable = 1;
594 csAttr.expandDown = 0;
595 csAttr.system = 1;
596
597 tc->setMiscRegNoEffect(MISCREG_CS_ATTR, csAttr);
598
599 Efer efer = 0;
600 efer.sce = 1; // Enable system call extensions.
601 efer.lme = 1; // Enable long mode.
602 efer.lma = 1; // Activate long mode.
603 efer.nxe = 1; // Enable nx support.
604 efer.svme = 0; // Disable svm support for now. It isn't implemented.
605 efer.ffxsr = 1; // Turn on fast fxsave and fxrstor.
606 tc->setMiscReg(MISCREG_EFER, efer);
607
608 // Set up the registers that describe the operating mode.
609 CR0 cr0 = 0;
610 cr0.pg = 1; // Turn on paging.
611 cr0.cd = 0; // Don't disable caching.
612 cr0.nw = 0; // This is bit is defined to be ignored.
613 cr0.am = 0; // No alignment checking
614 cr0.wp = 0; // Supervisor mode can write read only pages
615 cr0.ne = 1;
616 cr0.et = 1; // This should always be 1
617 cr0.ts = 0; // We don't do task switching, so causing fp exceptions
618 // would be pointless.
619 cr0.em = 0; // Allow x87 instructions to execute natively.
620 cr0.mp = 1; // This doesn't really matter, but the manual suggests
621 // setting it to one.
622 cr0.pe = 1; // We're definitely in protected mode.
623 tc->setMiscReg(MISCREG_CR0, cr0);
624
625 tc->setMiscReg(MISCREG_MXCSR, 0x1f80);
626 }
627 }
628}
629
630void
631I386Process::initState()
632{
633 X86Process::initState();
634
635 argsInit(PageBytes);
636
637 /*
638 * Set up a GDT for this process. The whole GDT wouldn't really be for
639 * this process, but the only parts we care about are.
640 */
641 allocateMem(_gdtStart, _gdtSize);
642 uint64_t zero = 0;
643 assert(_gdtSize % sizeof(zero) == 0);
644 for (Addr gdtCurrent = _gdtStart;
645 gdtCurrent < _gdtStart + _gdtSize; gdtCurrent += sizeof(zero)) {
646 initVirtMem.write(gdtCurrent, zero);
647 }
648
649 // Set up the vsyscall page for this process.
650 allocateMem(vsyscallPage.base, vsyscallPage.size);
651 uint8_t vsyscallBlob[] = {
652 0x51, // push %ecx
653 0x52, // push %edp
654 0x55, // push %ebp
655 0x89, 0xe5, // mov %esp, %ebp
656 0x0f, 0x34 // sysenter
657 };
658 initVirtMem.writeBlob(vsyscallPage.base + vsyscallPage.vsyscallOffset,
659 vsyscallBlob, sizeof(vsyscallBlob));
660
661 uint8_t vsysexitBlob[] = {
662 0x5d, // pop %ebp
663 0x5a, // pop %edx
664 0x59, // pop %ecx
665 0xc3 // ret
666 };
667 initVirtMem.writeBlob(vsyscallPage.base + vsyscallPage.vsysexitOffset,
668 vsysexitBlob, sizeof(vsysexitBlob));
669
670 for (int i = 0; i < contextIds.size(); i++) {
671 ThreadContext * tc = system->getThreadContext(contextIds[i]);
672
673 SegAttr dataAttr = 0;
674 dataAttr.dpl = 3;
675 dataAttr.unusable = 0;
676 dataAttr.defaultSize = 1;
677 dataAttr.longMode = 0;
678 dataAttr.avl = 0;
679 dataAttr.granularity = 1;
680 dataAttr.present = 1;
681 dataAttr.type = 3;
682 dataAttr.writable = 1;
683 dataAttr.readable = 1;
684 dataAttr.expandDown = 0;
685 dataAttr.system = 1;
686
687 // Initialize the segment registers.
688 for (int seg = 0; seg < NUM_SEGMENTREGS; seg++) {
689 tc->setMiscRegNoEffect(MISCREG_SEG_BASE(seg), 0);
690 tc->setMiscRegNoEffect(MISCREG_SEG_EFF_BASE(seg), 0);
691 tc->setMiscRegNoEffect(MISCREG_SEG_ATTR(seg), dataAttr);
692 tc->setMiscRegNoEffect(MISCREG_SEG_SEL(seg), 0xB);
693 tc->setMiscRegNoEffect(MISCREG_SEG_LIMIT(seg), (uint32_t)(-1));
694 }
695
696 SegAttr csAttr = 0;
697 csAttr.dpl = 3;
698 csAttr.unusable = 0;
699 csAttr.defaultSize = 1;
700 csAttr.longMode = 0;
701 csAttr.avl = 0;
702 csAttr.granularity = 1;
703 csAttr.present = 1;
704 csAttr.type = 0xa;
705 csAttr.writable = 0;
706 csAttr.readable = 1;
707 csAttr.expandDown = 0;
708 csAttr.system = 1;
709
710 tc->setMiscRegNoEffect(MISCREG_CS_ATTR, csAttr);
711
712 tc->setMiscRegNoEffect(MISCREG_TSG_BASE, _gdtStart);
713 tc->setMiscRegNoEffect(MISCREG_TSG_EFF_BASE, _gdtStart);
714 tc->setMiscRegNoEffect(MISCREG_TSG_LIMIT, _gdtStart + _gdtSize - 1);
715
716 // Set the LDT selector to 0 to deactivate it.
717 tc->setMiscRegNoEffect(MISCREG_TSL, 0);
718
719 Efer efer = 0;
720 efer.sce = 1; // Enable system call extensions.
721 efer.lme = 1; // Enable long mode.
722 efer.lma = 0; // Deactivate long mode.
723 efer.nxe = 1; // Enable nx support.
724 efer.svme = 0; // Disable svm support for now. It isn't implemented.
725 efer.ffxsr = 1; // Turn on fast fxsave and fxrstor.
726 tc->setMiscReg(MISCREG_EFER, efer);
727
728 // Set up the registers that describe the operating mode.
729 CR0 cr0 = 0;
730 cr0.pg = 1; // Turn on paging.
731 cr0.cd = 0; // Don't disable caching.
732 cr0.nw = 0; // This is bit is defined to be ignored.
733 cr0.am = 0; // No alignment checking
734 cr0.wp = 0; // Supervisor mode can write read only pages
735 cr0.ne = 1;
736 cr0.et = 1; // This should always be 1
737 cr0.ts = 0; // We don't do task switching, so causing fp exceptions
738 // would be pointless.
739 cr0.em = 0; // Allow x87 instructions to execute natively.
740 cr0.mp = 1; // This doesn't really matter, but the manual suggests
741 // setting it to one.
742 cr0.pe = 1; // We're definitely in protected mode.
743 tc->setMiscReg(MISCREG_CR0, cr0);
744
745 tc->setMiscReg(MISCREG_MXCSR, 0x1f80);
746 }
747}
748
749template<class IntType>
750void
751X86Process::argsInit(int pageSize,
752 std::vector<AuxVector<IntType> > extraAuxvs)
753{
754 int intSize = sizeof(IntType);
755
756 typedef AuxVector<IntType> auxv_t;
757 std::vector<auxv_t> auxv = extraAuxvs;
758
759 string filename;
760 if (argv.size() < 1)
761 filename = "";
762 else
763 filename = argv[0];
764
765 // We want 16 byte alignment
766 uint64_t align = 16;
767
768 // Patch the ld_bias for dynamic executables.
769 updateBias();
770
771 // load object file into target memory
772 objFile->loadSections(initVirtMem);
773
774 enum X86CpuFeature {
775 X86_OnboardFPU = 1 << 0,
776 X86_VirtualModeExtensions = 1 << 1,
777 X86_DebuggingExtensions = 1 << 2,
778 X86_PageSizeExtensions = 1 << 3,
779
780 X86_TimeStampCounter = 1 << 4,
781 X86_ModelSpecificRegisters = 1 << 5,
782 X86_PhysicalAddressExtensions = 1 << 6,
783 X86_MachineCheckExtensions = 1 << 7,
784
785 X86_CMPXCHG8Instruction = 1 << 8,
786 X86_OnboardAPIC = 1 << 9,
787 X86_SYSENTER_SYSEXIT = 1 << 11,
788
789 X86_MemoryTypeRangeRegisters = 1 << 12,
790 X86_PageGlobalEnable = 1 << 13,
791 X86_MachineCheckArchitecture = 1 << 14,
792 X86_CMOVInstruction = 1 << 15,
793
794 X86_PageAttributeTable = 1 << 16,
795 X86_36BitPSEs = 1 << 17,
796 X86_ProcessorSerialNumber = 1 << 18,
797 X86_CLFLUSHInstruction = 1 << 19,
798
799 X86_DebugTraceStore = 1 << 21,
800 X86_ACPIViaMSR = 1 << 22,
801 X86_MultimediaExtensions = 1 << 23,
802
803 X86_FXSAVE_FXRSTOR = 1 << 24,
804 X86_StreamingSIMDExtensions = 1 << 25,
805 X86_StreamingSIMDExtensions2 = 1 << 26,
806 X86_CPUSelfSnoop = 1 << 27,
807
808 X86_HyperThreading = 1 << 28,
809 X86_AutomaticClockControl = 1 << 29,
810 X86_IA64Processor = 1 << 30
811 };
812
813 // Setup the auxiliary vectors. These will already have endian
814 // conversion. Auxiliary vectors are loaded only for elf formatted
815 // executables; the auxv is responsible for passing information from
816 // the OS to the interpreter.
817 ElfObject * elfObject = dynamic_cast<ElfObject *>(objFile);
818 if (elfObject) {
819 uint64_t features =
820 X86_OnboardFPU |
821 X86_VirtualModeExtensions |
822 X86_DebuggingExtensions |
823 X86_PageSizeExtensions |
824 X86_TimeStampCounter |
825 X86_ModelSpecificRegisters |
826 X86_PhysicalAddressExtensions |
827 X86_MachineCheckExtensions |
828 X86_CMPXCHG8Instruction |
829 X86_OnboardAPIC |
830 X86_SYSENTER_SYSEXIT |
831 X86_MemoryTypeRangeRegisters |
832 X86_PageGlobalEnable |
833 X86_MachineCheckArchitecture |
834 X86_CMOVInstruction |
835 X86_PageAttributeTable |
836 X86_36BitPSEs |
837// X86_ProcessorSerialNumber |
838 X86_CLFLUSHInstruction |
839// X86_DebugTraceStore |
840// X86_ACPIViaMSR |
841 X86_MultimediaExtensions |
842 X86_FXSAVE_FXRSTOR |
843 X86_StreamingSIMDExtensions |
844 X86_StreamingSIMDExtensions2 |
845// X86_CPUSelfSnoop |
846// X86_HyperThreading |
847// X86_AutomaticClockControl |
848// X86_IA64Processor |
849 0;
850
851 // Bits which describe the system hardware capabilities
852 // XXX Figure out what these should be
853 auxv.push_back(auxv_t(M5_AT_HWCAP, features));
854 // The system page size
855 auxv.push_back(auxv_t(M5_AT_PAGESZ, X86ISA::PageBytes));
856 // Frequency at which times() increments
857 // Defined to be 100 in the kernel source.
858 auxv.push_back(auxv_t(M5_AT_CLKTCK, 100));
859 // This is the virtual address of the program header tables if they
860 // appear in the executable image.
861 auxv.push_back(auxv_t(M5_AT_PHDR, elfObject->programHeaderTable()));
862 // This is the size of a program header entry from the elf file.
863 auxv.push_back(auxv_t(M5_AT_PHENT, elfObject->programHeaderSize()));
864 // This is the number of program headers from the original elf file.
865 auxv.push_back(auxv_t(M5_AT_PHNUM, elfObject->programHeaderCount()));
866 // This is the base address of the ELF interpreter; it should be
867 // zero for static executables or contain the base address for
868 // dynamic executables.
869 auxv.push_back(auxv_t(M5_AT_BASE, getBias()));
870 // XXX Figure out what this should be.
871 auxv.push_back(auxv_t(M5_AT_FLAGS, 0));
872 // The entry point to the program
873 auxv.push_back(auxv_t(M5_AT_ENTRY, objFile->entryPoint()));
874 // Different user and group IDs
875 auxv.push_back(auxv_t(M5_AT_UID, uid()));
876 auxv.push_back(auxv_t(M5_AT_EUID, euid()));
877 auxv.push_back(auxv_t(M5_AT_GID, gid()));
878 auxv.push_back(auxv_t(M5_AT_EGID, egid()));
879 // Whether to enable "secure mode" in the executable
880 auxv.push_back(auxv_t(M5_AT_SECURE, 0));
881 // The address of 16 "random" bytes.
882 auxv.push_back(auxv_t(M5_AT_RANDOM, 0));
883 // The name of the program
884 auxv.push_back(auxv_t(M5_AT_EXECFN, 0));
885 // The platform string
886 auxv.push_back(auxv_t(M5_AT_PLATFORM, 0));
887 }
888
889 // Figure out how big the initial stack needs to be
890
891 // A sentry NULL void pointer at the top of the stack.
892 int sentry_size = intSize;
893
894 // This is the name of the file which is present on the initial stack
895 // It's purpose is to let the user space linker examine the original file.
896 int file_name_size = filename.size() + 1;
897
898 const int numRandomBytes = 16;
899 int aux_data_size = numRandomBytes;
900
901 string platform = "x86_64";
902 aux_data_size += platform.size() + 1;
903
904 int env_data_size = 0;
905 for (int i = 0; i < envp.size(); ++i)
906 env_data_size += envp[i].size() + 1;
907 int arg_data_size = 0;
908 for (int i = 0; i < argv.size(); ++i)
909 arg_data_size += argv[i].size() + 1;
910
911 // The info_block needs to be padded so its size is a multiple of the
912 // alignment mask. Also, it appears that there needs to be at least some
913 // padding, so if the size is already a multiple, we need to increase it
914 // anyway.
915 int base_info_block_size =
916 sentry_size + file_name_size + env_data_size + arg_data_size;
917
918 int info_block_size = roundUp(base_info_block_size, align);
919
920 int info_block_padding = info_block_size - base_info_block_size;
921
922 // Each auxiliary vector is two 8 byte words
923 int aux_array_size = intSize * 2 * (auxv.size() + 1);
924
925 int envp_array_size = intSize * (envp.size() + 1);
926 int argv_array_size = intSize * (argv.size() + 1);
927
928 int argc_size = intSize;
929
930 // Figure out the size of the contents of the actual initial frame
931 int frame_size =
932 aux_array_size +
933 envp_array_size +
934 argv_array_size +
935 argc_size;
936
937 // There needs to be padding after the auxiliary vector data so that the
938 // very bottom of the stack is aligned properly.
939 int partial_size = frame_size + aux_data_size;
940 int aligned_partial_size = roundUp(partial_size, align);
941 int aux_padding = aligned_partial_size - partial_size;
942
943 int space_needed =
944 info_block_size +
945 aux_data_size +
946 aux_padding +
947 frame_size;
948
949 Addr stack_base = memState->getStackBase();
950
951 Addr stack_min = stack_base - space_needed;
952 stack_min = roundDown(stack_min, align);
953
954 unsigned stack_size = stack_base - stack_min;
955 stack_size = roundUp(stack_size, pageSize);
956 memState->setStackSize(stack_size);
957
958 // map memory
959 Addr stack_end = roundDown(stack_base - stack_size, pageSize);
960
961 DPRINTF(Stack, "Mapping the stack: 0x%x %dB\n", stack_end, stack_size);
962 allocateMem(stack_end, stack_size);
963
964 // map out initial stack contents
965 IntType sentry_base = stack_base - sentry_size;
966 IntType file_name_base = sentry_base - file_name_size;
967 IntType env_data_base = file_name_base - env_data_size;
968 IntType arg_data_base = env_data_base - arg_data_size;
969 IntType aux_data_base = arg_data_base - info_block_padding - aux_data_size;
970 IntType auxv_array_base = aux_data_base - aux_array_size - aux_padding;
971 IntType envp_array_base = auxv_array_base - envp_array_size;
972 IntType argv_array_base = envp_array_base - argv_array_size;
973 IntType argc_base = argv_array_base - argc_size;
974
975 DPRINTF(Stack, "The addresses of items on the initial stack:\n");
976 DPRINTF(Stack, "0x%x - file name\n", file_name_base);
977 DPRINTF(Stack, "0x%x - env data\n", env_data_base);
978 DPRINTF(Stack, "0x%x - arg data\n", arg_data_base);
979 DPRINTF(Stack, "0x%x - aux data\n", aux_data_base);
980 DPRINTF(Stack, "0x%x - auxv array\n", auxv_array_base);
981 DPRINTF(Stack, "0x%x - envp array\n", envp_array_base);
982 DPRINTF(Stack, "0x%x - argv array\n", argv_array_base);
983 DPRINTF(Stack, "0x%x - argc \n", argc_base);
984 DPRINTF(Stack, "0x%x - stack min\n", stack_min);
985
986 // write contents to stack
987
988 // figure out argc
989 IntType argc = argv.size();
990 IntType guestArgc = X86ISA::htog(argc);
991
992 // Write out the sentry void *
993 IntType sentry_NULL = 0;
994 initVirtMem.writeBlob(sentry_base, (uint8_t*)&sentry_NULL, sentry_size);
995
996 // Write the file name
997 initVirtMem.writeString(file_name_base, filename.c_str());
998
999 // Fix up the aux vectors which point to data
1000 assert(auxv[auxv.size() - 3].a_type == M5_AT_RANDOM);
1001 auxv[auxv.size() - 3].a_val = aux_data_base;
1002 assert(auxv[auxv.size() - 2].a_type == M5_AT_EXECFN);
1003 auxv[auxv.size() - 2].a_val = argv_array_base;
1004 assert(auxv[auxv.size() - 1].a_type == M5_AT_PLATFORM);
1005 auxv[auxv.size() - 1].a_val = aux_data_base + numRandomBytes;
1006
1007
1008 // Copy the aux stuff
1009 for (int x = 0; x < auxv.size(); x++) {
1010 initVirtMem.writeBlob(auxv_array_base + x * 2 * intSize,
1011 (uint8_t*)&(auxv[x].a_type), intSize);
1012 initVirtMem.writeBlob(auxv_array_base + (x * 2 + 1) * intSize,
1013 (uint8_t*)&(auxv[x].a_val), intSize);
1014 }
1015 // Write out the terminating zeroed auxiliary vector
1016 const uint64_t zero = 0;
1017 initVirtMem.writeBlob(auxv_array_base + auxv.size() * 2 * intSize,
1018 (uint8_t*)&zero, intSize);
1019 initVirtMem.writeBlob(auxv_array_base + (auxv.size() * 2 + 1) * intSize,
1020 (uint8_t*)&zero, intSize);
1021
1022 initVirtMem.writeString(aux_data_base, platform.c_str());
1023
1024 copyStringArray(envp, envp_array_base, env_data_base, initVirtMem);
1025 copyStringArray(argv, argv_array_base, arg_data_base, initVirtMem);
1026
1027 initVirtMem.writeBlob(argc_base, (uint8_t*)&guestArgc, intSize);
1028
1029 ThreadContext *tc = system->getThreadContext(contextIds[0]);
1030 // Set the stack pointer register
1031 tc->setIntReg(StackPointerReg, stack_min);
1032
1033 // There doesn't need to be any segment base added in since we're dealing
1034 // with the flat segmentation model.
1035 tc->pcState(getStartPC());
1036
1037 // Align the "stack_min" to a page boundary.
1038 memState->setStackMin(roundDown(stack_min, pageSize));
1039}
1040
1041void
1042X86_64Process::argsInit(int pageSize)
1043{
1044 std::vector<AuxVector<uint64_t> > extraAuxvs;
1045 extraAuxvs.push_back(AuxVector<uint64_t>(M5_AT_SYSINFO_EHDR,
1046 vsyscallPage.base));
1047 X86Process::argsInit<uint64_t>(pageSize, extraAuxvs);
1048}
1049
1050void
1051I386Process::argsInit(int pageSize)
1052{
1053 std::vector<AuxVector<uint32_t> > extraAuxvs;
1054 //Tell the binary where the vsyscall part of the vsyscall page is.
1055 extraAuxvs.push_back(AuxVector<uint32_t>(M5_AT_SYSINFO,
1056 vsyscallPage.base + vsyscallPage.vsyscallOffset));
1057 extraAuxvs.push_back(AuxVector<uint32_t>(M5_AT_SYSINFO_EHDR,
1058 vsyscallPage.base));
1059 X86Process::argsInit<uint32_t>(pageSize, extraAuxvs);
1060}
1061
1062void
1063X86Process::setSyscallReturn(ThreadContext *tc, SyscallReturn retval)
1064{
1065 tc->setIntReg(INTREG_RAX, retval.encodedValue());
1066}
1067
1068X86ISA::IntReg
1069X86_64Process::getSyscallArg(ThreadContext *tc, int &i)
1070{
1071 assert(i < NumArgumentRegs);
1072 return tc->readIntReg(ArgumentReg[i++]);
1073}
1074
1075void
1076X86_64Process::setSyscallArg(ThreadContext *tc, int i, X86ISA::IntReg val)
1077{
1078 assert(i < NumArgumentRegs);
1079 return tc->setIntReg(ArgumentReg[i], val);
1080}
1081
1082void
1083X86_64Process::clone(ThreadContext *old_tc, ThreadContext *new_tc,
1084 Process *p, TheISA::IntReg flags)
1085{
1086 X86Process::clone(old_tc, new_tc, p, flags);
1087 ((X86_64Process*)p)->vsyscallPage = vsyscallPage;
1088}
1089
1090X86ISA::IntReg
1091I386Process::getSyscallArg(ThreadContext *tc, int &i)
1092{
1093 assert(i < NumArgumentRegs32);
1094 return tc->readIntReg(ArgumentReg32[i++]);
1095}
1096
1097X86ISA::IntReg
1098I386Process::getSyscallArg(ThreadContext *tc, int &i, int width)
1099{
1100 assert(width == 32 || width == 64);
1101 assert(i < NumArgumentRegs);
1102 uint64_t retVal = tc->readIntReg(ArgumentReg32[i++]) & mask(32);
1103 if (width == 64)
1104 retVal |= ((uint64_t)tc->readIntReg(ArgumentReg[i++]) << 32);
1105 return retVal;
1106}
1107
1108void
1109I386Process::setSyscallArg(ThreadContext *tc, int i, X86ISA::IntReg val)
1110{
1111 assert(i < NumArgumentRegs);
1112 return tc->setIntReg(ArgumentReg[i], val);
1113}
1114
1115void
1116I386Process::clone(ThreadContext *old_tc, ThreadContext *new_tc,
1117 Process *p, TheISA::IntReg flags)
1118{
1119 X86Process::clone(old_tc, new_tc, p, flags);
1120 ((I386Process*)p)->vsyscallPage = vsyscallPage;
1121}
108 objFile),
109 syscallDescs(_syscallDescs), numSyscallDescs(_numSyscallDescs)
110{
111}
112
113void X86Process::clone(ThreadContext *old_tc, ThreadContext *new_tc,
114 Process *p, TheISA::IntReg flags)
115{
116 Process::clone(old_tc, new_tc, p, flags);
117 X86Process *process = (X86Process*)p;
118 *process = *this;
119}
120
121X86_64Process::X86_64Process(ProcessParams *params, ObjectFile *objFile,
122 SyscallDesc *_syscallDescs, int _numSyscallDescs)
123 : X86Process(params, objFile, _syscallDescs, _numSyscallDescs)
124{
125
126 vsyscallPage.base = 0xffffffffff600000ULL;
127 vsyscallPage.size = PageBytes;
128 vsyscallPage.vtimeOffset = 0x400;
129 vsyscallPage.vgettimeofdayOffset = 0x0;
130
131 Addr brk_point = roundUp(objFile->dataBase() + objFile->dataSize() +
132 objFile->bssSize(), PageBytes);
133 Addr stack_base = 0x7FFFFFFFF000ULL;
134 Addr max_stack_size = 8 * 1024 * 1024;
135 Addr next_thread_stack_base = stack_base - max_stack_size;
136 Addr mmap_end = 0x7FFFF7FFF000ULL;
137
138 memState = make_shared<MemState>(brk_point, stack_base, max_stack_size,
139 next_thread_stack_base, mmap_end);
140}
141
142void
143I386Process::syscall(int64_t callnum, ThreadContext *tc, Fault *fault)
144{
145 TheISA::PCState pc = tc->pcState();
146 Addr eip = pc.pc();
147 if (eip >= vsyscallPage.base &&
148 eip < vsyscallPage.base + vsyscallPage.size) {
149 pc.npc(vsyscallPage.base + vsyscallPage.vsysexitOffset);
150 tc->pcState(pc);
151 }
152 X86Process::syscall(callnum, tc, fault);
153}
154
155
156I386Process::I386Process(ProcessParams *params, ObjectFile *objFile,
157 SyscallDesc *_syscallDescs, int _numSyscallDescs)
158 : X86Process(params, objFile, _syscallDescs, _numSyscallDescs)
159{
160 _gdtStart = ULL(0xffffd000);
161 _gdtSize = PageBytes;
162
163 vsyscallPage.base = 0xffffe000ULL;
164 vsyscallPage.size = PageBytes;
165 vsyscallPage.vsyscallOffset = 0x400;
166 vsyscallPage.vsysexitOffset = 0x410;
167
168 Addr brk_point = roundUp(objFile->dataBase() + objFile->dataSize() +
169 objFile->bssSize(), PageBytes);
170 Addr stack_base = _gdtStart;
171 Addr max_stack_size = 8 * 1024 * 1024;
172 Addr next_thread_stack_base = stack_base - max_stack_size;
173 Addr mmap_end = 0xB7FFF000ULL;
174
175 memState = make_shared<MemState>(brk_point, stack_base, max_stack_size,
176 next_thread_stack_base, mmap_end);
177}
178
179SyscallDesc*
180X86Process::getDesc(int callnum)
181{
182 if (callnum < 0 || callnum >= numSyscallDescs)
183 return NULL;
184 return &syscallDescs[callnum];
185}
186
187void
188X86_64Process::initState()
189{
190 X86Process::initState();
191
192 argsInit(PageBytes);
193
194 // Set up the vsyscall page for this process.
195 allocateMem(vsyscallPage.base, vsyscallPage.size);
196 uint8_t vtimeBlob[] = {
197 0x48,0xc7,0xc0,0xc9,0x00,0x00,0x00, // mov $0xc9,%rax
198 0x0f,0x05, // syscall
199 0xc3 // retq
200 };
201 initVirtMem.writeBlob(vsyscallPage.base + vsyscallPage.vtimeOffset,
202 vtimeBlob, sizeof(vtimeBlob));
203
204 uint8_t vgettimeofdayBlob[] = {
205 0x48,0xc7,0xc0,0x60,0x00,0x00,0x00, // mov $0x60,%rax
206 0x0f,0x05, // syscall
207 0xc3 // retq
208 };
209 initVirtMem.writeBlob(vsyscallPage.base + vsyscallPage.vgettimeofdayOffset,
210 vgettimeofdayBlob, sizeof(vgettimeofdayBlob));
211
212 if (kvmInSE) {
213 PortProxy physProxy = system->physProxy;
214
215 /*
216 * Set up the gdt.
217 */
218 uint8_t numGDTEntries = 0;
219 uint64_t nullDescriptor = 0;
220 physProxy.writeBlob(GDTPhysAddr + numGDTEntries * 8,
221 (uint8_t *)(&nullDescriptor), 8);
222 numGDTEntries++;
223
224 SegDescriptor initDesc = 0;
225 initDesc.type.codeOrData = 0; // code or data type
226 initDesc.type.c = 0; // conforming
227 initDesc.type.r = 1; // readable
228 initDesc.dpl = 0; // privilege
229 initDesc.p = 1; // present
230 initDesc.l = 1; // longmode - 64 bit
231 initDesc.d = 0; // operand size
232 initDesc.g = 1; // granularity
233 initDesc.s = 1; // system segment
234 initDesc.limitHigh = 0xFFFF;
235 initDesc.limitLow = 0xF;
236 initDesc.baseHigh = 0x0;
237 initDesc.baseLow = 0x0;
238
239 //64 bit code segment
240 SegDescriptor csLowPLDesc = initDesc;
241 csLowPLDesc.type.codeOrData = 1;
242 csLowPLDesc.dpl = 0;
243 uint64_t csLowPLDescVal = csLowPLDesc;
244 physProxy.writeBlob(GDTPhysAddr + numGDTEntries * 8,
245 (uint8_t *)(&csLowPLDescVal), 8);
246
247 numGDTEntries++;
248
249 SegSelector csLowPL = 0;
250 csLowPL.si = numGDTEntries - 1;
251 csLowPL.rpl = 0;
252
253 //64 bit data segment
254 SegDescriptor dsLowPLDesc = initDesc;
255 dsLowPLDesc.type.codeOrData = 0;
256 dsLowPLDesc.dpl = 0;
257 uint64_t dsLowPLDescVal = dsLowPLDesc;
258 physProxy.writeBlob(GDTPhysAddr + numGDTEntries * 8,
259 (uint8_t *)(&dsLowPLDescVal), 8);
260
261 numGDTEntries++;
262
263 SegSelector dsLowPL = 0;
264 dsLowPL.si = numGDTEntries - 1;
265 dsLowPL.rpl = 0;
266
267 //64 bit data segment
268 SegDescriptor dsDesc = initDesc;
269 dsDesc.type.codeOrData = 0;
270 dsDesc.dpl = 3;
271 uint64_t dsDescVal = dsDesc;
272 physProxy.writeBlob(GDTPhysAddr + numGDTEntries * 8,
273 (uint8_t *)(&dsDescVal), 8);
274
275 numGDTEntries++;
276
277 SegSelector ds = 0;
278 ds.si = numGDTEntries - 1;
279 ds.rpl = 3;
280
281 //64 bit code segment
282 SegDescriptor csDesc = initDesc;
283 csDesc.type.codeOrData = 1;
284 csDesc.dpl = 3;
285 uint64_t csDescVal = csDesc;
286 physProxy.writeBlob(GDTPhysAddr + numGDTEntries * 8,
287 (uint8_t *)(&csDescVal), 8);
288
289 numGDTEntries++;
290
291 SegSelector cs = 0;
292 cs.si = numGDTEntries - 1;
293 cs.rpl = 3;
294
295 SegSelector scall = 0;
296 scall.si = csLowPL.si;
297 scall.rpl = 0;
298
299 SegSelector sret = 0;
300 sret.si = dsLowPL.si;
301 sret.rpl = 3;
302
303 /* In long mode the TSS has been extended to 16 Bytes */
304 TSSlow TSSDescLow = 0;
305 TSSDescLow.type = 0xB;
306 TSSDescLow.dpl = 0; // Privelege level 0
307 TSSDescLow.p = 1; // Present
308 TSSDescLow.g = 1; // Page granularity
309 TSSDescLow.limitHigh = 0xF;
310 TSSDescLow.limitLow = 0xFFFF;
311 TSSDescLow.baseLow = bits(TSSVirtAddr, 23, 0);
312 TSSDescLow.baseHigh = bits(TSSVirtAddr, 31, 24);
313
314 TSShigh TSSDescHigh = 0;
315 TSSDescHigh.base = bits(TSSVirtAddr, 63, 32);
316
317 struct TSSDesc {
318 uint64_t low;
319 uint64_t high;
320 } tssDescVal = {TSSDescLow, TSSDescHigh};
321
322 physProxy.writeBlob(GDTPhysAddr + numGDTEntries * 8,
323 (uint8_t *)(&tssDescVal), sizeof(tssDescVal));
324
325 numGDTEntries++;
326
327 SegSelector tssSel = 0;
328 tssSel.si = numGDTEntries - 1;
329
330 uint64_t tss_base_addr = (TSSDescHigh.base << 32) |
331 (TSSDescLow.baseHigh << 24) |
332 TSSDescLow.baseLow;
333 uint64_t tss_limit = TSSDescLow.limitLow | (TSSDescLow.limitHigh << 16);
334
335 SegAttr tss_attr = 0;
336
337 tss_attr.type = TSSDescLow.type;
338 tss_attr.dpl = TSSDescLow.dpl;
339 tss_attr.present = TSSDescLow.p;
340 tss_attr.granularity = TSSDescLow.g;
341 tss_attr.unusable = 0;
342
343 for (int i = 0; i < contextIds.size(); i++) {
344 ThreadContext * tc = system->getThreadContext(contextIds[i]);
345
346 tc->setMiscReg(MISCREG_CS, cs);
347 tc->setMiscReg(MISCREG_DS, ds);
348 tc->setMiscReg(MISCREG_ES, ds);
349 tc->setMiscReg(MISCREG_FS, ds);
350 tc->setMiscReg(MISCREG_GS, ds);
351 tc->setMiscReg(MISCREG_SS, ds);
352
353 // LDT
354 tc->setMiscReg(MISCREG_TSL, 0);
355 SegAttr tslAttr = 0;
356 tslAttr.present = 1;
357 tslAttr.type = 2;
358 tc->setMiscReg(MISCREG_TSL_ATTR, tslAttr);
359
360 tc->setMiscReg(MISCREG_TSG_BASE, GDTVirtAddr);
361 tc->setMiscReg(MISCREG_TSG_LIMIT, 8 * numGDTEntries - 1);
362
363 tc->setMiscReg(MISCREG_TR, tssSel);
364 tc->setMiscReg(MISCREG_TR_BASE, tss_base_addr);
365 tc->setMiscReg(MISCREG_TR_EFF_BASE, 0);
366 tc->setMiscReg(MISCREG_TR_LIMIT, tss_limit);
367 tc->setMiscReg(MISCREG_TR_ATTR, tss_attr);
368
369 //Start using longmode segments.
370 installSegDesc(tc, SEGMENT_REG_CS, csDesc, true);
371 installSegDesc(tc, SEGMENT_REG_DS, dsDesc, true);
372 installSegDesc(tc, SEGMENT_REG_ES, dsDesc, true);
373 installSegDesc(tc, SEGMENT_REG_FS, dsDesc, true);
374 installSegDesc(tc, SEGMENT_REG_GS, dsDesc, true);
375 installSegDesc(tc, SEGMENT_REG_SS, dsDesc, true);
376
377 Efer efer = 0;
378 efer.sce = 1; // Enable system call extensions.
379 efer.lme = 1; // Enable long mode.
380 efer.lma = 1; // Activate long mode.
381 efer.nxe = 0; // Enable nx support.
382 efer.svme = 1; // Enable svm support for now.
383 efer.ffxsr = 0; // Turn on fast fxsave and fxrstor.
384 tc->setMiscReg(MISCREG_EFER, efer);
385
386 //Set up the registers that describe the operating mode.
387 CR0 cr0 = 0;
388 cr0.pg = 1; // Turn on paging.
389 cr0.cd = 0; // Don't disable caching.
390 cr0.nw = 0; // This is bit is defined to be ignored.
391 cr0.am = 1; // No alignment checking
392 cr0.wp = 1; // Supervisor mode can write read only pages
393 cr0.ne = 1;
394 cr0.et = 1; // This should always be 1
395 cr0.ts = 0; // We don't do task switching, so causing fp exceptions
396 // would be pointless.
397 cr0.em = 0; // Allow x87 instructions to execute natively.
398 cr0.mp = 1; // This doesn't really matter, but the manual suggests
399 // setting it to one.
400 cr0.pe = 1; // We're definitely in protected mode.
401 tc->setMiscReg(MISCREG_CR0, cr0);
402
403 CR0 cr2 = 0;
404 tc->setMiscReg(MISCREG_CR2, cr2);
405
406 CR3 cr3 = pageTablePhysAddr;
407 tc->setMiscReg(MISCREG_CR3, cr3);
408
409 CR4 cr4 = 0;
410 //Turn on pae.
411 cr4.osxsave = 1; // Enable XSAVE and Proc Extended States
412 cr4.osxmmexcpt = 1; // Operating System Unmasked Exception
413 cr4.osfxsr = 1; // Operating System FXSave/FSRSTOR Support
414 cr4.pce = 0; // Performance-Monitoring Counter Enable
415 cr4.pge = 0; // Page-Global Enable
416 cr4.mce = 0; // Machine Check Enable
417 cr4.pae = 1; // Physical-Address Extension
418 cr4.pse = 0; // Page Size Extensions
419 cr4.de = 0; // Debugging Extensions
420 cr4.tsd = 0; // Time Stamp Disable
421 cr4.pvi = 0; // Protected-Mode Virtual Interrupts
422 cr4.vme = 0; // Virtual-8086 Mode Extensions
423
424 tc->setMiscReg(MISCREG_CR4, cr4);
425
426 CR4 cr8 = 0;
427 tc->setMiscReg(MISCREG_CR8, cr8);
428
429 const Addr PageMapLevel4 = pageTablePhysAddr;
430 //Point to the page tables.
431 tc->setMiscReg(MISCREG_CR3, PageMapLevel4);
432
433 tc->setMiscReg(MISCREG_MXCSR, 0x1f80);
434
435 tc->setMiscReg(MISCREG_APIC_BASE, 0xfee00900);
436
437 tc->setMiscReg(MISCREG_TSG_BASE, GDTVirtAddr);
438 tc->setMiscReg(MISCREG_TSG_LIMIT, 0xffff);
439
440 tc->setMiscReg(MISCREG_IDTR_BASE, IDTVirtAddr);
441 tc->setMiscReg(MISCREG_IDTR_LIMIT, 0xffff);
442
443 /* enabling syscall and sysret */
444 MiscReg star = ((MiscReg)sret << 48) | ((MiscReg)scall << 32);
445 tc->setMiscReg(MISCREG_STAR, star);
446 MiscReg lstar = (MiscReg)syscallCodeVirtAddr;
447 tc->setMiscReg(MISCREG_LSTAR, lstar);
448 MiscReg sfmask = (1 << 8) | (1 << 10); // TF | DF
449 tc->setMiscReg(MISCREG_SF_MASK, sfmask);
450 }
451
452 /* Set up the content of the TSS and write it to physical memory. */
453
454 struct {
455 uint32_t reserved0; // +00h
456 uint32_t RSP0_low; // +04h
457 uint32_t RSP0_high; // +08h
458 uint32_t RSP1_low; // +0Ch
459 uint32_t RSP1_high; // +10h
460 uint32_t RSP2_low; // +14h
461 uint32_t RSP2_high; // +18h
462 uint32_t reserved1; // +1Ch
463 uint32_t reserved2; // +20h
464 uint32_t IST1_low; // +24h
465 uint32_t IST1_high; // +28h
466 uint32_t IST2_low; // +2Ch
467 uint32_t IST2_high; // +30h
468 uint32_t IST3_low; // +34h
469 uint32_t IST3_high; // +38h
470 uint32_t IST4_low; // +3Ch
471 uint32_t IST4_high; // +40h
472 uint32_t IST5_low; // +44h
473 uint32_t IST5_high; // +48h
474 uint32_t IST6_low; // +4Ch
475 uint32_t IST6_high; // +50h
476 uint32_t IST7_low; // +54h
477 uint32_t IST7_high; // +58h
478 uint32_t reserved3; // +5Ch
479 uint32_t reserved4; // +60h
480 uint16_t reserved5; // +64h
481 uint16_t IO_MapBase; // +66h
482 } tss;
483
484 /** setting Interrupt Stack Table */
485 uint64_t IST_start = ISTVirtAddr + PageBytes;
486 tss.IST1_low = IST_start;
487 tss.IST1_high = IST_start >> 32;
488 tss.RSP0_low = tss.IST1_low;
489 tss.RSP0_high = tss.IST1_high;
490 tss.RSP1_low = tss.IST1_low;
491 tss.RSP1_high = tss.IST1_high;
492 tss.RSP2_low = tss.IST1_low;
493 tss.RSP2_high = tss.IST1_high;
494 physProxy.writeBlob(TSSPhysAddr, (uint8_t *)(&tss), sizeof(tss));
495
496 /* Setting IDT gates */
497 GateDescriptorLow PFGateLow = 0;
498 PFGateLow.offsetHigh = bits(PFHandlerVirtAddr, 31, 16);
499 PFGateLow.offsetLow = bits(PFHandlerVirtAddr, 15, 0);
500 PFGateLow.selector = csLowPL;
501 PFGateLow.p = 1;
502 PFGateLow.dpl = 0;
503 PFGateLow.type = 0xe; // gate interrupt type
504 PFGateLow.IST = 0; // setting IST to 0 and using RSP0
505
506 GateDescriptorHigh PFGateHigh = 0;
507 PFGateHigh.offset = bits(PFHandlerVirtAddr, 63, 32);
508
509 struct {
510 uint64_t low;
511 uint64_t high;
512 } PFGate = {PFGateLow, PFGateHigh};
513
514 physProxy.writeBlob(IDTPhysAddr + 0xE0,
515 (uint8_t *)(&PFGate), sizeof(PFGate));
516
517 /* System call handler */
518 uint8_t syscallBlob[] = {
519 // mov %rax, (0xffffc90000005600)
520 0x48, 0xa3, 0x00, 0x60, 0x00,
521 0x00, 0x00, 0xc9, 0xff, 0xff,
522 // sysret
523 0x48, 0x0f, 0x07
524 };
525
526 physProxy.writeBlob(syscallCodePhysAddr,
527 syscallBlob, sizeof(syscallBlob));
528
529 /** Page fault handler */
530 uint8_t faultBlob[] = {
531 // mov %rax, (0xffffc90000005700)
532 0x48, 0xa3, 0x00, 0x61, 0x00,
533 0x00, 0x00, 0xc9, 0xff, 0xff,
534 // add $0x8, %rsp # skip error
535 0x48, 0x83, 0xc4, 0x08,
536 // iretq
537 0x48, 0xcf
538 };
539
540 physProxy.writeBlob(PFHandlerPhysAddr, faultBlob, sizeof(faultBlob));
541
542 MultiLevelPageTable<PageTableOps> *pt =
543 dynamic_cast<MultiLevelPageTable<PageTableOps> *>(pTable);
544
545 /* Syscall handler */
546 pt->map(syscallCodeVirtAddr, syscallCodePhysAddr, PageBytes, false);
547 /* GDT */
548 pt->map(GDTVirtAddr, GDTPhysAddr, PageBytes, false);
549 /* IDT */
550 pt->map(IDTVirtAddr, IDTPhysAddr, PageBytes, false);
551 /* TSS */
552 pt->map(TSSVirtAddr, TSSPhysAddr, PageBytes, false);
553 /* IST */
554 pt->map(ISTVirtAddr, ISTPhysAddr, PageBytes, false);
555 /* PF handler */
556 pt->map(PFHandlerVirtAddr, PFHandlerPhysAddr, PageBytes, false);
557 /* MMIO region for m5ops */
558 pt->map(MMIORegionVirtAddr, MMIORegionPhysAddr, 16*PageBytes, false);
559 } else {
560 for (int i = 0; i < contextIds.size(); i++) {
561 ThreadContext * tc = system->getThreadContext(contextIds[i]);
562
563 SegAttr dataAttr = 0;
564 dataAttr.dpl = 3;
565 dataAttr.unusable = 0;
566 dataAttr.defaultSize = 1;
567 dataAttr.longMode = 1;
568 dataAttr.avl = 0;
569 dataAttr.granularity = 1;
570 dataAttr.present = 1;
571 dataAttr.type = 3;
572 dataAttr.writable = 1;
573 dataAttr.readable = 1;
574 dataAttr.expandDown = 0;
575 dataAttr.system = 1;
576
577 // Initialize the segment registers.
578 for (int seg = 0; seg < NUM_SEGMENTREGS; seg++) {
579 tc->setMiscRegNoEffect(MISCREG_SEG_BASE(seg), 0);
580 tc->setMiscRegNoEffect(MISCREG_SEG_EFF_BASE(seg), 0);
581 tc->setMiscRegNoEffect(MISCREG_SEG_ATTR(seg), dataAttr);
582 }
583
584 SegAttr csAttr = 0;
585 csAttr.dpl = 3;
586 csAttr.unusable = 0;
587 csAttr.defaultSize = 0;
588 csAttr.longMode = 1;
589 csAttr.avl = 0;
590 csAttr.granularity = 1;
591 csAttr.present = 1;
592 csAttr.type = 10;
593 csAttr.writable = 0;
594 csAttr.readable = 1;
595 csAttr.expandDown = 0;
596 csAttr.system = 1;
597
598 tc->setMiscRegNoEffect(MISCREG_CS_ATTR, csAttr);
599
600 Efer efer = 0;
601 efer.sce = 1; // Enable system call extensions.
602 efer.lme = 1; // Enable long mode.
603 efer.lma = 1; // Activate long mode.
604 efer.nxe = 1; // Enable nx support.
605 efer.svme = 0; // Disable svm support for now. It isn't implemented.
606 efer.ffxsr = 1; // Turn on fast fxsave and fxrstor.
607 tc->setMiscReg(MISCREG_EFER, efer);
608
609 // Set up the registers that describe the operating mode.
610 CR0 cr0 = 0;
611 cr0.pg = 1; // Turn on paging.
612 cr0.cd = 0; // Don't disable caching.
613 cr0.nw = 0; // This is bit is defined to be ignored.
614 cr0.am = 0; // No alignment checking
615 cr0.wp = 0; // Supervisor mode can write read only pages
616 cr0.ne = 1;
617 cr0.et = 1; // This should always be 1
618 cr0.ts = 0; // We don't do task switching, so causing fp exceptions
619 // would be pointless.
620 cr0.em = 0; // Allow x87 instructions to execute natively.
621 cr0.mp = 1; // This doesn't really matter, but the manual suggests
622 // setting it to one.
623 cr0.pe = 1; // We're definitely in protected mode.
624 tc->setMiscReg(MISCREG_CR0, cr0);
625
626 tc->setMiscReg(MISCREG_MXCSR, 0x1f80);
627 }
628 }
629}
630
631void
632I386Process::initState()
633{
634 X86Process::initState();
635
636 argsInit(PageBytes);
637
638 /*
639 * Set up a GDT for this process. The whole GDT wouldn't really be for
640 * this process, but the only parts we care about are.
641 */
642 allocateMem(_gdtStart, _gdtSize);
643 uint64_t zero = 0;
644 assert(_gdtSize % sizeof(zero) == 0);
645 for (Addr gdtCurrent = _gdtStart;
646 gdtCurrent < _gdtStart + _gdtSize; gdtCurrent += sizeof(zero)) {
647 initVirtMem.write(gdtCurrent, zero);
648 }
649
650 // Set up the vsyscall page for this process.
651 allocateMem(vsyscallPage.base, vsyscallPage.size);
652 uint8_t vsyscallBlob[] = {
653 0x51, // push %ecx
654 0x52, // push %edp
655 0x55, // push %ebp
656 0x89, 0xe5, // mov %esp, %ebp
657 0x0f, 0x34 // sysenter
658 };
659 initVirtMem.writeBlob(vsyscallPage.base + vsyscallPage.vsyscallOffset,
660 vsyscallBlob, sizeof(vsyscallBlob));
661
662 uint8_t vsysexitBlob[] = {
663 0x5d, // pop %ebp
664 0x5a, // pop %edx
665 0x59, // pop %ecx
666 0xc3 // ret
667 };
668 initVirtMem.writeBlob(vsyscallPage.base + vsyscallPage.vsysexitOffset,
669 vsysexitBlob, sizeof(vsysexitBlob));
670
671 for (int i = 0; i < contextIds.size(); i++) {
672 ThreadContext * tc = system->getThreadContext(contextIds[i]);
673
674 SegAttr dataAttr = 0;
675 dataAttr.dpl = 3;
676 dataAttr.unusable = 0;
677 dataAttr.defaultSize = 1;
678 dataAttr.longMode = 0;
679 dataAttr.avl = 0;
680 dataAttr.granularity = 1;
681 dataAttr.present = 1;
682 dataAttr.type = 3;
683 dataAttr.writable = 1;
684 dataAttr.readable = 1;
685 dataAttr.expandDown = 0;
686 dataAttr.system = 1;
687
688 // Initialize the segment registers.
689 for (int seg = 0; seg < NUM_SEGMENTREGS; seg++) {
690 tc->setMiscRegNoEffect(MISCREG_SEG_BASE(seg), 0);
691 tc->setMiscRegNoEffect(MISCREG_SEG_EFF_BASE(seg), 0);
692 tc->setMiscRegNoEffect(MISCREG_SEG_ATTR(seg), dataAttr);
693 tc->setMiscRegNoEffect(MISCREG_SEG_SEL(seg), 0xB);
694 tc->setMiscRegNoEffect(MISCREG_SEG_LIMIT(seg), (uint32_t)(-1));
695 }
696
697 SegAttr csAttr = 0;
698 csAttr.dpl = 3;
699 csAttr.unusable = 0;
700 csAttr.defaultSize = 1;
701 csAttr.longMode = 0;
702 csAttr.avl = 0;
703 csAttr.granularity = 1;
704 csAttr.present = 1;
705 csAttr.type = 0xa;
706 csAttr.writable = 0;
707 csAttr.readable = 1;
708 csAttr.expandDown = 0;
709 csAttr.system = 1;
710
711 tc->setMiscRegNoEffect(MISCREG_CS_ATTR, csAttr);
712
713 tc->setMiscRegNoEffect(MISCREG_TSG_BASE, _gdtStart);
714 tc->setMiscRegNoEffect(MISCREG_TSG_EFF_BASE, _gdtStart);
715 tc->setMiscRegNoEffect(MISCREG_TSG_LIMIT, _gdtStart + _gdtSize - 1);
716
717 // Set the LDT selector to 0 to deactivate it.
718 tc->setMiscRegNoEffect(MISCREG_TSL, 0);
719
720 Efer efer = 0;
721 efer.sce = 1; // Enable system call extensions.
722 efer.lme = 1; // Enable long mode.
723 efer.lma = 0; // Deactivate long mode.
724 efer.nxe = 1; // Enable nx support.
725 efer.svme = 0; // Disable svm support for now. It isn't implemented.
726 efer.ffxsr = 1; // Turn on fast fxsave and fxrstor.
727 tc->setMiscReg(MISCREG_EFER, efer);
728
729 // Set up the registers that describe the operating mode.
730 CR0 cr0 = 0;
731 cr0.pg = 1; // Turn on paging.
732 cr0.cd = 0; // Don't disable caching.
733 cr0.nw = 0; // This is bit is defined to be ignored.
734 cr0.am = 0; // No alignment checking
735 cr0.wp = 0; // Supervisor mode can write read only pages
736 cr0.ne = 1;
737 cr0.et = 1; // This should always be 1
738 cr0.ts = 0; // We don't do task switching, so causing fp exceptions
739 // would be pointless.
740 cr0.em = 0; // Allow x87 instructions to execute natively.
741 cr0.mp = 1; // This doesn't really matter, but the manual suggests
742 // setting it to one.
743 cr0.pe = 1; // We're definitely in protected mode.
744 tc->setMiscReg(MISCREG_CR0, cr0);
745
746 tc->setMiscReg(MISCREG_MXCSR, 0x1f80);
747 }
748}
749
750template<class IntType>
751void
752X86Process::argsInit(int pageSize,
753 std::vector<AuxVector<IntType> > extraAuxvs)
754{
755 int intSize = sizeof(IntType);
756
757 typedef AuxVector<IntType> auxv_t;
758 std::vector<auxv_t> auxv = extraAuxvs;
759
760 string filename;
761 if (argv.size() < 1)
762 filename = "";
763 else
764 filename = argv[0];
765
766 // We want 16 byte alignment
767 uint64_t align = 16;
768
769 // Patch the ld_bias for dynamic executables.
770 updateBias();
771
772 // load object file into target memory
773 objFile->loadSections(initVirtMem);
774
775 enum X86CpuFeature {
776 X86_OnboardFPU = 1 << 0,
777 X86_VirtualModeExtensions = 1 << 1,
778 X86_DebuggingExtensions = 1 << 2,
779 X86_PageSizeExtensions = 1 << 3,
780
781 X86_TimeStampCounter = 1 << 4,
782 X86_ModelSpecificRegisters = 1 << 5,
783 X86_PhysicalAddressExtensions = 1 << 6,
784 X86_MachineCheckExtensions = 1 << 7,
785
786 X86_CMPXCHG8Instruction = 1 << 8,
787 X86_OnboardAPIC = 1 << 9,
788 X86_SYSENTER_SYSEXIT = 1 << 11,
789
790 X86_MemoryTypeRangeRegisters = 1 << 12,
791 X86_PageGlobalEnable = 1 << 13,
792 X86_MachineCheckArchitecture = 1 << 14,
793 X86_CMOVInstruction = 1 << 15,
794
795 X86_PageAttributeTable = 1 << 16,
796 X86_36BitPSEs = 1 << 17,
797 X86_ProcessorSerialNumber = 1 << 18,
798 X86_CLFLUSHInstruction = 1 << 19,
799
800 X86_DebugTraceStore = 1 << 21,
801 X86_ACPIViaMSR = 1 << 22,
802 X86_MultimediaExtensions = 1 << 23,
803
804 X86_FXSAVE_FXRSTOR = 1 << 24,
805 X86_StreamingSIMDExtensions = 1 << 25,
806 X86_StreamingSIMDExtensions2 = 1 << 26,
807 X86_CPUSelfSnoop = 1 << 27,
808
809 X86_HyperThreading = 1 << 28,
810 X86_AutomaticClockControl = 1 << 29,
811 X86_IA64Processor = 1 << 30
812 };
813
814 // Setup the auxiliary vectors. These will already have endian
815 // conversion. Auxiliary vectors are loaded only for elf formatted
816 // executables; the auxv is responsible for passing information from
817 // the OS to the interpreter.
818 ElfObject * elfObject = dynamic_cast<ElfObject *>(objFile);
819 if (elfObject) {
820 uint64_t features =
821 X86_OnboardFPU |
822 X86_VirtualModeExtensions |
823 X86_DebuggingExtensions |
824 X86_PageSizeExtensions |
825 X86_TimeStampCounter |
826 X86_ModelSpecificRegisters |
827 X86_PhysicalAddressExtensions |
828 X86_MachineCheckExtensions |
829 X86_CMPXCHG8Instruction |
830 X86_OnboardAPIC |
831 X86_SYSENTER_SYSEXIT |
832 X86_MemoryTypeRangeRegisters |
833 X86_PageGlobalEnable |
834 X86_MachineCheckArchitecture |
835 X86_CMOVInstruction |
836 X86_PageAttributeTable |
837 X86_36BitPSEs |
838// X86_ProcessorSerialNumber |
839 X86_CLFLUSHInstruction |
840// X86_DebugTraceStore |
841// X86_ACPIViaMSR |
842 X86_MultimediaExtensions |
843 X86_FXSAVE_FXRSTOR |
844 X86_StreamingSIMDExtensions |
845 X86_StreamingSIMDExtensions2 |
846// X86_CPUSelfSnoop |
847// X86_HyperThreading |
848// X86_AutomaticClockControl |
849// X86_IA64Processor |
850 0;
851
852 // Bits which describe the system hardware capabilities
853 // XXX Figure out what these should be
854 auxv.push_back(auxv_t(M5_AT_HWCAP, features));
855 // The system page size
856 auxv.push_back(auxv_t(M5_AT_PAGESZ, X86ISA::PageBytes));
857 // Frequency at which times() increments
858 // Defined to be 100 in the kernel source.
859 auxv.push_back(auxv_t(M5_AT_CLKTCK, 100));
860 // This is the virtual address of the program header tables if they
861 // appear in the executable image.
862 auxv.push_back(auxv_t(M5_AT_PHDR, elfObject->programHeaderTable()));
863 // This is the size of a program header entry from the elf file.
864 auxv.push_back(auxv_t(M5_AT_PHENT, elfObject->programHeaderSize()));
865 // This is the number of program headers from the original elf file.
866 auxv.push_back(auxv_t(M5_AT_PHNUM, elfObject->programHeaderCount()));
867 // This is the base address of the ELF interpreter; it should be
868 // zero for static executables or contain the base address for
869 // dynamic executables.
870 auxv.push_back(auxv_t(M5_AT_BASE, getBias()));
871 // XXX Figure out what this should be.
872 auxv.push_back(auxv_t(M5_AT_FLAGS, 0));
873 // The entry point to the program
874 auxv.push_back(auxv_t(M5_AT_ENTRY, objFile->entryPoint()));
875 // Different user and group IDs
876 auxv.push_back(auxv_t(M5_AT_UID, uid()));
877 auxv.push_back(auxv_t(M5_AT_EUID, euid()));
878 auxv.push_back(auxv_t(M5_AT_GID, gid()));
879 auxv.push_back(auxv_t(M5_AT_EGID, egid()));
880 // Whether to enable "secure mode" in the executable
881 auxv.push_back(auxv_t(M5_AT_SECURE, 0));
882 // The address of 16 "random" bytes.
883 auxv.push_back(auxv_t(M5_AT_RANDOM, 0));
884 // The name of the program
885 auxv.push_back(auxv_t(M5_AT_EXECFN, 0));
886 // The platform string
887 auxv.push_back(auxv_t(M5_AT_PLATFORM, 0));
888 }
889
890 // Figure out how big the initial stack needs to be
891
892 // A sentry NULL void pointer at the top of the stack.
893 int sentry_size = intSize;
894
895 // This is the name of the file which is present on the initial stack
896 // It's purpose is to let the user space linker examine the original file.
897 int file_name_size = filename.size() + 1;
898
899 const int numRandomBytes = 16;
900 int aux_data_size = numRandomBytes;
901
902 string platform = "x86_64";
903 aux_data_size += platform.size() + 1;
904
905 int env_data_size = 0;
906 for (int i = 0; i < envp.size(); ++i)
907 env_data_size += envp[i].size() + 1;
908 int arg_data_size = 0;
909 for (int i = 0; i < argv.size(); ++i)
910 arg_data_size += argv[i].size() + 1;
911
912 // The info_block needs to be padded so its size is a multiple of the
913 // alignment mask. Also, it appears that there needs to be at least some
914 // padding, so if the size is already a multiple, we need to increase it
915 // anyway.
916 int base_info_block_size =
917 sentry_size + file_name_size + env_data_size + arg_data_size;
918
919 int info_block_size = roundUp(base_info_block_size, align);
920
921 int info_block_padding = info_block_size - base_info_block_size;
922
923 // Each auxiliary vector is two 8 byte words
924 int aux_array_size = intSize * 2 * (auxv.size() + 1);
925
926 int envp_array_size = intSize * (envp.size() + 1);
927 int argv_array_size = intSize * (argv.size() + 1);
928
929 int argc_size = intSize;
930
931 // Figure out the size of the contents of the actual initial frame
932 int frame_size =
933 aux_array_size +
934 envp_array_size +
935 argv_array_size +
936 argc_size;
937
938 // There needs to be padding after the auxiliary vector data so that the
939 // very bottom of the stack is aligned properly.
940 int partial_size = frame_size + aux_data_size;
941 int aligned_partial_size = roundUp(partial_size, align);
942 int aux_padding = aligned_partial_size - partial_size;
943
944 int space_needed =
945 info_block_size +
946 aux_data_size +
947 aux_padding +
948 frame_size;
949
950 Addr stack_base = memState->getStackBase();
951
952 Addr stack_min = stack_base - space_needed;
953 stack_min = roundDown(stack_min, align);
954
955 unsigned stack_size = stack_base - stack_min;
956 stack_size = roundUp(stack_size, pageSize);
957 memState->setStackSize(stack_size);
958
959 // map memory
960 Addr stack_end = roundDown(stack_base - stack_size, pageSize);
961
962 DPRINTF(Stack, "Mapping the stack: 0x%x %dB\n", stack_end, stack_size);
963 allocateMem(stack_end, stack_size);
964
965 // map out initial stack contents
966 IntType sentry_base = stack_base - sentry_size;
967 IntType file_name_base = sentry_base - file_name_size;
968 IntType env_data_base = file_name_base - env_data_size;
969 IntType arg_data_base = env_data_base - arg_data_size;
970 IntType aux_data_base = arg_data_base - info_block_padding - aux_data_size;
971 IntType auxv_array_base = aux_data_base - aux_array_size - aux_padding;
972 IntType envp_array_base = auxv_array_base - envp_array_size;
973 IntType argv_array_base = envp_array_base - argv_array_size;
974 IntType argc_base = argv_array_base - argc_size;
975
976 DPRINTF(Stack, "The addresses of items on the initial stack:\n");
977 DPRINTF(Stack, "0x%x - file name\n", file_name_base);
978 DPRINTF(Stack, "0x%x - env data\n", env_data_base);
979 DPRINTF(Stack, "0x%x - arg data\n", arg_data_base);
980 DPRINTF(Stack, "0x%x - aux data\n", aux_data_base);
981 DPRINTF(Stack, "0x%x - auxv array\n", auxv_array_base);
982 DPRINTF(Stack, "0x%x - envp array\n", envp_array_base);
983 DPRINTF(Stack, "0x%x - argv array\n", argv_array_base);
984 DPRINTF(Stack, "0x%x - argc \n", argc_base);
985 DPRINTF(Stack, "0x%x - stack min\n", stack_min);
986
987 // write contents to stack
988
989 // figure out argc
990 IntType argc = argv.size();
991 IntType guestArgc = X86ISA::htog(argc);
992
993 // Write out the sentry void *
994 IntType sentry_NULL = 0;
995 initVirtMem.writeBlob(sentry_base, (uint8_t*)&sentry_NULL, sentry_size);
996
997 // Write the file name
998 initVirtMem.writeString(file_name_base, filename.c_str());
999
1000 // Fix up the aux vectors which point to data
1001 assert(auxv[auxv.size() - 3].a_type == M5_AT_RANDOM);
1002 auxv[auxv.size() - 3].a_val = aux_data_base;
1003 assert(auxv[auxv.size() - 2].a_type == M5_AT_EXECFN);
1004 auxv[auxv.size() - 2].a_val = argv_array_base;
1005 assert(auxv[auxv.size() - 1].a_type == M5_AT_PLATFORM);
1006 auxv[auxv.size() - 1].a_val = aux_data_base + numRandomBytes;
1007
1008
1009 // Copy the aux stuff
1010 for (int x = 0; x < auxv.size(); x++) {
1011 initVirtMem.writeBlob(auxv_array_base + x * 2 * intSize,
1012 (uint8_t*)&(auxv[x].a_type), intSize);
1013 initVirtMem.writeBlob(auxv_array_base + (x * 2 + 1) * intSize,
1014 (uint8_t*)&(auxv[x].a_val), intSize);
1015 }
1016 // Write out the terminating zeroed auxiliary vector
1017 const uint64_t zero = 0;
1018 initVirtMem.writeBlob(auxv_array_base + auxv.size() * 2 * intSize,
1019 (uint8_t*)&zero, intSize);
1020 initVirtMem.writeBlob(auxv_array_base + (auxv.size() * 2 + 1) * intSize,
1021 (uint8_t*)&zero, intSize);
1022
1023 initVirtMem.writeString(aux_data_base, platform.c_str());
1024
1025 copyStringArray(envp, envp_array_base, env_data_base, initVirtMem);
1026 copyStringArray(argv, argv_array_base, arg_data_base, initVirtMem);
1027
1028 initVirtMem.writeBlob(argc_base, (uint8_t*)&guestArgc, intSize);
1029
1030 ThreadContext *tc = system->getThreadContext(contextIds[0]);
1031 // Set the stack pointer register
1032 tc->setIntReg(StackPointerReg, stack_min);
1033
1034 // There doesn't need to be any segment base added in since we're dealing
1035 // with the flat segmentation model.
1036 tc->pcState(getStartPC());
1037
1038 // Align the "stack_min" to a page boundary.
1039 memState->setStackMin(roundDown(stack_min, pageSize));
1040}
1041
1042void
1043X86_64Process::argsInit(int pageSize)
1044{
1045 std::vector<AuxVector<uint64_t> > extraAuxvs;
1046 extraAuxvs.push_back(AuxVector<uint64_t>(M5_AT_SYSINFO_EHDR,
1047 vsyscallPage.base));
1048 X86Process::argsInit<uint64_t>(pageSize, extraAuxvs);
1049}
1050
1051void
1052I386Process::argsInit(int pageSize)
1053{
1054 std::vector<AuxVector<uint32_t> > extraAuxvs;
1055 //Tell the binary where the vsyscall part of the vsyscall page is.
1056 extraAuxvs.push_back(AuxVector<uint32_t>(M5_AT_SYSINFO,
1057 vsyscallPage.base + vsyscallPage.vsyscallOffset));
1058 extraAuxvs.push_back(AuxVector<uint32_t>(M5_AT_SYSINFO_EHDR,
1059 vsyscallPage.base));
1060 X86Process::argsInit<uint32_t>(pageSize, extraAuxvs);
1061}
1062
1063void
1064X86Process::setSyscallReturn(ThreadContext *tc, SyscallReturn retval)
1065{
1066 tc->setIntReg(INTREG_RAX, retval.encodedValue());
1067}
1068
1069X86ISA::IntReg
1070X86_64Process::getSyscallArg(ThreadContext *tc, int &i)
1071{
1072 assert(i < NumArgumentRegs);
1073 return tc->readIntReg(ArgumentReg[i++]);
1074}
1075
1076void
1077X86_64Process::setSyscallArg(ThreadContext *tc, int i, X86ISA::IntReg val)
1078{
1079 assert(i < NumArgumentRegs);
1080 return tc->setIntReg(ArgumentReg[i], val);
1081}
1082
1083void
1084X86_64Process::clone(ThreadContext *old_tc, ThreadContext *new_tc,
1085 Process *p, TheISA::IntReg flags)
1086{
1087 X86Process::clone(old_tc, new_tc, p, flags);
1088 ((X86_64Process*)p)->vsyscallPage = vsyscallPage;
1089}
1090
1091X86ISA::IntReg
1092I386Process::getSyscallArg(ThreadContext *tc, int &i)
1093{
1094 assert(i < NumArgumentRegs32);
1095 return tc->readIntReg(ArgumentReg32[i++]);
1096}
1097
1098X86ISA::IntReg
1099I386Process::getSyscallArg(ThreadContext *tc, int &i, int width)
1100{
1101 assert(width == 32 || width == 64);
1102 assert(i < NumArgumentRegs);
1103 uint64_t retVal = tc->readIntReg(ArgumentReg32[i++]) & mask(32);
1104 if (width == 64)
1105 retVal |= ((uint64_t)tc->readIntReg(ArgumentReg[i++]) << 32);
1106 return retVal;
1107}
1108
1109void
1110I386Process::setSyscallArg(ThreadContext *tc, int i, X86ISA::IntReg val)
1111{
1112 assert(i < NumArgumentRegs);
1113 return tc->setIntReg(ArgumentReg[i], val);
1114}
1115
1116void
1117I386Process::clone(ThreadContext *old_tc, ThreadContext *new_tc,
1118 Process *p, TheISA::IntReg flags)
1119{
1120 X86Process::clone(old_tc, new_tc, p, flags);
1121 ((I386Process*)p)->vsyscallPage = vsyscallPage;
1122}