1/*
2 * Copyright (c) 2014 Advanced Micro Devices, Inc.
3 * Copyright (c) 2007 The Hewlett-Packard Development Company
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2003-2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Gabe Black
42 * Ali Saidi
43 */
44
45#include "arch/x86/process.hh"
46
47#include <string>
48#include <vector>
49
50#include "arch/x86/isa_traits.hh"
51#include "arch/x86/regs/misc.hh"
52#include "arch/x86/regs/segment.hh"
53#include "arch/x86/system.hh"
54#include "arch/x86/types.hh"
55#include "base/loader/elf_object.hh"
56#include "base/loader/object_file.hh"
57#include "base/misc.hh"
58#include "base/trace.hh"
59#include "cpu/thread_context.hh"
60#include "debug/Stack.hh"
61#include "mem/multi_level_page_table.hh"
62#include "mem/page_table.hh"
63#include "sim/aux_vector.hh"
64#include "sim/process_impl.hh"
65#include "sim/syscall_desc.hh"
66#include "sim/syscall_return.hh"
67#include "sim/system.hh"
68
69using namespace std;
70using namespace X86ISA;
71
72static const int ArgumentReg[] = {
73 INTREG_RDI,
74 INTREG_RSI,
75 INTREG_RDX,
76 //This argument register is r10 for syscalls and rcx for C.
77 INTREG_R10W,
78 //INTREG_RCX,
79 INTREG_R8W,
80 INTREG_R9W
81};
82
83static const int NumArgumentRegs M5_VAR_USED =
84 sizeof(ArgumentReg) / sizeof(const int);
85
86static const int ArgumentReg32[] = {
87 INTREG_EBX,
88 INTREG_ECX,
89 INTREG_EDX,
90 INTREG_ESI,
91 INTREG_EDI,
92 INTREG_EBP
93};
94
95static const int NumArgumentRegs32 M5_VAR_USED =
96 sizeof(ArgumentReg) / sizeof(const int);
97
98X86Process::X86Process(ProcessParams * params, ObjectFile *objFile,
99 SyscallDesc *_syscallDescs, int _numSyscallDescs)
100 : Process(params, objFile), syscallDescs(_syscallDescs),
101 numSyscallDescs(_numSyscallDescs)
102{
103 memState->brkPoint = objFile->dataBase() + objFile->dataSize()
104 + objFile->bssSize();
105 memState->brkPoint = roundUp(memState->brkPoint, PageBytes);
106}
107
108void X86Process::clone(ThreadContext *old_tc, ThreadContext *new_tc,
109 Process *p, TheISA::IntReg flags)
110{
111 Process::clone(old_tc, new_tc, p, flags);
112 X86Process *process = (X86Process*)p;
113 *process = *this;
114}
115
116X86_64Process::X86_64Process(ProcessParams *params, ObjectFile *objFile,
117 SyscallDesc *_syscallDescs, int _numSyscallDescs)
118 : X86Process(params, objFile, _syscallDescs, _numSyscallDescs)
119{
120
121 vsyscallPage.base = 0xffffffffff600000ULL;
122 vsyscallPage.size = PageBytes;
123 vsyscallPage.vtimeOffset = 0x400;
124 vsyscallPage.vgettimeofdayOffset = 0x0;
125
126 // Set up stack. On X86_64 Linux, stack goes from the top of memory
127 // downward, less the hole for the kernel address space plus one page
128 // for undertermined purposes.
129 memState->stackBase = (Addr)0x7FFFFFFFF000ULL;
130
131 // Set pointer for next thread stack. Reserve 8M for main stack.
132 memState->nextThreadStackBase = memState->stackBase - (8 * 1024 * 1024);
133
134 // "mmap_base" is a function which defines where mmap region starts in
135 // the process address space.
136 // mmap_base: PAGE_ALIGN(TASK_SIZE-MIN_GAP-mmap_rnd())
137 // TASK_SIZE: (1<<47)-PAGE_SIZE
138 // MIN_GAP: 128*1024*1024+stack_maxrandom_size()
139 // We do not use any address space layout randomization in gem5
140 // therefore the random fields become zero; the smallest gap space was
141 // chosen but gap could potentially be much larger.
142 memState->mmapEnd = (Addr)0x7FFFF7FFF000ULL;
143}
144
145void
146I386Process::syscall(int64_t callnum, ThreadContext *tc, Fault *fault)
147{
148 TheISA::PCState pc = tc->pcState();
149 Addr eip = pc.pc();
150 if (eip >= vsyscallPage.base &&
151 eip < vsyscallPage.base + vsyscallPage.size) {
152 pc.npc(vsyscallPage.base + vsyscallPage.vsysexitOffset);
153 tc->pcState(pc);
154 }
155 X86Process::syscall(callnum, tc, fault);
156}
157
158
159I386Process::I386Process(ProcessParams *params, ObjectFile *objFile,
160 SyscallDesc *_syscallDescs, int _numSyscallDescs)
161 : X86Process(params, objFile, _syscallDescs, _numSyscallDescs)
162{
163 _gdtStart = ULL(0xffffd000);
164 _gdtSize = PageBytes;
165
166 vsyscallPage.base = 0xffffe000ULL;
167 vsyscallPage.size = PageBytes;
168 vsyscallPage.vsyscallOffset = 0x400;
169 vsyscallPage.vsysexitOffset = 0x410;
170
171 memState->stackBase = _gdtStart;
172
173 // Set pointer for next thread stack. Reserve 8M for main stack.
174 memState->nextThreadStackBase = memState->stackBase - (8 * 1024 * 1024);
175
176 // "mmap_base" is a function which defines where mmap region starts in
177 // the process address space.
178 // mmap_base: PAGE_ALIGN(TASK_SIZE-MIN_GAP-mmap_rnd())
179 // TASK_SIZE: 0xC0000000
180 // MIN_GAP: 128*1024*1024+stack_maxrandom_size()
181 // We do not use any address space layout randomization in gem5
182 // therefore the random fields become zero; the smallest gap space was
183 // chosen but gap could potentially be much larger.
184 memState->mmapEnd = (Addr)0xB7FFF000ULL;
185}
186
187SyscallDesc*
188X86Process::getDesc(int callnum)
189{
190 if (callnum < 0 || callnum >= numSyscallDescs)
191 return NULL;
192 return &syscallDescs[callnum];
193}
194
195void
196X86_64Process::initState()
197{
198 X86Process::initState();
199
200 argsInit(PageBytes);
201
202 // Set up the vsyscall page for this process.
203 allocateMem(vsyscallPage.base, vsyscallPage.size);
204 uint8_t vtimeBlob[] = {
205 0x48,0xc7,0xc0,0xc9,0x00,0x00,0x00, // mov $0xc9,%rax
206 0x0f,0x05, // syscall
207 0xc3 // retq
208 };
209 initVirtMem.writeBlob(vsyscallPage.base + vsyscallPage.vtimeOffset,
210 vtimeBlob, sizeof(vtimeBlob));
211
212 uint8_t vgettimeofdayBlob[] = {
213 0x48,0xc7,0xc0,0x60,0x00,0x00,0x00, // mov $0x60,%rax
214 0x0f,0x05, // syscall
215 0xc3 // retq
216 };
217 initVirtMem.writeBlob(vsyscallPage.base + vsyscallPage.vgettimeofdayOffset,
218 vgettimeofdayBlob, sizeof(vgettimeofdayBlob));
219
220 if (kvmInSE) {
221 PortProxy physProxy = system->physProxy;
222
223 /*
224 * Set up the gdt.
225 */
226 uint8_t numGDTEntries = 0;
227 uint64_t nullDescriptor = 0;
228 physProxy.writeBlob(GDTPhysAddr + numGDTEntries * 8,
229 (uint8_t *)(&nullDescriptor), 8);
230 numGDTEntries++;
231
232 SegDescriptor initDesc = 0;
233 initDesc.type.codeOrData = 0; // code or data type
234 initDesc.type.c = 0; // conforming
235 initDesc.type.r = 1; // readable
236 initDesc.dpl = 0; // privilege
237 initDesc.p = 1; // present
238 initDesc.l = 1; // longmode - 64 bit
239 initDesc.d = 0; // operand size
240 initDesc.g = 1; // granularity
241 initDesc.s = 1; // system segment
242 initDesc.limitHigh = 0xFFFF;
243 initDesc.limitLow = 0xF;
244 initDesc.baseHigh = 0x0;
245 initDesc.baseLow = 0x0;
246
247 //64 bit code segment
248 SegDescriptor csLowPLDesc = initDesc;
249 csLowPLDesc.type.codeOrData = 1;
250 csLowPLDesc.dpl = 0;
251 uint64_t csLowPLDescVal = csLowPLDesc;
252 physProxy.writeBlob(GDTPhysAddr + numGDTEntries * 8,
253 (uint8_t *)(&csLowPLDescVal), 8);
254
255 numGDTEntries++;
256
257 SegSelector csLowPL = 0;
258 csLowPL.si = numGDTEntries - 1;
259 csLowPL.rpl = 0;
260
261 //64 bit data segment
262 SegDescriptor dsLowPLDesc = initDesc;
263 dsLowPLDesc.type.codeOrData = 0;
264 dsLowPLDesc.dpl = 0;
265 uint64_t dsLowPLDescVal = dsLowPLDesc;
266 physProxy.writeBlob(GDTPhysAddr + numGDTEntries * 8,
267 (uint8_t *)(&dsLowPLDescVal), 8);
268
269 numGDTEntries++;
270
271 SegSelector dsLowPL = 0;
272 dsLowPL.si = numGDTEntries - 1;
273 dsLowPL.rpl = 0;
274
275 //64 bit data segment
276 SegDescriptor dsDesc = initDesc;
277 dsDesc.type.codeOrData = 0;
278 dsDesc.dpl = 3;
279 uint64_t dsDescVal = dsDesc;
280 physProxy.writeBlob(GDTPhysAddr + numGDTEntries * 8,
281 (uint8_t *)(&dsDescVal), 8);
282
283 numGDTEntries++;
284
285 SegSelector ds = 0;
286 ds.si = numGDTEntries - 1;
287 ds.rpl = 3;
288
289 //64 bit code segment
290 SegDescriptor csDesc = initDesc;
291 csDesc.type.codeOrData = 1;
292 csDesc.dpl = 3;
293 uint64_t csDescVal = csDesc;
294 physProxy.writeBlob(GDTPhysAddr + numGDTEntries * 8,
295 (uint8_t *)(&csDescVal), 8);
296
297 numGDTEntries++;
298
299 SegSelector cs = 0;
300 cs.si = numGDTEntries - 1;
301 cs.rpl = 3;
302
303 SegSelector scall = 0;
304 scall.si = csLowPL.si;
305 scall.rpl = 0;
306
307 SegSelector sret = 0;
308 sret.si = dsLowPL.si;
309 sret.rpl = 3;
310
311 /* In long mode the TSS has been extended to 16 Bytes */
312 TSSlow TSSDescLow = 0;
313 TSSDescLow.type = 0xB;
314 TSSDescLow.dpl = 0; // Privelege level 0
315 TSSDescLow.p = 1; // Present
316 TSSDescLow.g = 1; // Page granularity
317 TSSDescLow.limitHigh = 0xF;
318 TSSDescLow.limitLow = 0xFFFF;
319 TSSDescLow.baseLow = bits(TSSVirtAddr, 23, 0);
320 TSSDescLow.baseHigh = bits(TSSVirtAddr, 31, 24);
321
322 TSShigh TSSDescHigh = 0;
323 TSSDescHigh.base = bits(TSSVirtAddr, 63, 32);
324
325 struct TSSDesc {
326 uint64_t low;
327 uint64_t high;
328 } tssDescVal = {TSSDescLow, TSSDescHigh};
329
330 physProxy.writeBlob(GDTPhysAddr + numGDTEntries * 8,
331 (uint8_t *)(&tssDescVal), sizeof(tssDescVal));
332
333 numGDTEntries++;
334
335 SegSelector tssSel = 0;
336 tssSel.si = numGDTEntries - 1;
337
338 uint64_t tss_base_addr = (TSSDescHigh.base << 32) |
339 (TSSDescLow.baseHigh << 24) |
340 TSSDescLow.baseLow;
341 uint64_t tss_limit = TSSDescLow.limitLow | (TSSDescLow.limitHigh << 16);
342
343 SegAttr tss_attr = 0;
344
345 tss_attr.type = TSSDescLow.type;
346 tss_attr.dpl = TSSDescLow.dpl;
347 tss_attr.present = TSSDescLow.p;
348 tss_attr.granularity = TSSDescLow.g;
349 tss_attr.unusable = 0;
350
351 for (int i = 0; i < contextIds.size(); i++) {
352 ThreadContext * tc = system->getThreadContext(contextIds[i]);
353
354 tc->setMiscReg(MISCREG_CS, cs);
355 tc->setMiscReg(MISCREG_DS, ds);
356 tc->setMiscReg(MISCREG_ES, ds);
357 tc->setMiscReg(MISCREG_FS, ds);
358 tc->setMiscReg(MISCREG_GS, ds);
359 tc->setMiscReg(MISCREG_SS, ds);
360
361 // LDT
362 tc->setMiscReg(MISCREG_TSL, 0);
363 SegAttr tslAttr = 0;
364 tslAttr.present = 1;
365 tslAttr.type = 2;
366 tc->setMiscReg(MISCREG_TSL_ATTR, tslAttr);
367
368 tc->setMiscReg(MISCREG_TSG_BASE, GDTVirtAddr);
369 tc->setMiscReg(MISCREG_TSG_LIMIT, 8 * numGDTEntries - 1);
370
371 tc->setMiscReg(MISCREG_TR, tssSel);
372 tc->setMiscReg(MISCREG_TR_BASE, tss_base_addr);
373 tc->setMiscReg(MISCREG_TR_EFF_BASE, 0);
374 tc->setMiscReg(MISCREG_TR_LIMIT, tss_limit);
375 tc->setMiscReg(MISCREG_TR_ATTR, tss_attr);
376
377 //Start using longmode segments.
378 installSegDesc(tc, SEGMENT_REG_CS, csDesc, true);
379 installSegDesc(tc, SEGMENT_REG_DS, dsDesc, true);
380 installSegDesc(tc, SEGMENT_REG_ES, dsDesc, true);
381 installSegDesc(tc, SEGMENT_REG_FS, dsDesc, true);
382 installSegDesc(tc, SEGMENT_REG_GS, dsDesc, true);
383 installSegDesc(tc, SEGMENT_REG_SS, dsDesc, true);
384
385 Efer efer = 0;
386 efer.sce = 1; // Enable system call extensions.
387 efer.lme = 1; // Enable long mode.
388 efer.lma = 1; // Activate long mode.
389 efer.nxe = 0; // Enable nx support.
390 efer.svme = 1; // Enable svm support for now.
391 efer.ffxsr = 0; // Turn on fast fxsave and fxrstor.
392 tc->setMiscReg(MISCREG_EFER, efer);
393
394 //Set up the registers that describe the operating mode.
395 CR0 cr0 = 0;
396 cr0.pg = 1; // Turn on paging.
397 cr0.cd = 0; // Don't disable caching.
398 cr0.nw = 0; // This is bit is defined to be ignored.
399 cr0.am = 1; // No alignment checking
400 cr0.wp = 1; // Supervisor mode can write read only pages
401 cr0.ne = 1;
402 cr0.et = 1; // This should always be 1
403 cr0.ts = 0; // We don't do task switching, so causing fp exceptions
404 // would be pointless.
405 cr0.em = 0; // Allow x87 instructions to execute natively.
406 cr0.mp = 1; // This doesn't really matter, but the manual suggests
407 // setting it to one.
408 cr0.pe = 1; // We're definitely in protected mode.
409 tc->setMiscReg(MISCREG_CR0, cr0);
410
411 CR0 cr2 = 0;
412 tc->setMiscReg(MISCREG_CR2, cr2);
413
414 CR3 cr3 = pageTablePhysAddr;
415 tc->setMiscReg(MISCREG_CR3, cr3);
416
417 CR4 cr4 = 0;
418 //Turn on pae.
419 cr4.osxsave = 1; // Enable XSAVE and Proc Extended States
420 cr4.osxmmexcpt = 1; // Operating System Unmasked Exception
421 cr4.osfxsr = 1; // Operating System FXSave/FSRSTOR Support
422 cr4.pce = 0; // Performance-Monitoring Counter Enable
423 cr4.pge = 0; // Page-Global Enable
424 cr4.mce = 0; // Machine Check Enable
425 cr4.pae = 1; // Physical-Address Extension
426 cr4.pse = 0; // Page Size Extensions
427 cr4.de = 0; // Debugging Extensions
428 cr4.tsd = 0; // Time Stamp Disable
429 cr4.pvi = 0; // Protected-Mode Virtual Interrupts
430 cr4.vme = 0; // Virtual-8086 Mode Extensions
431
432 tc->setMiscReg(MISCREG_CR4, cr4);
433
434 CR4 cr8 = 0;
435 tc->setMiscReg(MISCREG_CR8, cr8);
436
437 const Addr PageMapLevel4 = pageTablePhysAddr;
438 //Point to the page tables.
439 tc->setMiscReg(MISCREG_CR3, PageMapLevel4);
440
441 tc->setMiscReg(MISCREG_MXCSR, 0x1f80);
442
443 tc->setMiscReg(MISCREG_APIC_BASE, 0xfee00900);
444
445 tc->setMiscReg(MISCREG_TSG_BASE, GDTVirtAddr);
446 tc->setMiscReg(MISCREG_TSG_LIMIT, 0xffff);
447
448 tc->setMiscReg(MISCREG_IDTR_BASE, IDTVirtAddr);
449 tc->setMiscReg(MISCREG_IDTR_LIMIT, 0xffff);
450
451 /* enabling syscall and sysret */
452 MiscReg star = ((MiscReg)sret << 48) | ((MiscReg)scall << 32);
453 tc->setMiscReg(MISCREG_STAR, star);
454 MiscReg lstar = (MiscReg)syscallCodeVirtAddr;
455 tc->setMiscReg(MISCREG_LSTAR, lstar);
456 MiscReg sfmask = (1 << 8) | (1 << 10); // TF | DF
457 tc->setMiscReg(MISCREG_SF_MASK, sfmask);
458 }
459
460 /* Set up the content of the TSS and write it to physical memory. */
461
462 struct {
463 uint32_t reserved0; // +00h
464 uint32_t RSP0_low; // +04h
465 uint32_t RSP0_high; // +08h
466 uint32_t RSP1_low; // +0Ch
467 uint32_t RSP1_high; // +10h
468 uint32_t RSP2_low; // +14h
469 uint32_t RSP2_high; // +18h
470 uint32_t reserved1; // +1Ch
471 uint32_t reserved2; // +20h
472 uint32_t IST1_low; // +24h
473 uint32_t IST1_high; // +28h
474 uint32_t IST2_low; // +2Ch
475 uint32_t IST2_high; // +30h
476 uint32_t IST3_low; // +34h
477 uint32_t IST3_high; // +38h
478 uint32_t IST4_low; // +3Ch
479 uint32_t IST4_high; // +40h
480 uint32_t IST5_low; // +44h
481 uint32_t IST5_high; // +48h
482 uint32_t IST6_low; // +4Ch
483 uint32_t IST6_high; // +50h
484 uint32_t IST7_low; // +54h
485 uint32_t IST7_high; // +58h
486 uint32_t reserved3; // +5Ch
487 uint32_t reserved4; // +60h
488 uint16_t reserved5; // +64h
489 uint16_t IO_MapBase; // +66h
490 } tss;
491
492 /** setting Interrupt Stack Table */
493 uint64_t IST_start = ISTVirtAddr + PageBytes;
494 tss.IST1_low = IST_start;
495 tss.IST1_high = IST_start >> 32;
496 tss.RSP0_low = tss.IST1_low;
497 tss.RSP0_high = tss.IST1_high;
498 tss.RSP1_low = tss.IST1_low;
499 tss.RSP1_high = tss.IST1_high;
500 tss.RSP2_low = tss.IST1_low;
501 tss.RSP2_high = tss.IST1_high;
502 physProxy.writeBlob(TSSPhysAddr, (uint8_t *)(&tss), sizeof(tss));
503
504 /* Setting IDT gates */
505 GateDescriptorLow PFGateLow = 0;
506 PFGateLow.offsetHigh = bits(PFHandlerVirtAddr, 31, 16);
507 PFGateLow.offsetLow = bits(PFHandlerVirtAddr, 15, 0);
508 PFGateLow.selector = csLowPL;
509 PFGateLow.p = 1;
510 PFGateLow.dpl = 0;
511 PFGateLow.type = 0xe; // gate interrupt type
512 PFGateLow.IST = 0; // setting IST to 0 and using RSP0
513
514 GateDescriptorHigh PFGateHigh = 0;
515 PFGateHigh.offset = bits(PFHandlerVirtAddr, 63, 32);
516
517 struct {
518 uint64_t low;
519 uint64_t high;
520 } PFGate = {PFGateLow, PFGateHigh};
521
522 physProxy.writeBlob(IDTPhysAddr + 0xE0,
523 (uint8_t *)(&PFGate), sizeof(PFGate));
524
525 /* System call handler */
526 uint8_t syscallBlob[] = {
527 // mov %rax, (0xffffc90000005600)
528 0x48, 0xa3, 0x00, 0x60, 0x00,
529 0x00, 0x00, 0xc9, 0xff, 0xff,
530 // sysret
531 0x48, 0x0f, 0x07
532 };
533
534 physProxy.writeBlob(syscallCodePhysAddr,
535 syscallBlob, sizeof(syscallBlob));
536
537 /** Page fault handler */
538 uint8_t faultBlob[] = {
539 // mov %rax, (0xffffc90000005700)
540 0x48, 0xa3, 0x00, 0x61, 0x00,
541 0x00, 0x00, 0xc9, 0xff, 0xff,
542 // add $0x8, %rsp # skip error
543 0x48, 0x83, 0xc4, 0x08,
544 // iretq
545 0x48, 0xcf
546 };
547
548 physProxy.writeBlob(PFHandlerPhysAddr, faultBlob, sizeof(faultBlob));
549
550 MultiLevelPageTable<PageTableOps> *pt =
551 dynamic_cast<MultiLevelPageTable<PageTableOps> *>(pTable);
552
553 /* Syscall handler */
554 pt->map(syscallCodeVirtAddr, syscallCodePhysAddr, PageBytes, false);
555 /* GDT */
556 pt->map(GDTVirtAddr, GDTPhysAddr, PageBytes, false);
557 /* IDT */
558 pt->map(IDTVirtAddr, IDTPhysAddr, PageBytes, false);
559 /* TSS */
560 pt->map(TSSVirtAddr, TSSPhysAddr, PageBytes, false);
561 /* IST */
562 pt->map(ISTVirtAddr, ISTPhysAddr, PageBytes, false);
563 /* PF handler */
564 pt->map(PFHandlerVirtAddr, PFHandlerPhysAddr, PageBytes, false);
565 /* MMIO region for m5ops */
566 pt->map(MMIORegionVirtAddr, MMIORegionPhysAddr, 16*PageBytes, false);
567 } else {
568 for (int i = 0; i < contextIds.size(); i++) {
569 ThreadContext * tc = system->getThreadContext(contextIds[i]);
570
571 SegAttr dataAttr = 0;
572 dataAttr.dpl = 3;
573 dataAttr.unusable = 0;
574 dataAttr.defaultSize = 1;
575 dataAttr.longMode = 1;
576 dataAttr.avl = 0;
577 dataAttr.granularity = 1;
578 dataAttr.present = 1;
579 dataAttr.type = 3;
580 dataAttr.writable = 1;
581 dataAttr.readable = 1;
582 dataAttr.expandDown = 0;
583 dataAttr.system = 1;
584
585 //Initialize the segment registers.
586 for (int seg = 0; seg < NUM_SEGMENTREGS; seg++) {
587 tc->setMiscRegNoEffect(MISCREG_SEG_BASE(seg), 0);
588 tc->setMiscRegNoEffect(MISCREG_SEG_EFF_BASE(seg), 0);
589 tc->setMiscRegNoEffect(MISCREG_SEG_ATTR(seg), dataAttr);
590 }
591
592 SegAttr csAttr = 0;
593 csAttr.dpl = 3;
594 csAttr.unusable = 0;
595 csAttr.defaultSize = 0;
596 csAttr.longMode = 1;
597 csAttr.avl = 0;
598 csAttr.granularity = 1;
599 csAttr.present = 1;
600 csAttr.type = 10;
601 csAttr.writable = 0;
602 csAttr.readable = 1;
603 csAttr.expandDown = 0;
604 csAttr.system = 1;
605
606 tc->setMiscRegNoEffect(MISCREG_CS_ATTR, csAttr);
607
608 Efer efer = 0;
609 efer.sce = 1; // Enable system call extensions.
610 efer.lme = 1; // Enable long mode.
611 efer.lma = 1; // Activate long mode.
612 efer.nxe = 1; // Enable nx support.
613 efer.svme = 0; // Disable svm support for now. It isn't implemented.
614 efer.ffxsr = 1; // Turn on fast fxsave and fxrstor.
615 tc->setMiscReg(MISCREG_EFER, efer);
616
617 //Set up the registers that describe the operating mode.
618 CR0 cr0 = 0;
619 cr0.pg = 1; // Turn on paging.
620 cr0.cd = 0; // Don't disable caching.
621 cr0.nw = 0; // This is bit is defined to be ignored.
622 cr0.am = 0; // No alignment checking
623 cr0.wp = 0; // Supervisor mode can write read only pages
624 cr0.ne = 1;
625 cr0.et = 1; // This should always be 1
626 cr0.ts = 0; // We don't do task switching, so causing fp exceptions
627 // would be pointless.
628 cr0.em = 0; // Allow x87 instructions to execute natively.
629 cr0.mp = 1; // This doesn't really matter, but the manual suggests
630 // setting it to one.
631 cr0.pe = 1; // We're definitely in protected mode.
632 tc->setMiscReg(MISCREG_CR0, cr0);
633
634 tc->setMiscReg(MISCREG_MXCSR, 0x1f80);
635 }
636 }
637}
638
639void
640I386Process::initState()
641{
642 X86Process::initState();
643
644 argsInit(PageBytes);
645
646 /*
647 * Set up a GDT for this process. The whole GDT wouldn't really be for
648 * this process, but the only parts we care about are.
649 */
650 allocateMem(_gdtStart, _gdtSize);
651 uint64_t zero = 0;
652 assert(_gdtSize % sizeof(zero) == 0);
653 for (Addr gdtCurrent = _gdtStart;
654 gdtCurrent < _gdtStart + _gdtSize; gdtCurrent += sizeof(zero)) {
655 initVirtMem.write(gdtCurrent, zero);
656 }
657
658 // Set up the vsyscall page for this process.
659 allocateMem(vsyscallPage.base, vsyscallPage.size);
660 uint8_t vsyscallBlob[] = {
661 0x51, // push %ecx
662 0x52, // push %edp
663 0x55, // push %ebp
664 0x89, 0xe5, // mov %esp, %ebp
665 0x0f, 0x34 // sysenter
666 };
667 initVirtMem.writeBlob(vsyscallPage.base + vsyscallPage.vsyscallOffset,
668 vsyscallBlob, sizeof(vsyscallBlob));
669
670 uint8_t vsysexitBlob[] = {
671 0x5d, // pop %ebp
672 0x5a, // pop %edx
673 0x59, // pop %ecx
674 0xc3 // ret
675 };
676 initVirtMem.writeBlob(vsyscallPage.base + vsyscallPage.vsysexitOffset,
677 vsysexitBlob, sizeof(vsysexitBlob));
678
679 for (int i = 0; i < contextIds.size(); i++) {
680 ThreadContext * tc = system->getThreadContext(contextIds[i]);
681
682 SegAttr dataAttr = 0;
683 dataAttr.dpl = 3;
684 dataAttr.unusable = 0;
685 dataAttr.defaultSize = 1;
686 dataAttr.longMode = 0;
687 dataAttr.avl = 0;
688 dataAttr.granularity = 1;
689 dataAttr.present = 1;
690 dataAttr.type = 3;
691 dataAttr.writable = 1;
692 dataAttr.readable = 1;
693 dataAttr.expandDown = 0;
694 dataAttr.system = 1;
695
696 //Initialize the segment registers.
697 for (int seg = 0; seg < NUM_SEGMENTREGS; seg++) {
698 tc->setMiscRegNoEffect(MISCREG_SEG_BASE(seg), 0);
699 tc->setMiscRegNoEffect(MISCREG_SEG_EFF_BASE(seg), 0);
700 tc->setMiscRegNoEffect(MISCREG_SEG_ATTR(seg), dataAttr);
701 tc->setMiscRegNoEffect(MISCREG_SEG_SEL(seg), 0xB);
702 tc->setMiscRegNoEffect(MISCREG_SEG_LIMIT(seg), (uint32_t)(-1));
703 }
704
705 SegAttr csAttr = 0;
706 csAttr.dpl = 3;
707 csAttr.unusable = 0;
708 csAttr.defaultSize = 1;
709 csAttr.longMode = 0;
710 csAttr.avl = 0;
711 csAttr.granularity = 1;
712 csAttr.present = 1;
713 csAttr.type = 0xa;
714 csAttr.writable = 0;
715 csAttr.readable = 1;
716 csAttr.expandDown = 0;
717 csAttr.system = 1;
718
719 tc->setMiscRegNoEffect(MISCREG_CS_ATTR, csAttr);
720
721 tc->setMiscRegNoEffect(MISCREG_TSG_BASE, _gdtStart);
722 tc->setMiscRegNoEffect(MISCREG_TSG_EFF_BASE, _gdtStart);
723 tc->setMiscRegNoEffect(MISCREG_TSG_LIMIT, _gdtStart + _gdtSize - 1);
724
725 // Set the LDT selector to 0 to deactivate it.
726 tc->setMiscRegNoEffect(MISCREG_TSL, 0);
727
728 Efer efer = 0;
729 efer.sce = 1; // Enable system call extensions.
730 efer.lme = 1; // Enable long mode.
731 efer.lma = 0; // Deactivate long mode.
732 efer.nxe = 1; // Enable nx support.
733 efer.svme = 0; // Disable svm support for now. It isn't implemented.
734 efer.ffxsr = 1; // Turn on fast fxsave and fxrstor.
735 tc->setMiscReg(MISCREG_EFER, efer);
736
737 //Set up the registers that describe the operating mode.
738 CR0 cr0 = 0;
739 cr0.pg = 1; // Turn on paging.
740 cr0.cd = 0; // Don't disable caching.
741 cr0.nw = 0; // This is bit is defined to be ignored.
742 cr0.am = 0; // No alignment checking
743 cr0.wp = 0; // Supervisor mode can write read only pages
744 cr0.ne = 1;
745 cr0.et = 1; // This should always be 1
746 cr0.ts = 0; // We don't do task switching, so causing fp exceptions
747 // would be pointless.
748 cr0.em = 0; // Allow x87 instructions to execute natively.
749 cr0.mp = 1; // This doesn't really matter, but the manual suggests
750 // setting it to one.
751 cr0.pe = 1; // We're definitely in protected mode.
752 tc->setMiscReg(MISCREG_CR0, cr0);
753
754 tc->setMiscReg(MISCREG_MXCSR, 0x1f80);
755 }
756}
757
758template<class IntType>
759void
760X86Process::argsInit(int pageSize,
761 std::vector<AuxVector<IntType> > extraAuxvs)
762{
763 int intSize = sizeof(IntType);
764
765 typedef AuxVector<IntType> auxv_t;
766 std::vector<auxv_t> auxv = extraAuxvs;
767
768 string filename;
769 if (argv.size() < 1)
770 filename = "";
771 else
772 filename = argv[0];
773
774 //We want 16 byte alignment
775 uint64_t align = 16;
776
777 // Patch the ld_bias for dynamic executables.
778 updateBias();
779
780 // load object file into target memory
781 objFile->loadSections(initVirtMem);
782
783 enum X86CpuFeature {
784 X86_OnboardFPU = 1 << 0,
785 X86_VirtualModeExtensions = 1 << 1,
786 X86_DebuggingExtensions = 1 << 2,
787 X86_PageSizeExtensions = 1 << 3,
788
789 X86_TimeStampCounter = 1 << 4,
790 X86_ModelSpecificRegisters = 1 << 5,
791 X86_PhysicalAddressExtensions = 1 << 6,
792 X86_MachineCheckExtensions = 1 << 7,
793
794 X86_CMPXCHG8Instruction = 1 << 8,
795 X86_OnboardAPIC = 1 << 9,
796 X86_SYSENTER_SYSEXIT = 1 << 11,
797
798 X86_MemoryTypeRangeRegisters = 1 << 12,
799 X86_PageGlobalEnable = 1 << 13,
800 X86_MachineCheckArchitecture = 1 << 14,
801 X86_CMOVInstruction = 1 << 15,
802
803 X86_PageAttributeTable = 1 << 16,
804 X86_36BitPSEs = 1 << 17,
805 X86_ProcessorSerialNumber = 1 << 18,
806 X86_CLFLUSHInstruction = 1 << 19,
807
808 X86_DebugTraceStore = 1 << 21,
809 X86_ACPIViaMSR = 1 << 22,
810 X86_MultimediaExtensions = 1 << 23,
811
812 X86_FXSAVE_FXRSTOR = 1 << 24,
813 X86_StreamingSIMDExtensions = 1 << 25,
814 X86_StreamingSIMDExtensions2 = 1 << 26,
815 X86_CPUSelfSnoop = 1 << 27,
816
817 X86_HyperThreading = 1 << 28,
818 X86_AutomaticClockControl = 1 << 29,
819 X86_IA64Processor = 1 << 30
820 };
821
822 // Setup the auxiliary vectors. These will already have endian
823 // conversion. Auxiliary vectors are loaded only for elf formatted
824 // executables; the auxv is responsible for passing information from
825 // the OS to the interpreter.
826 ElfObject * elfObject = dynamic_cast<ElfObject *>(objFile);
827 if (elfObject) {
828 uint64_t features =
829 X86_OnboardFPU |
830 X86_VirtualModeExtensions |
831 X86_DebuggingExtensions |
832 X86_PageSizeExtensions |
833 X86_TimeStampCounter |
834 X86_ModelSpecificRegisters |
835 X86_PhysicalAddressExtensions |
836 X86_MachineCheckExtensions |
837 X86_CMPXCHG8Instruction |
838 X86_OnboardAPIC |
839 X86_SYSENTER_SYSEXIT |
840 X86_MemoryTypeRangeRegisters |
841 X86_PageGlobalEnable |
842 X86_MachineCheckArchitecture |
843 X86_CMOVInstruction |
844 X86_PageAttributeTable |
845 X86_36BitPSEs |
846// X86_ProcessorSerialNumber |
847 X86_CLFLUSHInstruction |
848// X86_DebugTraceStore |
849// X86_ACPIViaMSR |
850 X86_MultimediaExtensions |
851 X86_FXSAVE_FXRSTOR |
852 X86_StreamingSIMDExtensions |
853 X86_StreamingSIMDExtensions2 |
854// X86_CPUSelfSnoop |
855// X86_HyperThreading |
856// X86_AutomaticClockControl |
857// X86_IA64Processor |
858 0;
859
860 //Bits which describe the system hardware capabilities
861 //XXX Figure out what these should be
862 auxv.push_back(auxv_t(M5_AT_HWCAP, features));
863 //The system page size
864 auxv.push_back(auxv_t(M5_AT_PAGESZ, X86ISA::PageBytes));
865 //Frequency at which times() increments
866 //Defined to be 100 in the kernel source.
867 auxv.push_back(auxv_t(M5_AT_CLKTCK, 100));
868 // This is the virtual address of the program header tables if they
869 // appear in the executable image.
870 auxv.push_back(auxv_t(M5_AT_PHDR, elfObject->programHeaderTable()));
871 // This is the size of a program header entry from the elf file.
872 auxv.push_back(auxv_t(M5_AT_PHENT, elfObject->programHeaderSize()));
873 // This is the number of program headers from the original elf file.
874 auxv.push_back(auxv_t(M5_AT_PHNUM, elfObject->programHeaderCount()));
875 // This is the base address of the ELF interpreter; it should be
876 // zero for static executables or contain the base address for
877 // dynamic executables.
878 auxv.push_back(auxv_t(M5_AT_BASE, getBias()));
879 //XXX Figure out what this should be.
880 auxv.push_back(auxv_t(M5_AT_FLAGS, 0));
881 //The entry point to the program
882 auxv.push_back(auxv_t(M5_AT_ENTRY, objFile->entryPoint()));
883 //Different user and group IDs
884 auxv.push_back(auxv_t(M5_AT_UID, uid()));
885 auxv.push_back(auxv_t(M5_AT_EUID, euid()));
886 auxv.push_back(auxv_t(M5_AT_GID, gid()));
887 auxv.push_back(auxv_t(M5_AT_EGID, egid()));
888 //Whether to enable "secure mode" in the executable
889 auxv.push_back(auxv_t(M5_AT_SECURE, 0));
890 //The address of 16 "random" bytes.
891 auxv.push_back(auxv_t(M5_AT_RANDOM, 0));
892 //The name of the program
893 auxv.push_back(auxv_t(M5_AT_EXECFN, 0));
894 //The platform string
895 auxv.push_back(auxv_t(M5_AT_PLATFORM, 0));
896 }
897
898 //Figure out how big the initial stack needs to be
899
900 // A sentry NULL void pointer at the top of the stack.
901 int sentry_size = intSize;
902
903 //This is the name of the file which is present on the initial stack
904 //It's purpose is to let the user space linker examine the original file.
905 int file_name_size = filename.size() + 1;
906
907 const int numRandomBytes = 16;
908 int aux_data_size = numRandomBytes;
909
910 string platform = "x86_64";
911 aux_data_size += platform.size() + 1;
912
913 int env_data_size = 0;
914 for (int i = 0; i < envp.size(); ++i)
915 env_data_size += envp[i].size() + 1;
916 int arg_data_size = 0;
917 for (int i = 0; i < argv.size(); ++i)
918 arg_data_size += argv[i].size() + 1;
919
920 //The info_block needs to be padded so it's size is a multiple of the
921 //alignment mask. Also, it appears that there needs to be at least some
922 //padding, so if the size is already a multiple, we need to increase it
923 //anyway.
924 int base_info_block_size =
925 sentry_size + file_name_size + env_data_size + arg_data_size;
926
927 int info_block_size = roundUp(base_info_block_size, align);
928
929 int info_block_padding = info_block_size - base_info_block_size;
930
931 //Each auxilliary vector is two 8 byte words
932 int aux_array_size = intSize * 2 * (auxv.size() + 1);
933
934 int envp_array_size = intSize * (envp.size() + 1);
935 int argv_array_size = intSize * (argv.size() + 1);
936
937 int argc_size = intSize;
938
939 //Figure out the size of the contents of the actual initial frame
940 int frame_size =
941 aux_array_size +
942 envp_array_size +
943 argv_array_size +
944 argc_size;
945
946 //There needs to be padding after the auxiliary vector data so that the
947 //very bottom of the stack is aligned properly.
948 int partial_size = frame_size + aux_data_size;
949 int aligned_partial_size = roundUp(partial_size, align);
950 int aux_padding = aligned_partial_size - partial_size;
951
952 int space_needed =
953 info_block_size +
954 aux_data_size +
955 aux_padding +
956 frame_size;
957
958 memState->stackMin = memState->stackBase - space_needed;
959 memState->stackMin = roundDown(memState->stackMin, align);
960 memState->stackSize = roundUp(memState->stackBase - memState->stackMin,
961 pageSize);
962
963 // map memory
964 Addr stack_end = roundDown(memState->stackBase - memState->stackSize,
965 pageSize);
966
967 DPRINTF(Stack, "Mapping the stack: 0x%x %dB\n",
968 stack_end, memState->stackSize);
969 allocateMem(stack_end, memState->stackSize);
970
971 // map out initial stack contents
972 IntType sentry_base = memState->stackBase - sentry_size;
973 IntType file_name_base = sentry_base - file_name_size;
974 IntType env_data_base = file_name_base - env_data_size;
975 IntType arg_data_base = env_data_base - arg_data_size;
976 IntType aux_data_base = arg_data_base - info_block_padding - aux_data_size;
977 IntType auxv_array_base = aux_data_base - aux_array_size - aux_padding;
978 IntType envp_array_base = auxv_array_base - envp_array_size;
979 IntType argv_array_base = envp_array_base - argv_array_size;
980 IntType argc_base = argv_array_base - argc_size;
981
982 DPRINTF(Stack, "The addresses of items on the initial stack:\n");
983 DPRINTF(Stack, "0x%x - file name\n", file_name_base);
984 DPRINTF(Stack, "0x%x - env data\n", env_data_base);
985 DPRINTF(Stack, "0x%x - arg data\n", arg_data_base);
986 DPRINTF(Stack, "0x%x - aux data\n", aux_data_base);
987 DPRINTF(Stack, "0x%x - auxv array\n", auxv_array_base);
988 DPRINTF(Stack, "0x%x - envp array\n", envp_array_base);
989 DPRINTF(Stack, "0x%x - argv array\n", argv_array_base);
990 DPRINTF(Stack, "0x%x - argc \n", argc_base);
991 DPRINTF(Stack, "0x%x - stack min\n", memState->stackMin);
992
993 // write contents to stack
994
995 // figure out argc
996 IntType argc = argv.size();
997 IntType guestArgc = X86ISA::htog(argc);
998
999 //Write out the sentry void *
1000 IntType sentry_NULL = 0;
1001 initVirtMem.writeBlob(sentry_base,
1002 (uint8_t*)&sentry_NULL, sentry_size);
1003
1004 //Write the file name
1005 initVirtMem.writeString(file_name_base, filename.c_str());
1006
1007 //Fix up the aux vectors which point to data
1008 assert(auxv[auxv.size() - 3].a_type == M5_AT_RANDOM);
1009 auxv[auxv.size() - 3].a_val = aux_data_base;
1010 assert(auxv[auxv.size() - 2].a_type == M5_AT_EXECFN);
1011 auxv[auxv.size() - 2].a_val = argv_array_base;
1012 assert(auxv[auxv.size() - 1].a_type == M5_AT_PLATFORM);
1013 auxv[auxv.size() - 1].a_val = aux_data_base + numRandomBytes;
1014
1015 //Copy the aux stuff
1016 for (int x = 0; x < auxv.size(); x++) {
1017 initVirtMem.writeBlob(auxv_array_base + x * 2 * intSize,
1018 (uint8_t*)&(auxv[x].a_type), intSize);
1019 initVirtMem.writeBlob(auxv_array_base + (x * 2 + 1) * intSize,
1020 (uint8_t*)&(auxv[x].a_val), intSize);
1021 }
1022 //Write out the terminating zeroed auxilliary vector
1023 const uint64_t zero = 0;
1024 initVirtMem.writeBlob(auxv_array_base + auxv.size() * 2 * intSize,
1025 (uint8_t*)&zero, intSize);
1026 initVirtMem.writeBlob(auxv_array_base + (auxv.size() * 2 + 1) * intSize,
1027 (uint8_t*)&zero, intSize);
1028
1029 initVirtMem.writeString(aux_data_base, platform.c_str());
1030
1031 copyStringArray(envp, envp_array_base, env_data_base, initVirtMem);
1032 copyStringArray(argv, argv_array_base, arg_data_base, initVirtMem);
1033
1034 initVirtMem.writeBlob(argc_base, (uint8_t*)&guestArgc, intSize);
1035
1036 ThreadContext *tc = system->getThreadContext(contextIds[0]);
1037 //Set the stack pointer register
1038 tc->setIntReg(StackPointerReg, memState->stackMin);
1039
1040 // There doesn't need to be any segment base added in since we're dealing
1041 // with the flat segmentation model.
1042 tc->pcState(getStartPC());
1043
1044 //Align the "stack_min" to a page boundary.
1045 memState->stackMin = roundDown(memState->stackMin, pageSize);
1046}
1047
1048void
1049X86_64Process::argsInit(int pageSize)
1050{
1051 std::vector<AuxVector<uint64_t> > extraAuxvs;
1052 extraAuxvs.push_back(AuxVector<uint64_t>(M5_AT_SYSINFO_EHDR,
1053 vsyscallPage.base));
1054 X86Process::argsInit<uint64_t>(pageSize, extraAuxvs);
1055}
1056
1057void
1058I386Process::argsInit(int pageSize)
1059{
1060 std::vector<AuxVector<uint32_t> > extraAuxvs;
1061 //Tell the binary where the vsyscall part of the vsyscall page is.
1062 extraAuxvs.push_back(AuxVector<uint32_t>(M5_AT_SYSINFO,
1063 vsyscallPage.base + vsyscallPage.vsyscallOffset));
1064 extraAuxvs.push_back(AuxVector<uint32_t>(M5_AT_SYSINFO_EHDR,
1065 vsyscallPage.base));
1066 X86Process::argsInit<uint32_t>(pageSize, extraAuxvs);
1067}
1068
1069void
1070X86Process::setSyscallReturn(ThreadContext *tc, SyscallReturn retval)
1071{
1072 tc->setIntReg(INTREG_RAX, retval.encodedValue());
1073}
1074
1075X86ISA::IntReg
1076X86_64Process::getSyscallArg(ThreadContext *tc, int &i)
1077{
1078 assert(i < NumArgumentRegs);
1079 return tc->readIntReg(ArgumentReg[i++]);
1080}
1081
1082void
1083X86_64Process::setSyscallArg(ThreadContext *tc, int i, X86ISA::IntReg val)
1084{
1085 assert(i < NumArgumentRegs);
1086 return tc->setIntReg(ArgumentReg[i], val);
1087}
1088
1089void
1090X86_64Process::clone(ThreadContext *old_tc, ThreadContext *new_tc,
1091 Process *p, TheISA::IntReg flags)
1092{
1093 X86Process::clone(old_tc, new_tc, p, flags);
1094 ((X86_64Process*)p)->vsyscallPage = vsyscallPage;
1095}
1096
1097X86ISA::IntReg
1098I386Process::getSyscallArg(ThreadContext *tc, int &i)
1099{
1100 assert(i < NumArgumentRegs32);
1101 return tc->readIntReg(ArgumentReg32[i++]);
1102}
1103
1104X86ISA::IntReg
1105I386Process::getSyscallArg(ThreadContext *tc, int &i, int width)
1106{
1107 assert(width == 32 || width == 64);
1108 assert(i < NumArgumentRegs);
1109 uint64_t retVal = tc->readIntReg(ArgumentReg32[i++]) & mask(32);
1110 if (width == 64)
1111 retVal |= ((uint64_t)tc->readIntReg(ArgumentReg[i++]) << 32);
1112 return retVal;
1113}
1114
1115void
1116I386Process::setSyscallArg(ThreadContext *tc, int i, X86ISA::IntReg val)
1117{
1118 assert(i < NumArgumentRegs);
1119 return tc->setIntReg(ArgumentReg[i], val);
1120}
1121
1122void
1123I386Process::clone(ThreadContext *old_tc, ThreadContext *new_tc,
1124 Process *p, TheISA::IntReg flags)
1125{
1126 X86Process::clone(old_tc, new_tc, p, flags);
1127 ((I386Process*)p)->vsyscallPage = vsyscallPage;
1128}
2 * Copyright (c) 2014 Advanced Micro Devices, Inc.
3 * Copyright (c) 2007 The Hewlett-Packard Development Company
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2003-2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Gabe Black
42 * Ali Saidi
43 */
44
45#include "arch/x86/process.hh"
46
47#include <string>
48#include <vector>
49
50#include "arch/x86/isa_traits.hh"
51#include "arch/x86/regs/misc.hh"
52#include "arch/x86/regs/segment.hh"
53#include "arch/x86/system.hh"
54#include "arch/x86/types.hh"
55#include "base/loader/elf_object.hh"
56#include "base/loader/object_file.hh"
57#include "base/misc.hh"
58#include "base/trace.hh"
59#include "cpu/thread_context.hh"
60#include "debug/Stack.hh"
61#include "mem/multi_level_page_table.hh"
62#include "mem/page_table.hh"
63#include "sim/aux_vector.hh"
64#include "sim/process_impl.hh"
65#include "sim/syscall_desc.hh"
66#include "sim/syscall_return.hh"
67#include "sim/system.hh"
68
69using namespace std;
70using namespace X86ISA;
71
72static const int ArgumentReg[] = {
73 INTREG_RDI,
74 INTREG_RSI,
75 INTREG_RDX,
76 //This argument register is r10 for syscalls and rcx for C.
77 INTREG_R10W,
78 //INTREG_RCX,
79 INTREG_R8W,
80 INTREG_R9W
81};
82
83static const int NumArgumentRegs M5_VAR_USED =
84 sizeof(ArgumentReg) / sizeof(const int);
85
86static const int ArgumentReg32[] = {
87 INTREG_EBX,
88 INTREG_ECX,
89 INTREG_EDX,
90 INTREG_ESI,
91 INTREG_EDI,
92 INTREG_EBP
93};
94
95static const int NumArgumentRegs32 M5_VAR_USED =
96 sizeof(ArgumentReg) / sizeof(const int);
97
98X86Process::X86Process(ProcessParams * params, ObjectFile *objFile,
99 SyscallDesc *_syscallDescs, int _numSyscallDescs)
100 : Process(params, objFile), syscallDescs(_syscallDescs),
101 numSyscallDescs(_numSyscallDescs)
102{
103 memState->brkPoint = objFile->dataBase() + objFile->dataSize()
104 + objFile->bssSize();
105 memState->brkPoint = roundUp(memState->brkPoint, PageBytes);
106}
107
108void X86Process::clone(ThreadContext *old_tc, ThreadContext *new_tc,
109 Process *p, TheISA::IntReg flags)
110{
111 Process::clone(old_tc, new_tc, p, flags);
112 X86Process *process = (X86Process*)p;
113 *process = *this;
114}
115
116X86_64Process::X86_64Process(ProcessParams *params, ObjectFile *objFile,
117 SyscallDesc *_syscallDescs, int _numSyscallDescs)
118 : X86Process(params, objFile, _syscallDescs, _numSyscallDescs)
119{
120
121 vsyscallPage.base = 0xffffffffff600000ULL;
122 vsyscallPage.size = PageBytes;
123 vsyscallPage.vtimeOffset = 0x400;
124 vsyscallPage.vgettimeofdayOffset = 0x0;
125
126 // Set up stack. On X86_64 Linux, stack goes from the top of memory
127 // downward, less the hole for the kernel address space plus one page
128 // for undertermined purposes.
129 memState->stackBase = (Addr)0x7FFFFFFFF000ULL;
130
131 // Set pointer for next thread stack. Reserve 8M for main stack.
132 memState->nextThreadStackBase = memState->stackBase - (8 * 1024 * 1024);
133
134 // "mmap_base" is a function which defines where mmap region starts in
135 // the process address space.
136 // mmap_base: PAGE_ALIGN(TASK_SIZE-MIN_GAP-mmap_rnd())
137 // TASK_SIZE: (1<<47)-PAGE_SIZE
138 // MIN_GAP: 128*1024*1024+stack_maxrandom_size()
139 // We do not use any address space layout randomization in gem5
140 // therefore the random fields become zero; the smallest gap space was
141 // chosen but gap could potentially be much larger.
142 memState->mmapEnd = (Addr)0x7FFFF7FFF000ULL;
143}
144
145void
146I386Process::syscall(int64_t callnum, ThreadContext *tc, Fault *fault)
147{
148 TheISA::PCState pc = tc->pcState();
149 Addr eip = pc.pc();
150 if (eip >= vsyscallPage.base &&
151 eip < vsyscallPage.base + vsyscallPage.size) {
152 pc.npc(vsyscallPage.base + vsyscallPage.vsysexitOffset);
153 tc->pcState(pc);
154 }
155 X86Process::syscall(callnum, tc, fault);
156}
157
158
159I386Process::I386Process(ProcessParams *params, ObjectFile *objFile,
160 SyscallDesc *_syscallDescs, int _numSyscallDescs)
161 : X86Process(params, objFile, _syscallDescs, _numSyscallDescs)
162{
163 _gdtStart = ULL(0xffffd000);
164 _gdtSize = PageBytes;
165
166 vsyscallPage.base = 0xffffe000ULL;
167 vsyscallPage.size = PageBytes;
168 vsyscallPage.vsyscallOffset = 0x400;
169 vsyscallPage.vsysexitOffset = 0x410;
170
171 memState->stackBase = _gdtStart;
172
173 // Set pointer for next thread stack. Reserve 8M for main stack.
174 memState->nextThreadStackBase = memState->stackBase - (8 * 1024 * 1024);
175
176 // "mmap_base" is a function which defines where mmap region starts in
177 // the process address space.
178 // mmap_base: PAGE_ALIGN(TASK_SIZE-MIN_GAP-mmap_rnd())
179 // TASK_SIZE: 0xC0000000
180 // MIN_GAP: 128*1024*1024+stack_maxrandom_size()
181 // We do not use any address space layout randomization in gem5
182 // therefore the random fields become zero; the smallest gap space was
183 // chosen but gap could potentially be much larger.
184 memState->mmapEnd = (Addr)0xB7FFF000ULL;
185}
186
187SyscallDesc*
188X86Process::getDesc(int callnum)
189{
190 if (callnum < 0 || callnum >= numSyscallDescs)
191 return NULL;
192 return &syscallDescs[callnum];
193}
194
195void
196X86_64Process::initState()
197{
198 X86Process::initState();
199
200 argsInit(PageBytes);
201
202 // Set up the vsyscall page for this process.
203 allocateMem(vsyscallPage.base, vsyscallPage.size);
204 uint8_t vtimeBlob[] = {
205 0x48,0xc7,0xc0,0xc9,0x00,0x00,0x00, // mov $0xc9,%rax
206 0x0f,0x05, // syscall
207 0xc3 // retq
208 };
209 initVirtMem.writeBlob(vsyscallPage.base + vsyscallPage.vtimeOffset,
210 vtimeBlob, sizeof(vtimeBlob));
211
212 uint8_t vgettimeofdayBlob[] = {
213 0x48,0xc7,0xc0,0x60,0x00,0x00,0x00, // mov $0x60,%rax
214 0x0f,0x05, // syscall
215 0xc3 // retq
216 };
217 initVirtMem.writeBlob(vsyscallPage.base + vsyscallPage.vgettimeofdayOffset,
218 vgettimeofdayBlob, sizeof(vgettimeofdayBlob));
219
220 if (kvmInSE) {
221 PortProxy physProxy = system->physProxy;
222
223 /*
224 * Set up the gdt.
225 */
226 uint8_t numGDTEntries = 0;
227 uint64_t nullDescriptor = 0;
228 physProxy.writeBlob(GDTPhysAddr + numGDTEntries * 8,
229 (uint8_t *)(&nullDescriptor), 8);
230 numGDTEntries++;
231
232 SegDescriptor initDesc = 0;
233 initDesc.type.codeOrData = 0; // code or data type
234 initDesc.type.c = 0; // conforming
235 initDesc.type.r = 1; // readable
236 initDesc.dpl = 0; // privilege
237 initDesc.p = 1; // present
238 initDesc.l = 1; // longmode - 64 bit
239 initDesc.d = 0; // operand size
240 initDesc.g = 1; // granularity
241 initDesc.s = 1; // system segment
242 initDesc.limitHigh = 0xFFFF;
243 initDesc.limitLow = 0xF;
244 initDesc.baseHigh = 0x0;
245 initDesc.baseLow = 0x0;
246
247 //64 bit code segment
248 SegDescriptor csLowPLDesc = initDesc;
249 csLowPLDesc.type.codeOrData = 1;
250 csLowPLDesc.dpl = 0;
251 uint64_t csLowPLDescVal = csLowPLDesc;
252 physProxy.writeBlob(GDTPhysAddr + numGDTEntries * 8,
253 (uint8_t *)(&csLowPLDescVal), 8);
254
255 numGDTEntries++;
256
257 SegSelector csLowPL = 0;
258 csLowPL.si = numGDTEntries - 1;
259 csLowPL.rpl = 0;
260
261 //64 bit data segment
262 SegDescriptor dsLowPLDesc = initDesc;
263 dsLowPLDesc.type.codeOrData = 0;
264 dsLowPLDesc.dpl = 0;
265 uint64_t dsLowPLDescVal = dsLowPLDesc;
266 physProxy.writeBlob(GDTPhysAddr + numGDTEntries * 8,
267 (uint8_t *)(&dsLowPLDescVal), 8);
268
269 numGDTEntries++;
270
271 SegSelector dsLowPL = 0;
272 dsLowPL.si = numGDTEntries - 1;
273 dsLowPL.rpl = 0;
274
275 //64 bit data segment
276 SegDescriptor dsDesc = initDesc;
277 dsDesc.type.codeOrData = 0;
278 dsDesc.dpl = 3;
279 uint64_t dsDescVal = dsDesc;
280 physProxy.writeBlob(GDTPhysAddr + numGDTEntries * 8,
281 (uint8_t *)(&dsDescVal), 8);
282
283 numGDTEntries++;
284
285 SegSelector ds = 0;
286 ds.si = numGDTEntries - 1;
287 ds.rpl = 3;
288
289 //64 bit code segment
290 SegDescriptor csDesc = initDesc;
291 csDesc.type.codeOrData = 1;
292 csDesc.dpl = 3;
293 uint64_t csDescVal = csDesc;
294 physProxy.writeBlob(GDTPhysAddr + numGDTEntries * 8,
295 (uint8_t *)(&csDescVal), 8);
296
297 numGDTEntries++;
298
299 SegSelector cs = 0;
300 cs.si = numGDTEntries - 1;
301 cs.rpl = 3;
302
303 SegSelector scall = 0;
304 scall.si = csLowPL.si;
305 scall.rpl = 0;
306
307 SegSelector sret = 0;
308 sret.si = dsLowPL.si;
309 sret.rpl = 3;
310
311 /* In long mode the TSS has been extended to 16 Bytes */
312 TSSlow TSSDescLow = 0;
313 TSSDescLow.type = 0xB;
314 TSSDescLow.dpl = 0; // Privelege level 0
315 TSSDescLow.p = 1; // Present
316 TSSDescLow.g = 1; // Page granularity
317 TSSDescLow.limitHigh = 0xF;
318 TSSDescLow.limitLow = 0xFFFF;
319 TSSDescLow.baseLow = bits(TSSVirtAddr, 23, 0);
320 TSSDescLow.baseHigh = bits(TSSVirtAddr, 31, 24);
321
322 TSShigh TSSDescHigh = 0;
323 TSSDescHigh.base = bits(TSSVirtAddr, 63, 32);
324
325 struct TSSDesc {
326 uint64_t low;
327 uint64_t high;
328 } tssDescVal = {TSSDescLow, TSSDescHigh};
329
330 physProxy.writeBlob(GDTPhysAddr + numGDTEntries * 8,
331 (uint8_t *)(&tssDescVal), sizeof(tssDescVal));
332
333 numGDTEntries++;
334
335 SegSelector tssSel = 0;
336 tssSel.si = numGDTEntries - 1;
337
338 uint64_t tss_base_addr = (TSSDescHigh.base << 32) |
339 (TSSDescLow.baseHigh << 24) |
340 TSSDescLow.baseLow;
341 uint64_t tss_limit = TSSDescLow.limitLow | (TSSDescLow.limitHigh << 16);
342
343 SegAttr tss_attr = 0;
344
345 tss_attr.type = TSSDescLow.type;
346 tss_attr.dpl = TSSDescLow.dpl;
347 tss_attr.present = TSSDescLow.p;
348 tss_attr.granularity = TSSDescLow.g;
349 tss_attr.unusable = 0;
350
351 for (int i = 0; i < contextIds.size(); i++) {
352 ThreadContext * tc = system->getThreadContext(contextIds[i]);
353
354 tc->setMiscReg(MISCREG_CS, cs);
355 tc->setMiscReg(MISCREG_DS, ds);
356 tc->setMiscReg(MISCREG_ES, ds);
357 tc->setMiscReg(MISCREG_FS, ds);
358 tc->setMiscReg(MISCREG_GS, ds);
359 tc->setMiscReg(MISCREG_SS, ds);
360
361 // LDT
362 tc->setMiscReg(MISCREG_TSL, 0);
363 SegAttr tslAttr = 0;
364 tslAttr.present = 1;
365 tslAttr.type = 2;
366 tc->setMiscReg(MISCREG_TSL_ATTR, tslAttr);
367
368 tc->setMiscReg(MISCREG_TSG_BASE, GDTVirtAddr);
369 tc->setMiscReg(MISCREG_TSG_LIMIT, 8 * numGDTEntries - 1);
370
371 tc->setMiscReg(MISCREG_TR, tssSel);
372 tc->setMiscReg(MISCREG_TR_BASE, tss_base_addr);
373 tc->setMiscReg(MISCREG_TR_EFF_BASE, 0);
374 tc->setMiscReg(MISCREG_TR_LIMIT, tss_limit);
375 tc->setMiscReg(MISCREG_TR_ATTR, tss_attr);
376
377 //Start using longmode segments.
378 installSegDesc(tc, SEGMENT_REG_CS, csDesc, true);
379 installSegDesc(tc, SEGMENT_REG_DS, dsDesc, true);
380 installSegDesc(tc, SEGMENT_REG_ES, dsDesc, true);
381 installSegDesc(tc, SEGMENT_REG_FS, dsDesc, true);
382 installSegDesc(tc, SEGMENT_REG_GS, dsDesc, true);
383 installSegDesc(tc, SEGMENT_REG_SS, dsDesc, true);
384
385 Efer efer = 0;
386 efer.sce = 1; // Enable system call extensions.
387 efer.lme = 1; // Enable long mode.
388 efer.lma = 1; // Activate long mode.
389 efer.nxe = 0; // Enable nx support.
390 efer.svme = 1; // Enable svm support for now.
391 efer.ffxsr = 0; // Turn on fast fxsave and fxrstor.
392 tc->setMiscReg(MISCREG_EFER, efer);
393
394 //Set up the registers that describe the operating mode.
395 CR0 cr0 = 0;
396 cr0.pg = 1; // Turn on paging.
397 cr0.cd = 0; // Don't disable caching.
398 cr0.nw = 0; // This is bit is defined to be ignored.
399 cr0.am = 1; // No alignment checking
400 cr0.wp = 1; // Supervisor mode can write read only pages
401 cr0.ne = 1;
402 cr0.et = 1; // This should always be 1
403 cr0.ts = 0; // We don't do task switching, so causing fp exceptions
404 // would be pointless.
405 cr0.em = 0; // Allow x87 instructions to execute natively.
406 cr0.mp = 1; // This doesn't really matter, but the manual suggests
407 // setting it to one.
408 cr0.pe = 1; // We're definitely in protected mode.
409 tc->setMiscReg(MISCREG_CR0, cr0);
410
411 CR0 cr2 = 0;
412 tc->setMiscReg(MISCREG_CR2, cr2);
413
414 CR3 cr3 = pageTablePhysAddr;
415 tc->setMiscReg(MISCREG_CR3, cr3);
416
417 CR4 cr4 = 0;
418 //Turn on pae.
419 cr4.osxsave = 1; // Enable XSAVE and Proc Extended States
420 cr4.osxmmexcpt = 1; // Operating System Unmasked Exception
421 cr4.osfxsr = 1; // Operating System FXSave/FSRSTOR Support
422 cr4.pce = 0; // Performance-Monitoring Counter Enable
423 cr4.pge = 0; // Page-Global Enable
424 cr4.mce = 0; // Machine Check Enable
425 cr4.pae = 1; // Physical-Address Extension
426 cr4.pse = 0; // Page Size Extensions
427 cr4.de = 0; // Debugging Extensions
428 cr4.tsd = 0; // Time Stamp Disable
429 cr4.pvi = 0; // Protected-Mode Virtual Interrupts
430 cr4.vme = 0; // Virtual-8086 Mode Extensions
431
432 tc->setMiscReg(MISCREG_CR4, cr4);
433
434 CR4 cr8 = 0;
435 tc->setMiscReg(MISCREG_CR8, cr8);
436
437 const Addr PageMapLevel4 = pageTablePhysAddr;
438 //Point to the page tables.
439 tc->setMiscReg(MISCREG_CR3, PageMapLevel4);
440
441 tc->setMiscReg(MISCREG_MXCSR, 0x1f80);
442
443 tc->setMiscReg(MISCREG_APIC_BASE, 0xfee00900);
444
445 tc->setMiscReg(MISCREG_TSG_BASE, GDTVirtAddr);
446 tc->setMiscReg(MISCREG_TSG_LIMIT, 0xffff);
447
448 tc->setMiscReg(MISCREG_IDTR_BASE, IDTVirtAddr);
449 tc->setMiscReg(MISCREG_IDTR_LIMIT, 0xffff);
450
451 /* enabling syscall and sysret */
452 MiscReg star = ((MiscReg)sret << 48) | ((MiscReg)scall << 32);
453 tc->setMiscReg(MISCREG_STAR, star);
454 MiscReg lstar = (MiscReg)syscallCodeVirtAddr;
455 tc->setMiscReg(MISCREG_LSTAR, lstar);
456 MiscReg sfmask = (1 << 8) | (1 << 10); // TF | DF
457 tc->setMiscReg(MISCREG_SF_MASK, sfmask);
458 }
459
460 /* Set up the content of the TSS and write it to physical memory. */
461
462 struct {
463 uint32_t reserved0; // +00h
464 uint32_t RSP0_low; // +04h
465 uint32_t RSP0_high; // +08h
466 uint32_t RSP1_low; // +0Ch
467 uint32_t RSP1_high; // +10h
468 uint32_t RSP2_low; // +14h
469 uint32_t RSP2_high; // +18h
470 uint32_t reserved1; // +1Ch
471 uint32_t reserved2; // +20h
472 uint32_t IST1_low; // +24h
473 uint32_t IST1_high; // +28h
474 uint32_t IST2_low; // +2Ch
475 uint32_t IST2_high; // +30h
476 uint32_t IST3_low; // +34h
477 uint32_t IST3_high; // +38h
478 uint32_t IST4_low; // +3Ch
479 uint32_t IST4_high; // +40h
480 uint32_t IST5_low; // +44h
481 uint32_t IST5_high; // +48h
482 uint32_t IST6_low; // +4Ch
483 uint32_t IST6_high; // +50h
484 uint32_t IST7_low; // +54h
485 uint32_t IST7_high; // +58h
486 uint32_t reserved3; // +5Ch
487 uint32_t reserved4; // +60h
488 uint16_t reserved5; // +64h
489 uint16_t IO_MapBase; // +66h
490 } tss;
491
492 /** setting Interrupt Stack Table */
493 uint64_t IST_start = ISTVirtAddr + PageBytes;
494 tss.IST1_low = IST_start;
495 tss.IST1_high = IST_start >> 32;
496 tss.RSP0_low = tss.IST1_low;
497 tss.RSP0_high = tss.IST1_high;
498 tss.RSP1_low = tss.IST1_low;
499 tss.RSP1_high = tss.IST1_high;
500 tss.RSP2_low = tss.IST1_low;
501 tss.RSP2_high = tss.IST1_high;
502 physProxy.writeBlob(TSSPhysAddr, (uint8_t *)(&tss), sizeof(tss));
503
504 /* Setting IDT gates */
505 GateDescriptorLow PFGateLow = 0;
506 PFGateLow.offsetHigh = bits(PFHandlerVirtAddr, 31, 16);
507 PFGateLow.offsetLow = bits(PFHandlerVirtAddr, 15, 0);
508 PFGateLow.selector = csLowPL;
509 PFGateLow.p = 1;
510 PFGateLow.dpl = 0;
511 PFGateLow.type = 0xe; // gate interrupt type
512 PFGateLow.IST = 0; // setting IST to 0 and using RSP0
513
514 GateDescriptorHigh PFGateHigh = 0;
515 PFGateHigh.offset = bits(PFHandlerVirtAddr, 63, 32);
516
517 struct {
518 uint64_t low;
519 uint64_t high;
520 } PFGate = {PFGateLow, PFGateHigh};
521
522 physProxy.writeBlob(IDTPhysAddr + 0xE0,
523 (uint8_t *)(&PFGate), sizeof(PFGate));
524
525 /* System call handler */
526 uint8_t syscallBlob[] = {
527 // mov %rax, (0xffffc90000005600)
528 0x48, 0xa3, 0x00, 0x60, 0x00,
529 0x00, 0x00, 0xc9, 0xff, 0xff,
530 // sysret
531 0x48, 0x0f, 0x07
532 };
533
534 physProxy.writeBlob(syscallCodePhysAddr,
535 syscallBlob, sizeof(syscallBlob));
536
537 /** Page fault handler */
538 uint8_t faultBlob[] = {
539 // mov %rax, (0xffffc90000005700)
540 0x48, 0xa3, 0x00, 0x61, 0x00,
541 0x00, 0x00, 0xc9, 0xff, 0xff,
542 // add $0x8, %rsp # skip error
543 0x48, 0x83, 0xc4, 0x08,
544 // iretq
545 0x48, 0xcf
546 };
547
548 physProxy.writeBlob(PFHandlerPhysAddr, faultBlob, sizeof(faultBlob));
549
550 MultiLevelPageTable<PageTableOps> *pt =
551 dynamic_cast<MultiLevelPageTable<PageTableOps> *>(pTable);
552
553 /* Syscall handler */
554 pt->map(syscallCodeVirtAddr, syscallCodePhysAddr, PageBytes, false);
555 /* GDT */
556 pt->map(GDTVirtAddr, GDTPhysAddr, PageBytes, false);
557 /* IDT */
558 pt->map(IDTVirtAddr, IDTPhysAddr, PageBytes, false);
559 /* TSS */
560 pt->map(TSSVirtAddr, TSSPhysAddr, PageBytes, false);
561 /* IST */
562 pt->map(ISTVirtAddr, ISTPhysAddr, PageBytes, false);
563 /* PF handler */
564 pt->map(PFHandlerVirtAddr, PFHandlerPhysAddr, PageBytes, false);
565 /* MMIO region for m5ops */
566 pt->map(MMIORegionVirtAddr, MMIORegionPhysAddr, 16*PageBytes, false);
567 } else {
568 for (int i = 0; i < contextIds.size(); i++) {
569 ThreadContext * tc = system->getThreadContext(contextIds[i]);
570
571 SegAttr dataAttr = 0;
572 dataAttr.dpl = 3;
573 dataAttr.unusable = 0;
574 dataAttr.defaultSize = 1;
575 dataAttr.longMode = 1;
576 dataAttr.avl = 0;
577 dataAttr.granularity = 1;
578 dataAttr.present = 1;
579 dataAttr.type = 3;
580 dataAttr.writable = 1;
581 dataAttr.readable = 1;
582 dataAttr.expandDown = 0;
583 dataAttr.system = 1;
584
585 //Initialize the segment registers.
586 for (int seg = 0; seg < NUM_SEGMENTREGS; seg++) {
587 tc->setMiscRegNoEffect(MISCREG_SEG_BASE(seg), 0);
588 tc->setMiscRegNoEffect(MISCREG_SEG_EFF_BASE(seg), 0);
589 tc->setMiscRegNoEffect(MISCREG_SEG_ATTR(seg), dataAttr);
590 }
591
592 SegAttr csAttr = 0;
593 csAttr.dpl = 3;
594 csAttr.unusable = 0;
595 csAttr.defaultSize = 0;
596 csAttr.longMode = 1;
597 csAttr.avl = 0;
598 csAttr.granularity = 1;
599 csAttr.present = 1;
600 csAttr.type = 10;
601 csAttr.writable = 0;
602 csAttr.readable = 1;
603 csAttr.expandDown = 0;
604 csAttr.system = 1;
605
606 tc->setMiscRegNoEffect(MISCREG_CS_ATTR, csAttr);
607
608 Efer efer = 0;
609 efer.sce = 1; // Enable system call extensions.
610 efer.lme = 1; // Enable long mode.
611 efer.lma = 1; // Activate long mode.
612 efer.nxe = 1; // Enable nx support.
613 efer.svme = 0; // Disable svm support for now. It isn't implemented.
614 efer.ffxsr = 1; // Turn on fast fxsave and fxrstor.
615 tc->setMiscReg(MISCREG_EFER, efer);
616
617 //Set up the registers that describe the operating mode.
618 CR0 cr0 = 0;
619 cr0.pg = 1; // Turn on paging.
620 cr0.cd = 0; // Don't disable caching.
621 cr0.nw = 0; // This is bit is defined to be ignored.
622 cr0.am = 0; // No alignment checking
623 cr0.wp = 0; // Supervisor mode can write read only pages
624 cr0.ne = 1;
625 cr0.et = 1; // This should always be 1
626 cr0.ts = 0; // We don't do task switching, so causing fp exceptions
627 // would be pointless.
628 cr0.em = 0; // Allow x87 instructions to execute natively.
629 cr0.mp = 1; // This doesn't really matter, but the manual suggests
630 // setting it to one.
631 cr0.pe = 1; // We're definitely in protected mode.
632 tc->setMiscReg(MISCREG_CR0, cr0);
633
634 tc->setMiscReg(MISCREG_MXCSR, 0x1f80);
635 }
636 }
637}
638
639void
640I386Process::initState()
641{
642 X86Process::initState();
643
644 argsInit(PageBytes);
645
646 /*
647 * Set up a GDT for this process. The whole GDT wouldn't really be for
648 * this process, but the only parts we care about are.
649 */
650 allocateMem(_gdtStart, _gdtSize);
651 uint64_t zero = 0;
652 assert(_gdtSize % sizeof(zero) == 0);
653 for (Addr gdtCurrent = _gdtStart;
654 gdtCurrent < _gdtStart + _gdtSize; gdtCurrent += sizeof(zero)) {
655 initVirtMem.write(gdtCurrent, zero);
656 }
657
658 // Set up the vsyscall page for this process.
659 allocateMem(vsyscallPage.base, vsyscallPage.size);
660 uint8_t vsyscallBlob[] = {
661 0x51, // push %ecx
662 0x52, // push %edp
663 0x55, // push %ebp
664 0x89, 0xe5, // mov %esp, %ebp
665 0x0f, 0x34 // sysenter
666 };
667 initVirtMem.writeBlob(vsyscallPage.base + vsyscallPage.vsyscallOffset,
668 vsyscallBlob, sizeof(vsyscallBlob));
669
670 uint8_t vsysexitBlob[] = {
671 0x5d, // pop %ebp
672 0x5a, // pop %edx
673 0x59, // pop %ecx
674 0xc3 // ret
675 };
676 initVirtMem.writeBlob(vsyscallPage.base + vsyscallPage.vsysexitOffset,
677 vsysexitBlob, sizeof(vsysexitBlob));
678
679 for (int i = 0; i < contextIds.size(); i++) {
680 ThreadContext * tc = system->getThreadContext(contextIds[i]);
681
682 SegAttr dataAttr = 0;
683 dataAttr.dpl = 3;
684 dataAttr.unusable = 0;
685 dataAttr.defaultSize = 1;
686 dataAttr.longMode = 0;
687 dataAttr.avl = 0;
688 dataAttr.granularity = 1;
689 dataAttr.present = 1;
690 dataAttr.type = 3;
691 dataAttr.writable = 1;
692 dataAttr.readable = 1;
693 dataAttr.expandDown = 0;
694 dataAttr.system = 1;
695
696 //Initialize the segment registers.
697 for (int seg = 0; seg < NUM_SEGMENTREGS; seg++) {
698 tc->setMiscRegNoEffect(MISCREG_SEG_BASE(seg), 0);
699 tc->setMiscRegNoEffect(MISCREG_SEG_EFF_BASE(seg), 0);
700 tc->setMiscRegNoEffect(MISCREG_SEG_ATTR(seg), dataAttr);
701 tc->setMiscRegNoEffect(MISCREG_SEG_SEL(seg), 0xB);
702 tc->setMiscRegNoEffect(MISCREG_SEG_LIMIT(seg), (uint32_t)(-1));
703 }
704
705 SegAttr csAttr = 0;
706 csAttr.dpl = 3;
707 csAttr.unusable = 0;
708 csAttr.defaultSize = 1;
709 csAttr.longMode = 0;
710 csAttr.avl = 0;
711 csAttr.granularity = 1;
712 csAttr.present = 1;
713 csAttr.type = 0xa;
714 csAttr.writable = 0;
715 csAttr.readable = 1;
716 csAttr.expandDown = 0;
717 csAttr.system = 1;
718
719 tc->setMiscRegNoEffect(MISCREG_CS_ATTR, csAttr);
720
721 tc->setMiscRegNoEffect(MISCREG_TSG_BASE, _gdtStart);
722 tc->setMiscRegNoEffect(MISCREG_TSG_EFF_BASE, _gdtStart);
723 tc->setMiscRegNoEffect(MISCREG_TSG_LIMIT, _gdtStart + _gdtSize - 1);
724
725 // Set the LDT selector to 0 to deactivate it.
726 tc->setMiscRegNoEffect(MISCREG_TSL, 0);
727
728 Efer efer = 0;
729 efer.sce = 1; // Enable system call extensions.
730 efer.lme = 1; // Enable long mode.
731 efer.lma = 0; // Deactivate long mode.
732 efer.nxe = 1; // Enable nx support.
733 efer.svme = 0; // Disable svm support for now. It isn't implemented.
734 efer.ffxsr = 1; // Turn on fast fxsave and fxrstor.
735 tc->setMiscReg(MISCREG_EFER, efer);
736
737 //Set up the registers that describe the operating mode.
738 CR0 cr0 = 0;
739 cr0.pg = 1; // Turn on paging.
740 cr0.cd = 0; // Don't disable caching.
741 cr0.nw = 0; // This is bit is defined to be ignored.
742 cr0.am = 0; // No alignment checking
743 cr0.wp = 0; // Supervisor mode can write read only pages
744 cr0.ne = 1;
745 cr0.et = 1; // This should always be 1
746 cr0.ts = 0; // We don't do task switching, so causing fp exceptions
747 // would be pointless.
748 cr0.em = 0; // Allow x87 instructions to execute natively.
749 cr0.mp = 1; // This doesn't really matter, but the manual suggests
750 // setting it to one.
751 cr0.pe = 1; // We're definitely in protected mode.
752 tc->setMiscReg(MISCREG_CR0, cr0);
753
754 tc->setMiscReg(MISCREG_MXCSR, 0x1f80);
755 }
756}
757
758template<class IntType>
759void
760X86Process::argsInit(int pageSize,
761 std::vector<AuxVector<IntType> > extraAuxvs)
762{
763 int intSize = sizeof(IntType);
764
765 typedef AuxVector<IntType> auxv_t;
766 std::vector<auxv_t> auxv = extraAuxvs;
767
768 string filename;
769 if (argv.size() < 1)
770 filename = "";
771 else
772 filename = argv[0];
773
774 //We want 16 byte alignment
775 uint64_t align = 16;
776
777 // Patch the ld_bias for dynamic executables.
778 updateBias();
779
780 // load object file into target memory
781 objFile->loadSections(initVirtMem);
782
783 enum X86CpuFeature {
784 X86_OnboardFPU = 1 << 0,
785 X86_VirtualModeExtensions = 1 << 1,
786 X86_DebuggingExtensions = 1 << 2,
787 X86_PageSizeExtensions = 1 << 3,
788
789 X86_TimeStampCounter = 1 << 4,
790 X86_ModelSpecificRegisters = 1 << 5,
791 X86_PhysicalAddressExtensions = 1 << 6,
792 X86_MachineCheckExtensions = 1 << 7,
793
794 X86_CMPXCHG8Instruction = 1 << 8,
795 X86_OnboardAPIC = 1 << 9,
796 X86_SYSENTER_SYSEXIT = 1 << 11,
797
798 X86_MemoryTypeRangeRegisters = 1 << 12,
799 X86_PageGlobalEnable = 1 << 13,
800 X86_MachineCheckArchitecture = 1 << 14,
801 X86_CMOVInstruction = 1 << 15,
802
803 X86_PageAttributeTable = 1 << 16,
804 X86_36BitPSEs = 1 << 17,
805 X86_ProcessorSerialNumber = 1 << 18,
806 X86_CLFLUSHInstruction = 1 << 19,
807
808 X86_DebugTraceStore = 1 << 21,
809 X86_ACPIViaMSR = 1 << 22,
810 X86_MultimediaExtensions = 1 << 23,
811
812 X86_FXSAVE_FXRSTOR = 1 << 24,
813 X86_StreamingSIMDExtensions = 1 << 25,
814 X86_StreamingSIMDExtensions2 = 1 << 26,
815 X86_CPUSelfSnoop = 1 << 27,
816
817 X86_HyperThreading = 1 << 28,
818 X86_AutomaticClockControl = 1 << 29,
819 X86_IA64Processor = 1 << 30
820 };
821
822 // Setup the auxiliary vectors. These will already have endian
823 // conversion. Auxiliary vectors are loaded only for elf formatted
824 // executables; the auxv is responsible for passing information from
825 // the OS to the interpreter.
826 ElfObject * elfObject = dynamic_cast<ElfObject *>(objFile);
827 if (elfObject) {
828 uint64_t features =
829 X86_OnboardFPU |
830 X86_VirtualModeExtensions |
831 X86_DebuggingExtensions |
832 X86_PageSizeExtensions |
833 X86_TimeStampCounter |
834 X86_ModelSpecificRegisters |
835 X86_PhysicalAddressExtensions |
836 X86_MachineCheckExtensions |
837 X86_CMPXCHG8Instruction |
838 X86_OnboardAPIC |
839 X86_SYSENTER_SYSEXIT |
840 X86_MemoryTypeRangeRegisters |
841 X86_PageGlobalEnable |
842 X86_MachineCheckArchitecture |
843 X86_CMOVInstruction |
844 X86_PageAttributeTable |
845 X86_36BitPSEs |
846// X86_ProcessorSerialNumber |
847 X86_CLFLUSHInstruction |
848// X86_DebugTraceStore |
849// X86_ACPIViaMSR |
850 X86_MultimediaExtensions |
851 X86_FXSAVE_FXRSTOR |
852 X86_StreamingSIMDExtensions |
853 X86_StreamingSIMDExtensions2 |
854// X86_CPUSelfSnoop |
855// X86_HyperThreading |
856// X86_AutomaticClockControl |
857// X86_IA64Processor |
858 0;
859
860 //Bits which describe the system hardware capabilities
861 //XXX Figure out what these should be
862 auxv.push_back(auxv_t(M5_AT_HWCAP, features));
863 //The system page size
864 auxv.push_back(auxv_t(M5_AT_PAGESZ, X86ISA::PageBytes));
865 //Frequency at which times() increments
866 //Defined to be 100 in the kernel source.
867 auxv.push_back(auxv_t(M5_AT_CLKTCK, 100));
868 // This is the virtual address of the program header tables if they
869 // appear in the executable image.
870 auxv.push_back(auxv_t(M5_AT_PHDR, elfObject->programHeaderTable()));
871 // This is the size of a program header entry from the elf file.
872 auxv.push_back(auxv_t(M5_AT_PHENT, elfObject->programHeaderSize()));
873 // This is the number of program headers from the original elf file.
874 auxv.push_back(auxv_t(M5_AT_PHNUM, elfObject->programHeaderCount()));
875 // This is the base address of the ELF interpreter; it should be
876 // zero for static executables or contain the base address for
877 // dynamic executables.
878 auxv.push_back(auxv_t(M5_AT_BASE, getBias()));
879 //XXX Figure out what this should be.
880 auxv.push_back(auxv_t(M5_AT_FLAGS, 0));
881 //The entry point to the program
882 auxv.push_back(auxv_t(M5_AT_ENTRY, objFile->entryPoint()));
883 //Different user and group IDs
884 auxv.push_back(auxv_t(M5_AT_UID, uid()));
885 auxv.push_back(auxv_t(M5_AT_EUID, euid()));
886 auxv.push_back(auxv_t(M5_AT_GID, gid()));
887 auxv.push_back(auxv_t(M5_AT_EGID, egid()));
888 //Whether to enable "secure mode" in the executable
889 auxv.push_back(auxv_t(M5_AT_SECURE, 0));
890 //The address of 16 "random" bytes.
891 auxv.push_back(auxv_t(M5_AT_RANDOM, 0));
892 //The name of the program
893 auxv.push_back(auxv_t(M5_AT_EXECFN, 0));
894 //The platform string
895 auxv.push_back(auxv_t(M5_AT_PLATFORM, 0));
896 }
897
898 //Figure out how big the initial stack needs to be
899
900 // A sentry NULL void pointer at the top of the stack.
901 int sentry_size = intSize;
902
903 //This is the name of the file which is present on the initial stack
904 //It's purpose is to let the user space linker examine the original file.
905 int file_name_size = filename.size() + 1;
906
907 const int numRandomBytes = 16;
908 int aux_data_size = numRandomBytes;
909
910 string platform = "x86_64";
911 aux_data_size += platform.size() + 1;
912
913 int env_data_size = 0;
914 for (int i = 0; i < envp.size(); ++i)
915 env_data_size += envp[i].size() + 1;
916 int arg_data_size = 0;
917 for (int i = 0; i < argv.size(); ++i)
918 arg_data_size += argv[i].size() + 1;
919
920 //The info_block needs to be padded so it's size is a multiple of the
921 //alignment mask. Also, it appears that there needs to be at least some
922 //padding, so if the size is already a multiple, we need to increase it
923 //anyway.
924 int base_info_block_size =
925 sentry_size + file_name_size + env_data_size + arg_data_size;
926
927 int info_block_size = roundUp(base_info_block_size, align);
928
929 int info_block_padding = info_block_size - base_info_block_size;
930
931 //Each auxilliary vector is two 8 byte words
932 int aux_array_size = intSize * 2 * (auxv.size() + 1);
933
934 int envp_array_size = intSize * (envp.size() + 1);
935 int argv_array_size = intSize * (argv.size() + 1);
936
937 int argc_size = intSize;
938
939 //Figure out the size of the contents of the actual initial frame
940 int frame_size =
941 aux_array_size +
942 envp_array_size +
943 argv_array_size +
944 argc_size;
945
946 //There needs to be padding after the auxiliary vector data so that the
947 //very bottom of the stack is aligned properly.
948 int partial_size = frame_size + aux_data_size;
949 int aligned_partial_size = roundUp(partial_size, align);
950 int aux_padding = aligned_partial_size - partial_size;
951
952 int space_needed =
953 info_block_size +
954 aux_data_size +
955 aux_padding +
956 frame_size;
957
958 memState->stackMin = memState->stackBase - space_needed;
959 memState->stackMin = roundDown(memState->stackMin, align);
960 memState->stackSize = roundUp(memState->stackBase - memState->stackMin,
961 pageSize);
962
963 // map memory
964 Addr stack_end = roundDown(memState->stackBase - memState->stackSize,
965 pageSize);
966
967 DPRINTF(Stack, "Mapping the stack: 0x%x %dB\n",
968 stack_end, memState->stackSize);
969 allocateMem(stack_end, memState->stackSize);
970
971 // map out initial stack contents
972 IntType sentry_base = memState->stackBase - sentry_size;
973 IntType file_name_base = sentry_base - file_name_size;
974 IntType env_data_base = file_name_base - env_data_size;
975 IntType arg_data_base = env_data_base - arg_data_size;
976 IntType aux_data_base = arg_data_base - info_block_padding - aux_data_size;
977 IntType auxv_array_base = aux_data_base - aux_array_size - aux_padding;
978 IntType envp_array_base = auxv_array_base - envp_array_size;
979 IntType argv_array_base = envp_array_base - argv_array_size;
980 IntType argc_base = argv_array_base - argc_size;
981
982 DPRINTF(Stack, "The addresses of items on the initial stack:\n");
983 DPRINTF(Stack, "0x%x - file name\n", file_name_base);
984 DPRINTF(Stack, "0x%x - env data\n", env_data_base);
985 DPRINTF(Stack, "0x%x - arg data\n", arg_data_base);
986 DPRINTF(Stack, "0x%x - aux data\n", aux_data_base);
987 DPRINTF(Stack, "0x%x - auxv array\n", auxv_array_base);
988 DPRINTF(Stack, "0x%x - envp array\n", envp_array_base);
989 DPRINTF(Stack, "0x%x - argv array\n", argv_array_base);
990 DPRINTF(Stack, "0x%x - argc \n", argc_base);
991 DPRINTF(Stack, "0x%x - stack min\n", memState->stackMin);
992
993 // write contents to stack
994
995 // figure out argc
996 IntType argc = argv.size();
997 IntType guestArgc = X86ISA::htog(argc);
998
999 //Write out the sentry void *
1000 IntType sentry_NULL = 0;
1001 initVirtMem.writeBlob(sentry_base,
1002 (uint8_t*)&sentry_NULL, sentry_size);
1003
1004 //Write the file name
1005 initVirtMem.writeString(file_name_base, filename.c_str());
1006
1007 //Fix up the aux vectors which point to data
1008 assert(auxv[auxv.size() - 3].a_type == M5_AT_RANDOM);
1009 auxv[auxv.size() - 3].a_val = aux_data_base;
1010 assert(auxv[auxv.size() - 2].a_type == M5_AT_EXECFN);
1011 auxv[auxv.size() - 2].a_val = argv_array_base;
1012 assert(auxv[auxv.size() - 1].a_type == M5_AT_PLATFORM);
1013 auxv[auxv.size() - 1].a_val = aux_data_base + numRandomBytes;
1014
1015 //Copy the aux stuff
1016 for (int x = 0; x < auxv.size(); x++) {
1017 initVirtMem.writeBlob(auxv_array_base + x * 2 * intSize,
1018 (uint8_t*)&(auxv[x].a_type), intSize);
1019 initVirtMem.writeBlob(auxv_array_base + (x * 2 + 1) * intSize,
1020 (uint8_t*)&(auxv[x].a_val), intSize);
1021 }
1022 //Write out the terminating zeroed auxilliary vector
1023 const uint64_t zero = 0;
1024 initVirtMem.writeBlob(auxv_array_base + auxv.size() * 2 * intSize,
1025 (uint8_t*)&zero, intSize);
1026 initVirtMem.writeBlob(auxv_array_base + (auxv.size() * 2 + 1) * intSize,
1027 (uint8_t*)&zero, intSize);
1028
1029 initVirtMem.writeString(aux_data_base, platform.c_str());
1030
1031 copyStringArray(envp, envp_array_base, env_data_base, initVirtMem);
1032 copyStringArray(argv, argv_array_base, arg_data_base, initVirtMem);
1033
1034 initVirtMem.writeBlob(argc_base, (uint8_t*)&guestArgc, intSize);
1035
1036 ThreadContext *tc = system->getThreadContext(contextIds[0]);
1037 //Set the stack pointer register
1038 tc->setIntReg(StackPointerReg, memState->stackMin);
1039
1040 // There doesn't need to be any segment base added in since we're dealing
1041 // with the flat segmentation model.
1042 tc->pcState(getStartPC());
1043
1044 //Align the "stack_min" to a page boundary.
1045 memState->stackMin = roundDown(memState->stackMin, pageSize);
1046}
1047
1048void
1049X86_64Process::argsInit(int pageSize)
1050{
1051 std::vector<AuxVector<uint64_t> > extraAuxvs;
1052 extraAuxvs.push_back(AuxVector<uint64_t>(M5_AT_SYSINFO_EHDR,
1053 vsyscallPage.base));
1054 X86Process::argsInit<uint64_t>(pageSize, extraAuxvs);
1055}
1056
1057void
1058I386Process::argsInit(int pageSize)
1059{
1060 std::vector<AuxVector<uint32_t> > extraAuxvs;
1061 //Tell the binary where the vsyscall part of the vsyscall page is.
1062 extraAuxvs.push_back(AuxVector<uint32_t>(M5_AT_SYSINFO,
1063 vsyscallPage.base + vsyscallPage.vsyscallOffset));
1064 extraAuxvs.push_back(AuxVector<uint32_t>(M5_AT_SYSINFO_EHDR,
1065 vsyscallPage.base));
1066 X86Process::argsInit<uint32_t>(pageSize, extraAuxvs);
1067}
1068
1069void
1070X86Process::setSyscallReturn(ThreadContext *tc, SyscallReturn retval)
1071{
1072 tc->setIntReg(INTREG_RAX, retval.encodedValue());
1073}
1074
1075X86ISA::IntReg
1076X86_64Process::getSyscallArg(ThreadContext *tc, int &i)
1077{
1078 assert(i < NumArgumentRegs);
1079 return tc->readIntReg(ArgumentReg[i++]);
1080}
1081
1082void
1083X86_64Process::setSyscallArg(ThreadContext *tc, int i, X86ISA::IntReg val)
1084{
1085 assert(i < NumArgumentRegs);
1086 return tc->setIntReg(ArgumentReg[i], val);
1087}
1088
1089void
1090X86_64Process::clone(ThreadContext *old_tc, ThreadContext *new_tc,
1091 Process *p, TheISA::IntReg flags)
1092{
1093 X86Process::clone(old_tc, new_tc, p, flags);
1094 ((X86_64Process*)p)->vsyscallPage = vsyscallPage;
1095}
1096
1097X86ISA::IntReg
1098I386Process::getSyscallArg(ThreadContext *tc, int &i)
1099{
1100 assert(i < NumArgumentRegs32);
1101 return tc->readIntReg(ArgumentReg32[i++]);
1102}
1103
1104X86ISA::IntReg
1105I386Process::getSyscallArg(ThreadContext *tc, int &i, int width)
1106{
1107 assert(width == 32 || width == 64);
1108 assert(i < NumArgumentRegs);
1109 uint64_t retVal = tc->readIntReg(ArgumentReg32[i++]) & mask(32);
1110 if (width == 64)
1111 retVal |= ((uint64_t)tc->readIntReg(ArgumentReg[i++]) << 32);
1112 return retVal;
1113}
1114
1115void
1116I386Process::setSyscallArg(ThreadContext *tc, int i, X86ISA::IntReg val)
1117{
1118 assert(i < NumArgumentRegs);
1119 return tc->setIntReg(ArgumentReg[i], val);
1120}
1121
1122void
1123I386Process::clone(ThreadContext *old_tc, ThreadContext *new_tc,
1124 Process *p, TheISA::IntReg flags)
1125{
1126 X86Process::clone(old_tc, new_tc, p, flags);
1127 ((I386Process*)p)->vsyscallPage = vsyscallPage;
1128}