pagetable_walker.cc (5881:73c0aaaaf186) | pagetable_walker.cc (5895:569e3b31a868) |
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1/* 2 * Copyright (c) 2007 The Hewlett-Packard Development Company 3 * All rights reserved. 4 * 5 * Redistribution and use of this software in source and binary forms, 6 * with or without modification, are permitted provided that the 7 * following conditions are met: 8 * --- 70 unchanged lines hidden (view full) --- 79 Bitfield<5> a; 80 Bitfield<4> pcd; 81 Bitfield<3> pwt; 82 Bitfield<2> u; 83 Bitfield<1> w; 84 Bitfield<0> p; 85EndBitUnion(PageTableEntry) 86 | 1/* 2 * Copyright (c) 2007 The Hewlett-Packard Development Company 3 * All rights reserved. 4 * 5 * Redistribution and use of this software in source and binary forms, 6 * with or without modification, are permitted provided that the 7 * following conditions are met: 8 * --- 70 unchanged lines hidden (view full) --- 79 Bitfield<5> a; 80 Bitfield<4> pcd; 81 Bitfield<3> pwt; 82 Bitfield<2> u; 83 Bitfield<1> w; 84 Bitfield<0> p; 85EndBitUnion(PageTableEntry) 86 |
87void | 87Fault |
88Walker::doNext(PacketPtr &read, PacketPtr &write) 89{ 90 assert(state != Ready && state != Waiting); 91 write = NULL; 92 PageTableEntry pte; 93 if (size == 8) 94 pte = read->get<uint64_t>(); 95 else --- 5 unchanged lines hidden (view full) --- 101 bool badNX = pte.nx && (!tlb->allowNX() || !enableNX); 102 switch(state) { 103 case LongPML4: 104 nextRead = ((uint64_t)pte & (mask(40) << 12)) + vaddr.longl3 * size; 105 doWrite = !pte.a; 106 pte.a = 1; 107 entry.writable = pte.w; 108 entry.user = pte.u; | 88Walker::doNext(PacketPtr &read, PacketPtr &write) 89{ 90 assert(state != Ready && state != Waiting); 91 write = NULL; 92 PageTableEntry pte; 93 if (size == 8) 94 pte = read->get<uint64_t>(); 95 else --- 5 unchanged lines hidden (view full) --- 101 bool badNX = pte.nx && (!tlb->allowNX() || !enableNX); 102 switch(state) { 103 case LongPML4: 104 nextRead = ((uint64_t)pte & (mask(40) << 12)) + vaddr.longl3 * size; 105 doWrite = !pte.a; 106 pte.a = 1; 107 entry.writable = pte.w; 108 entry.user = pte.u; |
109 if (badNX) 110 panic("NX violation!\n"); | 109 if (badNX || !pte.p) { 110 stop(); 111 return pageFault(pte.p); 112 } |
111 entry.noExec = pte.nx; | 113 entry.noExec = pte.nx; |
112 if (!pte.p) 113 panic("Page at %#x not present!\n", entry.vaddr); | |
114 nextState = LongPDP; 115 break; 116 case LongPDP: 117 nextRead = ((uint64_t)pte & (mask(40) << 12)) + vaddr.longl2 * size; 118 doWrite = !pte.a; 119 pte.a = 1; 120 entry.writable = entry.writable && pte.w; 121 entry.user = entry.user && pte.u; | 114 nextState = LongPDP; 115 break; 116 case LongPDP: 117 nextRead = ((uint64_t)pte & (mask(40) << 12)) + vaddr.longl2 * size; 118 doWrite = !pte.a; 119 pte.a = 1; 120 entry.writable = entry.writable && pte.w; 121 entry.user = entry.user && pte.u; |
122 if (badNX) 123 panic("NX violation!\n"); 124 if (!pte.p) 125 panic("Page at %#x not present!\n", entry.vaddr); | 122 if (badNX || !pte.p) { 123 stop(); 124 return pageFault(pte.p); 125 } |
126 nextState = LongPD; 127 break; 128 case LongPD: 129 doWrite = !pte.a; 130 pte.a = 1; 131 entry.writable = entry.writable && pte.w; 132 entry.user = entry.user && pte.u; | 126 nextState = LongPD; 127 break; 128 case LongPD: 129 doWrite = !pte.a; 130 pte.a = 1; 131 entry.writable = entry.writable && pte.w; 132 entry.user = entry.user && pte.u; |
133 if (badNX) 134 panic("NX violation!\n"); 135 if (!pte.p) 136 panic("Page at %#x not present!\n", entry.vaddr); | 133 if (badNX || !pte.p) { 134 stop(); 135 return pageFault(pte.p); 136 } |
137 if (!pte.ps) { 138 // 4 KB page 139 entry.size = 4 * (1 << 10); 140 nextRead = 141 ((uint64_t)pte & (mask(40) << 12)) + vaddr.longl1 * size; 142 nextState = LongPTE; 143 break; 144 } else { 145 // 2 MB page 146 entry.size = 2 * (1 << 20); 147 entry.paddr = (uint64_t)pte & (mask(31) << 21); 148 entry.uncacheable = uncacheable; 149 entry.global = pte.g; 150 entry.patBit = bits(pte, 12); 151 entry.vaddr = entry.vaddr & ~((2 * (1 << 20)) - 1); 152 tlb->insert(entry.vaddr, entry); | 137 if (!pte.ps) { 138 // 4 KB page 139 entry.size = 4 * (1 << 10); 140 nextRead = 141 ((uint64_t)pte & (mask(40) << 12)) + vaddr.longl1 * size; 142 nextState = LongPTE; 143 break; 144 } else { 145 // 2 MB page 146 entry.size = 2 * (1 << 20); 147 entry.paddr = (uint64_t)pte & (mask(31) << 21); 148 entry.uncacheable = uncacheable; 149 entry.global = pte.g; 150 entry.patBit = bits(pte, 12); 151 entry.vaddr = entry.vaddr & ~((2 * (1 << 20)) - 1); 152 tlb->insert(entry.vaddr, entry); |
153 nextState = Ready; 154 delete read->req; 155 delete read; 156 read = NULL; 157 return; | 153 stop(); 154 return NoFault; |
158 } 159 case LongPTE: 160 doWrite = !pte.a; 161 pte.a = 1; 162 entry.writable = entry.writable && pte.w; 163 entry.user = entry.user && pte.u; | 155 } 156 case LongPTE: 157 doWrite = !pte.a; 158 pte.a = 1; 159 entry.writable = entry.writable && pte.w; 160 entry.user = entry.user && pte.u; |
164 if (badNX) 165 panic("NX violation!\n"); 166 if (!pte.p) 167 panic("Page at %#x not present!\n", entry.vaddr); | 161 if (badNX || !pte.p) { 162 stop(); 163 return pageFault(pte.p); 164 } |
168 entry.paddr = (uint64_t)pte & (mask(40) << 12); 169 entry.uncacheable = uncacheable; 170 entry.global = pte.g; 171 entry.patBit = bits(pte, 12); 172 entry.vaddr = entry.vaddr & ~((4 * (1 << 10)) - 1); 173 tlb->insert(entry.vaddr, entry); | 165 entry.paddr = (uint64_t)pte & (mask(40) << 12); 166 entry.uncacheable = uncacheable; 167 entry.global = pte.g; 168 entry.patBit = bits(pte, 12); 169 entry.vaddr = entry.vaddr & ~((4 * (1 << 10)) - 1); 170 tlb->insert(entry.vaddr, entry); |
174 nextState = Ready; 175 delete read->req; 176 delete read; 177 read = NULL; 178 return; | 171 stop(); 172 return NoFault; |
179 case PAEPDP: 180 nextRead = ((uint64_t)pte & (mask(40) << 12)) + vaddr.pael2 * size; | 173 case PAEPDP: 174 nextRead = ((uint64_t)pte & (mask(40) << 12)) + vaddr.pael2 * size; |
181 if (!pte.p) 182 panic("Page at %#x not present!\n", entry.vaddr); | 175 if (!pte.p) { 176 stop(); 177 return pageFault(pte.p); 178 } |
183 nextState = PAEPD; 184 break; 185 case PAEPD: 186 doWrite = !pte.a; 187 pte.a = 1; 188 entry.writable = pte.w; 189 entry.user = pte.u; | 179 nextState = PAEPD; 180 break; 181 case PAEPD: 182 doWrite = !pte.a; 183 pte.a = 1; 184 entry.writable = pte.w; 185 entry.user = pte.u; |
190 if (badNX) 191 panic("NX violation!\n"); 192 if (!pte.p) 193 panic("Page at %#x not present!\n", entry.vaddr); | 186 if (badNX || !pte.p) { 187 stop(); 188 return pageFault(pte.p); 189 } |
194 if (!pte.ps) { 195 // 4 KB page 196 entry.size = 4 * (1 << 10); 197 nextRead = ((uint64_t)pte & (mask(40) << 12)) + vaddr.pael1 * size; 198 nextState = PAEPTE; 199 break; 200 } else { 201 // 2 MB page 202 entry.size = 2 * (1 << 20); 203 entry.paddr = (uint64_t)pte & (mask(31) << 21); 204 entry.uncacheable = uncacheable; 205 entry.global = pte.g; 206 entry.patBit = bits(pte, 12); 207 entry.vaddr = entry.vaddr & ~((2 * (1 << 20)) - 1); 208 tlb->insert(entry.vaddr, entry); | 190 if (!pte.ps) { 191 // 4 KB page 192 entry.size = 4 * (1 << 10); 193 nextRead = ((uint64_t)pte & (mask(40) << 12)) + vaddr.pael1 * size; 194 nextState = PAEPTE; 195 break; 196 } else { 197 // 2 MB page 198 entry.size = 2 * (1 << 20); 199 entry.paddr = (uint64_t)pte & (mask(31) << 21); 200 entry.uncacheable = uncacheable; 201 entry.global = pte.g; 202 entry.patBit = bits(pte, 12); 203 entry.vaddr = entry.vaddr & ~((2 * (1 << 20)) - 1); 204 tlb->insert(entry.vaddr, entry); |
209 nextState = Ready; 210 delete read->req; 211 delete read; 212 read = NULL; 213 return; | 205 stop(); 206 return NoFault; |
214 } 215 case PAEPTE: 216 doWrite = !pte.a; 217 pte.a = 1; 218 entry.writable = entry.writable && pte.w; 219 entry.user = entry.user && pte.u; | 207 } 208 case PAEPTE: 209 doWrite = !pte.a; 210 pte.a = 1; 211 entry.writable = entry.writable && pte.w; 212 entry.user = entry.user && pte.u; |
220 if (badNX) 221 panic("NX violation!\n"); 222 if (!pte.p) 223 panic("Page at %#x not present!\n", entry.vaddr); | 213 if (badNX || !pte.p) { 214 stop(); 215 return pageFault(pte.p); 216 } |
224 entry.paddr = (uint64_t)pte & (mask(40) << 12); 225 entry.uncacheable = uncacheable; 226 entry.global = pte.g; 227 entry.patBit = bits(pte, 7); 228 entry.vaddr = entry.vaddr & ~((4 * (1 << 10)) - 1); 229 tlb->insert(entry.vaddr, entry); | 217 entry.paddr = (uint64_t)pte & (mask(40) << 12); 218 entry.uncacheable = uncacheable; 219 entry.global = pte.g; 220 entry.patBit = bits(pte, 7); 221 entry.vaddr = entry.vaddr & ~((4 * (1 << 10)) - 1); 222 tlb->insert(entry.vaddr, entry); |
230 nextState = Ready; 231 delete read->req; 232 delete read; 233 read = NULL; 234 return; | 223 stop(); 224 return NoFault; |
235 case PSEPD: 236 doWrite = !pte.a; 237 pte.a = 1; 238 entry.writable = pte.w; 239 entry.user = pte.u; | 225 case PSEPD: 226 doWrite = !pte.a; 227 pte.a = 1; 228 entry.writable = pte.w; 229 entry.user = pte.u; |
240 if (!pte.p) 241 panic("Page at %#x not present!\n", entry.vaddr); | 230 if (!pte.p) { 231 stop(); 232 return pageFault(pte.p); 233 } |
242 if (!pte.ps) { 243 // 4 KB page 244 entry.size = 4 * (1 << 10); 245 nextRead = 246 ((uint64_t)pte & (mask(20) << 12)) + vaddr.norml2 * size; 247 nextState = PTE; 248 break; 249 } else { 250 // 4 MB page 251 entry.size = 4 * (1 << 20); 252 entry.paddr = bits(pte, 20, 13) << 32 | bits(pte, 31, 22) << 22; 253 entry.uncacheable = uncacheable; 254 entry.global = pte.g; 255 entry.patBit = bits(pte, 12); 256 entry.vaddr = entry.vaddr & ~((4 * (1 << 20)) - 1); 257 tlb->insert(entry.vaddr, entry); | 234 if (!pte.ps) { 235 // 4 KB page 236 entry.size = 4 * (1 << 10); 237 nextRead = 238 ((uint64_t)pte & (mask(20) << 12)) + vaddr.norml2 * size; 239 nextState = PTE; 240 break; 241 } else { 242 // 4 MB page 243 entry.size = 4 * (1 << 20); 244 entry.paddr = bits(pte, 20, 13) << 32 | bits(pte, 31, 22) << 22; 245 entry.uncacheable = uncacheable; 246 entry.global = pte.g; 247 entry.patBit = bits(pte, 12); 248 entry.vaddr = entry.vaddr & ~((4 * (1 << 20)) - 1); 249 tlb->insert(entry.vaddr, entry); |
258 nextState = Ready; 259 delete read->req; 260 delete read; 261 read = NULL; 262 return; | 250 stop(); 251 return NoFault; |
263 } 264 case PD: 265 doWrite = !pte.a; 266 pte.a = 1; 267 entry.writable = pte.w; 268 entry.user = pte.u; | 252 } 253 case PD: 254 doWrite = !pte.a; 255 pte.a = 1; 256 entry.writable = pte.w; 257 entry.user = pte.u; |
269 if (!pte.p) 270 panic("Page at %#x not present!\n", entry.vaddr); | 258 if (!pte.p) { 259 stop(); 260 return pageFault(pte.p); 261 } |
271 // 4 KB page 272 entry.size = 4 * (1 << 10); 273 nextRead = ((uint64_t)pte & (mask(20) << 12)) + vaddr.norml2 * size; 274 nextState = PTE; 275 break; | 262 // 4 KB page 263 entry.size = 4 * (1 << 10); 264 nextRead = ((uint64_t)pte & (mask(20) << 12)) + vaddr.norml2 * size; 265 nextState = PTE; 266 break; |
276 nextState = PTE; 277 break; | |
278 case PTE: 279 doWrite = !pte.a; 280 pte.a = 1; 281 entry.writable = pte.w; 282 entry.user = pte.u; | 267 case PTE: 268 doWrite = !pte.a; 269 pte.a = 1; 270 entry.writable = pte.w; 271 entry.user = pte.u; |
283 if (!pte.p) 284 panic("Page at %#x not present!\n", entry.vaddr); | 272 if (!pte.p) { 273 stop(); 274 return pageFault(pte.p); 275 } |
285 entry.paddr = (uint64_t)pte & (mask(20) << 12); 286 entry.uncacheable = uncacheable; 287 entry.global = pte.g; 288 entry.patBit = bits(pte, 7); 289 entry.vaddr = entry.vaddr & ~((4 * (1 << 10)) - 1); 290 tlb->insert(entry.vaddr, entry); | 276 entry.paddr = (uint64_t)pte & (mask(20) << 12); 277 entry.uncacheable = uncacheable; 278 entry.global = pte.g; 279 entry.patBit = bits(pte, 7); 280 entry.vaddr = entry.vaddr & ~((4 * (1 << 10)) - 1); 281 tlb->insert(entry.vaddr, entry); |
291 nextState = Ready; 292 delete read->req; 293 delete read; 294 read = NULL; 295 return; | 282 stop(); 283 return NoFault; |
296 default: 297 panic("Unknown page table walker state %d!\n"); 298 } 299 PacketPtr oldRead = read; 300 //If we didn't return, we're setting up another read. 301 Request::Flags flags = oldRead->req->getFlags(); 302 flags.set(Request::UNCACHEABLE, uncacheable); 303 RequestPtr request = --- 7 unchanged lines hidden (view full) --- 311 write->set<uint64_t>(pte); 312 write->cmd = MemCmd::WriteReq; 313 write->setDest(Packet::Broadcast); 314 } else { 315 write = NULL; 316 delete oldRead->req; 317 delete oldRead; 318 } | 284 default: 285 panic("Unknown page table walker state %d!\n"); 286 } 287 PacketPtr oldRead = read; 288 //If we didn't return, we're setting up another read. 289 Request::Flags flags = oldRead->req->getFlags(); 290 flags.set(Request::UNCACHEABLE, uncacheable); 291 RequestPtr request = --- 7 unchanged lines hidden (view full) --- 299 write->set<uint64_t>(pte); 300 write->cmd = MemCmd::WriteReq; 301 write->setDest(Packet::Broadcast); 302 } else { 303 write = NULL; 304 delete oldRead->req; 305 delete oldRead; 306 } |
307 return NoFault; |
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319} 320 | 308} 309 |
321void 322Walker::start(ThreadContext * _tc, Addr vaddr, bool _write, bool _execute) | 310Fault 311Walker::start(ThreadContext * _tc, BaseTLB::Translation *_translation, 312 RequestPtr _req, bool _write, bool _execute) |
323{ 324 assert(state == Ready); 325 assert(!tc); 326 tc = _tc; | 313{ 314 assert(state == Ready); 315 assert(!tc); 316 tc = _tc; |
317 req = _req; 318 Addr vaddr = req->getVaddr(); |
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327 execute = _execute; 328 write = _write; | 319 execute = _execute; 320 write = _write; |
321 translation = _translation; |
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329 330 VAddr addr = vaddr; 331 332 //Figure out what we're doing. 333 CR3 cr3 = tc->readMiscRegNoEffect(MISCREG_CR3); 334 Addr top = 0; 335 // Check if we're in long mode or not 336 Efer efer = tc->readMiscRegNoEffect(MISCREG_EFER); 337 size = 8; 338 if (efer.lma) { 339 // Do long mode. 340 state = LongPML4; 341 top = (cr3.longPdtb << 12) + addr.longl4 * size; | 322 323 VAddr addr = vaddr; 324 325 //Figure out what we're doing. 326 CR3 cr3 = tc->readMiscRegNoEffect(MISCREG_CR3); 327 Addr top = 0; 328 // Check if we're in long mode or not 329 Efer efer = tc->readMiscRegNoEffect(MISCREG_EFER); 330 size = 8; 331 if (efer.lma) { 332 // Do long mode. 333 state = LongPML4; 334 top = (cr3.longPdtb << 12) + addr.longl4 * size; |
335 enableNX = efer.nxe; |
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342 } else { 343 // We're in some flavor of legacy mode. 344 CR4 cr4 = tc->readMiscRegNoEffect(MISCREG_CR4); 345 if (cr4.pae) { 346 // Do legacy PAE. 347 state = PAEPDP; 348 top = (cr3.paePdtb << 5) + addr.pael3 * size; | 336 } else { 337 // We're in some flavor of legacy mode. 338 CR4 cr4 = tc->readMiscRegNoEffect(MISCREG_CR4); 339 if (cr4.pae) { 340 // Do legacy PAE. 341 state = PAEPDP; 342 top = (cr3.paePdtb << 5) + addr.pael3 * size; |
343 enableNX = efer.nxe; |
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349 } else { 350 size = 4; 351 top = (cr3.pdtb << 12) + addr.norml2 * size; 352 if (cr4.pse) { 353 // Do legacy PSE. 354 state = PSEPD; 355 } else { 356 // Do legacy non PSE. 357 state = PD; 358 } | 344 } else { 345 size = 4; 346 top = (cr3.pdtb << 12) + addr.norml2 * size; 347 if (cr4.pse) { 348 // Do legacy PSE. 349 state = PSEPD; 350 } else { 351 // Do legacy non PSE. 352 state = PD; 353 } |
354 enableNX = false; |
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359 } 360 } 361 362 nextState = Ready; 363 entry.vaddr = vaddr; 364 | 355 } 356 } 357 358 nextState = Ready; 359 entry.vaddr = vaddr; 360 |
365 enableNX = efer.nxe; 366 | |
367 Request::Flags flags = Request::PHYSICAL; 368 if (cr3.pcd) 369 flags.set(Request::UNCACHEABLE); 370 RequestPtr request = new Request(top, size, flags); 371 read = new Packet(request, MemCmd::ReadExReq, Packet::Broadcast); 372 read->allocate(); 373 Enums::MemoryMode memMode = sys->getMemoryMode(); 374 if (memMode == Enums::timing) { | 361 Request::Flags flags = Request::PHYSICAL; 362 if (cr3.pcd) 363 flags.set(Request::UNCACHEABLE); 364 RequestPtr request = new Request(top, size, flags); 365 read = new Packet(request, MemCmd::ReadExReq, Packet::Broadcast); 366 read->allocate(); 367 Enums::MemoryMode memMode = sys->getMemoryMode(); 368 if (memMode == Enums::timing) { |
375 tc->suspend(); | 369 timingFault = NoFault; |
376 port.sendTiming(read); 377 } else if (memMode == Enums::atomic) { | 370 port.sendTiming(read); 371 } else if (memMode == Enums::atomic) { |
372 Fault fault; |
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378 do { 379 port.sendAtomic(read); 380 PacketPtr write = NULL; | 373 do { 374 port.sendAtomic(read); 375 PacketPtr write = NULL; |
381 doNext(read, write); | 376 fault = doNext(read, write); 377 assert(fault == NoFault || read == NULL); |
382 state = nextState; 383 nextState = Ready; 384 if (write) 385 port.sendAtomic(write); 386 } while(read); 387 tc = NULL; 388 state = Ready; 389 nextState = Waiting; | 378 state = nextState; 379 nextState = Ready; 380 if (write) 381 port.sendAtomic(write); 382 } while(read); 383 tc = NULL; 384 state = Ready; 385 nextState = Waiting; |
386 return fault; |
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390 } else { 391 panic("Unrecognized memory system mode.\n"); 392 } | 387 } else { 388 panic("Unrecognized memory system mode.\n"); 389 } |
390 return NoFault; |
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393} 394 395bool 396Walker::WalkerPort::recvTiming(PacketPtr pkt) 397{ 398 return walker->recvTiming(pkt); 399} 400 --- 4 unchanged lines hidden (view full) --- 405 if (pkt->isResponse() && !pkt->wasNacked()) { 406 if (pkt->isRead()) { 407 assert(inflight); 408 assert(state == Waiting); 409 assert(!read); 410 state = nextState; 411 nextState = Ready; 412 PacketPtr write = NULL; | 391} 392 393bool 394Walker::WalkerPort::recvTiming(PacketPtr pkt) 395{ 396 return walker->recvTiming(pkt); 397} 398 --- 4 unchanged lines hidden (view full) --- 403 if (pkt->isResponse() && !pkt->wasNacked()) { 404 if (pkt->isRead()) { 405 assert(inflight); 406 assert(state == Waiting); 407 assert(!read); 408 state = nextState; 409 nextState = Ready; 410 PacketPtr write = NULL; |
413 doNext(pkt, write); | 411 timingFault = doNext(pkt, write); |
414 state = Waiting; 415 read = pkt; | 412 state = Waiting; 413 read = pkt; |
414 assert(timingFault == NoFault || read == NULL); |
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416 if (write) { 417 writes.push_back(write); 418 } 419 sendPackets(); 420 } else { 421 sendPackets(); 422 } 423 if (inflight == 0 && read == NULL && writes.size() == 0) { | 415 if (write) { 416 writes.push_back(write); 417 } 418 sendPackets(); 419 } else { 420 sendPackets(); 421 } 422 if (inflight == 0 && read == NULL && writes.size() == 0) { |
424 tc->activate(0); | |
425 tc = NULL; 426 state = Ready; 427 nextState = Waiting; | 423 tc = NULL; 424 state = Ready; 425 nextState = Waiting; |
426 if (timingFault == NoFault) { 427 /* 428 * Finish the translation. Now that we now the right entry is 429 * in the TLB, this should work with no memory accesses. 430 * There could be new faults unrelated to the table walk like 431 * permissions violations, so we'll need the return value as 432 * well. 433 */ 434 bool delayedResponse; 435 Fault fault = tlb->translate(req, tc, NULL, write, execute, 436 delayedResponse, true); 437 assert(!delayedResponse); 438 // Let the CPU continue. 439 translation->finish(fault, req, tc, write); 440 } else { 441 // There was a fault during the walk. Let the CPU know. 442 translation->finish(timingFault, req, tc, write); 443 } |
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428 } 429 } else if (pkt->wasNacked()) { 430 pkt->reinitNacked(); 431 if (!port.sendTiming(pkt)) { 432 retrying = true; 433 if (pkt->isWrite()) { 434 writes.push_back(pkt); 435 } else { --- 84 unchanged lines hidden (view full) --- 520Walker::getPort(const std::string &if_name, int idx) 521{ 522 if (if_name == "port") 523 return &port; 524 else 525 panic("No page table walker port named %s!\n", if_name); 526} 527 | 444 } 445 } else if (pkt->wasNacked()) { 446 pkt->reinitNacked(); 447 if (!port.sendTiming(pkt)) { 448 retrying = true; 449 if (pkt->isWrite()) { 450 writes.push_back(pkt); 451 } else { --- 84 unchanged lines hidden (view full) --- 536Walker::getPort(const std::string &if_name, int idx) 537{ 538 if (if_name == "port") 539 return &port; 540 else 541 panic("No page table walker port named %s!\n", if_name); 542} 543 |
544Fault 545Walker::pageFault(bool present) 546{ 547 HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG); 548 return new PageFault(entry.vaddr, present, write, 549 m5reg.cpl == 3, false, execute && enableNX); |
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528} 529 | 550} 551 |
552} 553 |
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530X86ISA::Walker * 531X86PagetableWalkerParams::create() 532{ 533 return new X86ISA::Walker(this); 534} | 554X86ISA::Walker * 555X86PagetableWalkerParams::create() 556{ 557 return new X86ISA::Walker(this); 558} |