pagetable_walker.cc (12749:223c83ed9979) pagetable_walker.cc (13229:b45254f2733a)
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 265 unchanged lines hidden (view full) ---

274Fault
275Walker::WalkerState::stepWalk(PacketPtr &write)
276{
277 assert(state != Ready && state != Waiting);
278 Fault fault = NoFault;
279 write = NULL;
280 PageTableEntry pte;
281 if (dataSize == 8)
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 265 unchanged lines hidden (view full) ---

274Fault
275Walker::WalkerState::stepWalk(PacketPtr &write)
276{
277 assert(state != Ready && state != Waiting);
278 Fault fault = NoFault;
279 write = NULL;
280 PageTableEntry pte;
281 if (dataSize == 8)
282 pte = read->get();
282 pte = read->getLE<uint64_t>();
283 else
283 else
284 pte = read->get();
284 pte = read->getLE<uint32_t>();
285 VAddr vaddr = entry.vaddr;
286 bool uncacheable = pte.pcd;
287 Addr nextRead = 0;
288 bool doWrite = false;
289 bool doTLBInsert = false;
290 bool doEndWalk = false;
291 bool badNX = pte.nx && mode == BaseTLB::Execute && enableNX;
292 switch(state) {

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517 RequestPtr request = std::make_shared<Request>(
518 nextRead, oldRead->getSize(), flags, walker->masterId);
519 read = new Packet(request, MemCmd::ReadReq);
520 read->allocate();
521 // If we need to write, adjust the read packet to write the modified
522 // value back to memory.
523 if (doWrite) {
524 write = oldRead;
285 VAddr vaddr = entry.vaddr;
286 bool uncacheable = pte.pcd;
287 Addr nextRead = 0;
288 bool doWrite = false;
289 bool doTLBInsert = false;
290 bool doEndWalk = false;
291 bool badNX = pte.nx && mode == BaseTLB::Execute && enableNX;
292 switch(state) {

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517 RequestPtr request = std::make_shared<Request>(
518 nextRead, oldRead->getSize(), flags, walker->masterId);
519 read = new Packet(request, MemCmd::ReadReq);
520 read->allocate();
521 // If we need to write, adjust the read packet to write the modified
522 // value back to memory.
523 if (doWrite) {
524 write = oldRead;
525 write->set(pte);
525 write->setLE<uint64_t>(pte);
526 write->cmd = MemCmd::WriteReq;
527 } else {
528 write = NULL;
529 delete oldRead;
530 }
531 }
532 return fault;
533}

--- 190 unchanged lines hidden --- 		526 write->cmd = MemCmd::WriteReq;
527 } else {
528 write = NULL;
529 delete oldRead;
530 }
531 }
532 return fault;
533}

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