1/* 2 * Copyright (c) 2012 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 556 unchanged lines hidden (view full) --- 565 read = new Packet(request, MemCmd::ReadReq); 566 read->allocate(); 567} 568 569bool 570Walker::WalkerState::recvPacket(PacketPtr pkt) 571{ 572 assert(pkt->isResponse()); |
573 assert(inflight); 574 assert(state == Waiting); 575 assert(!read); 576 inflight--; 577 if (pkt->isRead()) { 578 state = nextState; 579 nextState = Ready; 580 PacketPtr write = NULL; 581 read = pkt; 582 timingFault = stepWalk(write); 583 state = Waiting; 584 assert(timingFault == NoFault || read == NULL); 585 if (write) { 586 writes.push_back(write); |
587 } |
588 sendPackets(); |
589 } else { |
590 sendPackets(); 591 } 592 if (inflight == 0 && read == NULL && writes.size() == 0) { 593 state = Ready; 594 nextState = Waiting; 595 if (timingFault == NoFault) { 596 /* 597 * Finish the translation. Now that we now the right entry is 598 * in the TLB, this should work with no memory accesses. 599 * There could be new faults unrelated to the table walk like 600 * permissions violations, so we'll need the return value as 601 * well. 602 */ 603 bool delayedResponse; 604 Fault fault = walker->tlb->translate(req, tc, NULL, mode, 605 delayedResponse, true); 606 assert(!delayedResponse); 607 // Let the CPU continue. 608 translation->finish(fault, req, tc, mode); 609 } else { 610 // There was a fault during the walk. Let the CPU know. 611 translation->finish(timingFault, req, tc, mode); |
612 } |
613 return true; |
614 } |
615 |
616 return false; 617} 618 619void 620Walker::WalkerState::sendPackets() 621{ 622 //If we're already waiting for the port to become available, just return. 623 if (retrying) --- 70 unchanged lines hidden --- |