1/*
| 1/*
|
| 2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
|
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 */
39
40#include "arch/x86/pagetable.hh"
41#include "arch/x86/pagetable_walker.hh"
42#include "arch/x86/tlb.hh"
43#include "arch/x86/vtophys.hh"
44#include "base/bitfield.hh"
45#include "cpu/base.hh"
46#include "cpu/thread_context.hh"
47#include "debug/PageTableWalker.hh"
48#include "mem/packet_access.hh"
49#include "mem/request.hh"
50#include "sim/system.hh"
51
52namespace X86ISA {
53
54// Unfortunately, the placement of the base field in a page table entry is
55// very erratic and would make a mess here. It might be moved here at some
56// point in the future.
57BitUnion64(PageTableEntry)
58 Bitfield<63> nx;
59 Bitfield<11, 9> avl;
60 Bitfield<8> g;
61 Bitfield<7> ps;
62 Bitfield<6> d;
63 Bitfield<5> a;
64 Bitfield<4> pcd;
65 Bitfield<3> pwt;
66 Bitfield<2> u;
67 Bitfield<1> w;
68 Bitfield<0> p;
69EndBitUnion(PageTableEntry)
70
71Fault
72Walker::start(ThreadContext * _tc, BaseTLB::Translation *_translation,
73 RequestPtr _req, BaseTLB::Mode _mode)
74{
75 // TODO: in timing mode, instead of blocking when there are other
76 // outstanding requests, see if this request can be coalesced with
77 // another one (i.e. either coalesce or start walk)
78 WalkerState * newState = new WalkerState(this, _translation, _req);
79 newState->initState(_tc, _mode, sys->getMemoryMode() == Enums::timing);
80 if (currStates.size()) {
81 assert(newState->isTiming());
82 DPRINTF(PageTableWalker, "Walks in progress: %d\n", currStates.size());
83 currStates.push_back(newState);
84 return NoFault;
85 } else {
86 currStates.push_back(newState);
87 Fault fault = newState->startWalk();
88 if (!newState->isTiming()) {
89 currStates.pop_front();
90 delete newState;
91 }
92 return fault;
93 }
94}
95
96Fault
97Walker::startFunctional(ThreadContext * _tc, Addr &addr, Addr &pageSize,
98 BaseTLB::Mode _mode)
99{
100 funcState.initState(_tc, _mode);
101 return funcState.startFunctional(addr, pageSize);
102}
103
104bool
105Walker::WalkerPort::recvTiming(PacketPtr pkt)
106{
107 return walker->recvTiming(pkt);
108}
109
110bool
111Walker::recvTiming(PacketPtr pkt)
112{
| 14 * Copyright (c) 2007 The Hewlett-Packard Development Company
15 * All rights reserved.
16 *
17 * The license below extends only to copyright in the software and shall
18 * not be construed as granting a license to any other intellectual
19 * property including but not limited to intellectual property relating
20 * to a hardware implementation of the functionality of the software
21 * licensed hereunder. You may use the software subject to the license
22 * terms below provided that you ensure that this notice is replicated
23 * unmodified and in its entirety in all distributions of the software,
24 * modified or unmodified, in source code or in binary form.
25 *
26 * Redistribution and use in source and binary forms, with or without
27 * modification, are permitted provided that the following conditions are
28 * met: redistributions of source code must retain the above copyright
29 * notice, this list of conditions and the following disclaimer;
30 * redistributions in binary form must reproduce the above copyright
31 * notice, this list of conditions and the following disclaimer in the
32 * documentation and/or other materials provided with the distribution;
33 * neither the name of the copyright holders nor the names of its
34 * contributors may be used to endorse or promote products derived from
35 * this software without specific prior written permission.
36 *
37 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
38 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
39 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
40 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
41 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
42 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
43 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
44 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
45 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
46 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
47 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
48 *
49 * Authors: Gabe Black
50 */
51
52#include "arch/x86/pagetable.hh"
53#include "arch/x86/pagetable_walker.hh"
54#include "arch/x86/tlb.hh"
55#include "arch/x86/vtophys.hh"
56#include "base/bitfield.hh"
57#include "cpu/base.hh"
58#include "cpu/thread_context.hh"
59#include "debug/PageTableWalker.hh"
60#include "mem/packet_access.hh"
61#include "mem/request.hh"
62#include "sim/system.hh"
63
64namespace X86ISA {
65
66// Unfortunately, the placement of the base field in a page table entry is
67// very erratic and would make a mess here. It might be moved here at some
68// point in the future.
69BitUnion64(PageTableEntry)
70 Bitfield<63> nx;
71 Bitfield<11, 9> avl;
72 Bitfield<8> g;
73 Bitfield<7> ps;
74 Bitfield<6> d;
75 Bitfield<5> a;
76 Bitfield<4> pcd;
77 Bitfield<3> pwt;
78 Bitfield<2> u;
79 Bitfield<1> w;
80 Bitfield<0> p;
81EndBitUnion(PageTableEntry)
82
83Fault
84Walker::start(ThreadContext * _tc, BaseTLB::Translation *_translation,
85 RequestPtr _req, BaseTLB::Mode _mode)
86{
87 // TODO: in timing mode, instead of blocking when there are other
88 // outstanding requests, see if this request can be coalesced with
89 // another one (i.e. either coalesce or start walk)
90 WalkerState * newState = new WalkerState(this, _translation, _req);
91 newState->initState(_tc, _mode, sys->getMemoryMode() == Enums::timing);
92 if (currStates.size()) {
93 assert(newState->isTiming());
94 DPRINTF(PageTableWalker, "Walks in progress: %d\n", currStates.size());
95 currStates.push_back(newState);
96 return NoFault;
97 } else {
98 currStates.push_back(newState);
99 Fault fault = newState->startWalk();
100 if (!newState->isTiming()) {
101 currStates.pop_front();
102 delete newState;
103 }
104 return fault;
105 }
106}
107
108Fault
109Walker::startFunctional(ThreadContext * _tc, Addr &addr, Addr &pageSize,
110 BaseTLB::Mode _mode)
111{
112 funcState.initState(_tc, _mode);
113 return funcState.startFunctional(addr, pageSize);
114}
115
116bool
117Walker::WalkerPort::recvTiming(PacketPtr pkt)
118{
119 return walker->recvTiming(pkt);
120}
121
122bool
123Walker::recvTiming(PacketPtr pkt)
124{
|
113 if (pkt->isResponse() || pkt->wasNacked()) {
114 WalkerSenderState * senderState =
115 dynamic_cast<WalkerSenderState *>(pkt->senderState);
116 pkt->senderState = senderState->saved;
117 WalkerState * senderWalk = senderState->senderWalk;
118 bool walkComplete = senderWalk->recvPacket(pkt);
119 delete senderState;
120 if (walkComplete) {
121 std::list<WalkerState *>::iterator iter;
122 for (iter = currStates.begin(); iter != currStates.end(); iter++) {
123 WalkerState * walkerState = *(iter);
124 if (walkerState == senderWalk) {
125 iter = currStates.erase(iter);
126 break;
127 }
| 125 assert(pkt->isResponse());
126 WalkerSenderState * senderState =
127 dynamic_cast(pkt->senderState);
128 pkt->senderState = senderState->saved;
129 WalkerState * senderWalk = senderState->senderWalk;
130 bool walkComplete = senderWalk->recvPacket(pkt);
131 delete senderState;
132 if (walkComplete) {
133 std::list::iterator iter;
134 for (iter = currStates.begin(); iter != currStates.end(); iter++) {
135 WalkerState * walkerState = *(iter);
136 if (walkerState == senderWalk) {
137 iter = currStates.erase(iter);
138 break;
|
128 }
| 139 }
|
129 delete senderWalk;
130 // Since we block requests when another is outstanding, we
131 // need to check if there is a waiting request to be serviced
132 if (currStates.size()) {
133 WalkerState * newState = currStates.front();
134 if (!newState->wasStarted())
135 newState->startWalk();
136 }
| |
137 }
| 140 }
|
138 } else {
139 DPRINTF(PageTableWalker, "Received strange packet\n");
| 141 delete senderWalk;
142 // Since we block requests when another is outstanding, we
143 // need to check if there is a waiting request to be serviced
144 if (currStates.size()) {
145 WalkerState * newState = currStates.front();
146 if (!newState->wasStarted())
147 newState->startWalk();
148 }
|
140 }
141 return true;
142}
143
| 149 }
150 return true;
151}
152
|
144Tick
145Walker::WalkerPort::recvAtomic(PacketPtr pkt)
146{
147 return 0;
148}
149
| |
150void
| 153void
|
151Walker::WalkerPort::recvFunctional(PacketPtr pkt)
152{
153 return;
154}
155
156void
| |
157Walker::WalkerPort::recvRetry()
158{
159 walker->recvRetry();
160}
161
162void
163Walker::recvRetry()
164{
165 std::list<WalkerState *>::iterator iter;
166 for (iter = currStates.begin(); iter != currStates.end(); iter++) {
167 WalkerState * walkerState = *(iter);
168 if (walkerState->isRetrying()) {
169 walkerState->retry();
170 }
171 }
172}
173
174bool Walker::sendTiming(WalkerState* sendingState, PacketPtr pkt)
175{
176 pkt->senderState = new WalkerSenderState(sendingState, pkt->senderState);
177 return port.sendTiming(pkt);
178}
179
180MasterPort &
181Walker::getMasterPort(const std::string &if_name, int idx)
182{
183 if (if_name == "port")
184 return port;
185 else
186 return MemObject::getMasterPort(if_name, idx);
187}
188
189void
190Walker::WalkerState::initState(ThreadContext * _tc,
191 BaseTLB::Mode _mode, bool _isTiming)
192{
193 assert(state == Ready);
194 started = false;
195 tc = _tc;
196 mode = _mode;
197 timing = _isTiming;
198}
199
200Fault
201Walker::WalkerState::startWalk()
202{
203 Fault fault = NoFault;
204 assert(started == false);
205 started = true;
206 setupWalk(req->getVaddr());
207 if (timing) {
208 nextState = state;
209 state = Waiting;
210 timingFault = NoFault;
211 sendPackets();
212 } else {
213 do {
214 walker->port.sendAtomic(read);
215 PacketPtr write = NULL;
216 fault = stepWalk(write);
217 assert(fault == NoFault || read == NULL);
218 state = nextState;
219 nextState = Ready;
220 if (write)
221 walker->port.sendAtomic(write);
222 } while(read);
223 state = Ready;
224 nextState = Waiting;
225 }
226 return fault;
227}
228
229Fault
230Walker::WalkerState::startFunctional(Addr &addr, Addr &pageSize)
231{
232 Fault fault = NoFault;
233 assert(started == false);
234 started = true;
235 setupWalk(addr);
236
237 do {
238 walker->port.sendFunctional(read);
239 // On a functional access (page table lookup), writes should
240 // not happen so this pointer is ignored after stepWalk
241 PacketPtr write = NULL;
242 fault = stepWalk(write);
243 assert(fault == NoFault || read == NULL);
244 state = nextState;
245 nextState = Ready;
246 } while(read);
247 pageSize = entry.size;
248 addr = entry.paddr;
249
250 return fault;
251}
252
253Fault
254Walker::WalkerState::stepWalk(PacketPtr &write)
255{
256 assert(state != Ready && state != Waiting);
257 Fault fault = NoFault;
258 write = NULL;
259 PageTableEntry pte;
260 if (dataSize == 8)
261 pte = read->get<uint64_t>();
262 else
263 pte = read->get<uint32_t>();
264 VAddr vaddr = entry.vaddr;
265 bool uncacheable = pte.pcd;
266 Addr nextRead = 0;
267 bool doWrite = false;
268 bool doTLBInsert = false;
269 bool doEndWalk = false;
270 bool badNX = pte.nx && mode == BaseTLB::Execute && enableNX;
271 switch(state) {
272 case LongPML4:
273 DPRINTF(PageTableWalker,
274 "Got long mode PML4 entry %#016x.\n", (uint64_t)pte);
275 nextRead = ((uint64_t)pte & (mask(40) << 12)) + vaddr.longl3 * dataSize;
276 doWrite = !pte.a;
277 pte.a = 1;
278 entry.writable = pte.w;
279 entry.user = pte.u;
280 if (badNX || !pte.p) {
281 doEndWalk = true;
282 fault = pageFault(pte.p);
283 break;
284 }
285 entry.noExec = pte.nx;
286 nextState = LongPDP;
287 break;
288 case LongPDP:
289 DPRINTF(PageTableWalker,
290 "Got long mode PDP entry %#016x.\n", (uint64_t)pte);
291 nextRead = ((uint64_t)pte & (mask(40) << 12)) + vaddr.longl2 * dataSize;
292 doWrite = !pte.a;
293 pte.a = 1;
294 entry.writable = entry.writable && pte.w;
295 entry.user = entry.user && pte.u;
296 if (badNX || !pte.p) {
297 doEndWalk = true;
298 fault = pageFault(pte.p);
299 break;
300 }
301 nextState = LongPD;
302 break;
303 case LongPD:
304 DPRINTF(PageTableWalker,
305 "Got long mode PD entry %#016x.\n", (uint64_t)pte);
306 doWrite = !pte.a;
307 pte.a = 1;
308 entry.writable = entry.writable && pte.w;
309 entry.user = entry.user && pte.u;
310 if (badNX || !pte.p) {
311 doEndWalk = true;
312 fault = pageFault(pte.p);
313 break;
314 }
315 if (!pte.ps) {
316 // 4 KB page
317 entry.size = 4 * (1 << 10);
318 nextRead =
319 ((uint64_t)pte & (mask(40) << 12)) + vaddr.longl1 * dataSize;
320 nextState = LongPTE;
321 break;
322 } else {
323 // 2 MB page
324 entry.size = 2 * (1 << 20);
325 entry.paddr = (uint64_t)pte & (mask(31) << 21);
326 entry.uncacheable = uncacheable;
327 entry.global = pte.g;
328 entry.patBit = bits(pte, 12);
329 entry.vaddr = entry.vaddr & ~((2 * (1 << 20)) - 1);
330 doTLBInsert = true;
331 doEndWalk = true;
332 break;
333 }
334 case LongPTE:
335 DPRINTF(PageTableWalker,
336 "Got long mode PTE entry %#016x.\n", (uint64_t)pte);
337 doWrite = !pte.a;
338 pte.a = 1;
339 entry.writable = entry.writable && pte.w;
340 entry.user = entry.user && pte.u;
341 if (badNX || !pte.p) {
342 doEndWalk = true;
343 fault = pageFault(pte.p);
344 break;
345 }
346 entry.paddr = (uint64_t)pte & (mask(40) << 12);
347 entry.uncacheable = uncacheable;
348 entry.global = pte.g;
349 entry.patBit = bits(pte, 12);
350 entry.vaddr = entry.vaddr & ~((4 * (1 << 10)) - 1);
351 doTLBInsert = true;
352 doEndWalk = true;
353 break;
354 case PAEPDP:
355 DPRINTF(PageTableWalker,
356 "Got legacy mode PAE PDP entry %#08x.\n", (uint32_t)pte);
357 nextRead = ((uint64_t)pte & (mask(40) << 12)) + vaddr.pael2 * dataSize;
358 if (!pte.p) {
359 doEndWalk = true;
360 fault = pageFault(pte.p);
361 break;
362 }
363 nextState = PAEPD;
364 break;
365 case PAEPD:
366 DPRINTF(PageTableWalker,
367 "Got legacy mode PAE PD entry %#08x.\n", (uint32_t)pte);
368 doWrite = !pte.a;
369 pte.a = 1;
370 entry.writable = pte.w;
371 entry.user = pte.u;
372 if (badNX || !pte.p) {
373 doEndWalk = true;
374 fault = pageFault(pte.p);
375 break;
376 }
377 if (!pte.ps) {
378 // 4 KB page
379 entry.size = 4 * (1 << 10);
380 nextRead = ((uint64_t)pte & (mask(40) << 12)) + vaddr.pael1 * dataSize;
381 nextState = PAEPTE;
382 break;
383 } else {
384 // 2 MB page
385 entry.size = 2 * (1 << 20);
386 entry.paddr = (uint64_t)pte & (mask(31) << 21);
387 entry.uncacheable = uncacheable;
388 entry.global = pte.g;
389 entry.patBit = bits(pte, 12);
390 entry.vaddr = entry.vaddr & ~((2 * (1 << 20)) - 1);
391 doTLBInsert = true;
392 doEndWalk = true;
393 break;
394 }
395 case PAEPTE:
396 DPRINTF(PageTableWalker,
397 "Got legacy mode PAE PTE entry %#08x.\n", (uint32_t)pte);
398 doWrite = !pte.a;
399 pte.a = 1;
400 entry.writable = entry.writable && pte.w;
401 entry.user = entry.user && pte.u;
402 if (badNX || !pte.p) {
403 doEndWalk = true;
404 fault = pageFault(pte.p);
405 break;
406 }
407 entry.paddr = (uint64_t)pte & (mask(40) << 12);
408 entry.uncacheable = uncacheable;
409 entry.global = pte.g;
410 entry.patBit = bits(pte, 7);
411 entry.vaddr = entry.vaddr & ~((4 * (1 << 10)) - 1);
412 doTLBInsert = true;
413 doEndWalk = true;
414 break;
415 case PSEPD:
416 DPRINTF(PageTableWalker,
417 "Got legacy mode PSE PD entry %#08x.\n", (uint32_t)pte);
418 doWrite = !pte.a;
419 pte.a = 1;
420 entry.writable = pte.w;
421 entry.user = pte.u;
422 if (!pte.p) {
423 doEndWalk = true;
424 fault = pageFault(pte.p);
425 break;
426 }
427 if (!pte.ps) {
428 // 4 KB page
429 entry.size = 4 * (1 << 10);
430 nextRead =
431 ((uint64_t)pte & (mask(20) << 12)) + vaddr.norml2 * dataSize;
432 nextState = PTE;
433 break;
434 } else {
435 // 4 MB page
436 entry.size = 4 * (1 << 20);
437 entry.paddr = bits(pte, 20, 13) << 32 | bits(pte, 31, 22) << 22;
438 entry.uncacheable = uncacheable;
439 entry.global = pte.g;
440 entry.patBit = bits(pte, 12);
441 entry.vaddr = entry.vaddr & ~((4 * (1 << 20)) - 1);
442 doTLBInsert = true;
443 doEndWalk = true;
444 break;
445 }
446 case PD:
447 DPRINTF(PageTableWalker,
448 "Got legacy mode PD entry %#08x.\n", (uint32_t)pte);
449 doWrite = !pte.a;
450 pte.a = 1;
451 entry.writable = pte.w;
452 entry.user = pte.u;
453 if (!pte.p) {
454 doEndWalk = true;
455 fault = pageFault(pte.p);
456 break;
457 }
458 // 4 KB page
459 entry.size = 4 * (1 << 10);
460 nextRead = ((uint64_t)pte & (mask(20) << 12)) + vaddr.norml2 * dataSize;
461 nextState = PTE;
462 break;
463 case PTE:
464 DPRINTF(PageTableWalker,
465 "Got legacy mode PTE entry %#08x.\n", (uint32_t)pte);
466 doWrite = !pte.a;
467 pte.a = 1;
468 entry.writable = pte.w;
469 entry.user = pte.u;
470 if (!pte.p) {
471 doEndWalk = true;
472 fault = pageFault(pte.p);
473 break;
474 }
475 entry.paddr = (uint64_t)pte & (mask(20) << 12);
476 entry.uncacheable = uncacheable;
477 entry.global = pte.g;
478 entry.patBit = bits(pte, 7);
479 entry.vaddr = entry.vaddr & ~((4 * (1 << 10)) - 1);
480 doTLBInsert = true;
481 doEndWalk = true;
482 break;
483 default:
484 panic("Unknown page table walker state %d!\n");
485 }
486 if (doEndWalk) {
487 if (doTLBInsert)
488 if (!functional)
489 walker->tlb->insert(entry.vaddr, entry);
490 endWalk();
491 } else {
492 PacketPtr oldRead = read;
493 //If we didn't return, we're setting up another read.
494 Request::Flags flags = oldRead->req->getFlags();
495 flags.set(Request::UNCACHEABLE, uncacheable);
496 RequestPtr request =
497 new Request(nextRead, oldRead->getSize(), flags, walker->masterId);
498 read = new Packet(request, MemCmd::ReadReq, Packet::Broadcast);
499 read->allocate();
500 // If we need to write, adjust the read packet to write the modified
501 // value back to memory.
502 if (doWrite) {
503 write = oldRead;
504 write->set<uint64_t>(pte);
505 write->cmd = MemCmd::WriteReq;
506 write->setDest(Packet::Broadcast);
507 } else {
508 write = NULL;
509 delete oldRead->req;
510 delete oldRead;
511 }
512 }
513 return fault;
514}
515
516void
517Walker::WalkerState::endWalk()
518{
519 nextState = Ready;
520 delete read->req;
521 delete read;
522 read = NULL;
523}
524
525void
526Walker::WalkerState::setupWalk(Addr vaddr)
527{
528 VAddr addr = vaddr;
529 CR3 cr3 = tc->readMiscRegNoEffect(MISCREG_CR3);
530 // Check if we're in long mode or not
531 Efer efer = tc->readMiscRegNoEffect(MISCREG_EFER);
532 dataSize = 8;
533 Addr topAddr;
534 if (efer.lma) {
535 // Do long mode.
536 state = LongPML4;
537 topAddr = (cr3.longPdtb << 12) + addr.longl4 * dataSize;
538 enableNX = efer.nxe;
539 } else {
540 // We're in some flavor of legacy mode.
541 CR4 cr4 = tc->readMiscRegNoEffect(MISCREG_CR4);
542 if (cr4.pae) {
543 // Do legacy PAE.
544 state = PAEPDP;
545 topAddr = (cr3.paePdtb << 5) + addr.pael3 * dataSize;
546 enableNX = efer.nxe;
547 } else {
548 dataSize = 4;
549 topAddr = (cr3.pdtb << 12) + addr.norml2 * dataSize;
550 if (cr4.pse) {
551 // Do legacy PSE.
552 state = PSEPD;
553 } else {
554 // Do legacy non PSE.
555 state = PD;
556 }
557 enableNX = false;
558 }
559 }
560
561 nextState = Ready;
562 entry.vaddr = vaddr;
563
564 Request::Flags flags = Request::PHYSICAL;
565 if (cr3.pcd)
566 flags.set(Request::UNCACHEABLE);
567 RequestPtr request = new Request(topAddr, dataSize, flags, walker->masterId);
568 read = new Packet(request, MemCmd::ReadReq, Packet::Broadcast);
569 read->allocate();
570}
571
572bool
573Walker::WalkerState::recvPacket(PacketPtr pkt)
574{
| 154Walker::WalkerPort::recvRetry()
155{
156 walker->recvRetry();
157}
158
159void
160Walker::recvRetry()
161{
162 std::list<WalkerState *>::iterator iter;
163 for (iter = currStates.begin(); iter != currStates.end(); iter++) {
164 WalkerState * walkerState = *(iter);
165 if (walkerState->isRetrying()) {
166 walkerState->retry();
167 }
168 }
169}
170
171bool Walker::sendTiming(WalkerState* sendingState, PacketPtr pkt)
172{
173 pkt->senderState = new WalkerSenderState(sendingState, pkt->senderState);
174 return port.sendTiming(pkt);
175}
176
177MasterPort &
178Walker::getMasterPort(const std::string &if_name, int idx)
179{
180 if (if_name == "port")
181 return port;
182 else
183 return MemObject::getMasterPort(if_name, idx);
184}
185
186void
187Walker::WalkerState::initState(ThreadContext * _tc,
188 BaseTLB::Mode _mode, bool _isTiming)
189{
190 assert(state == Ready);
191 started = false;
192 tc = _tc;
193 mode = _mode;
194 timing = _isTiming;
195}
196
197Fault
198Walker::WalkerState::startWalk()
199{
200 Fault fault = NoFault;
201 assert(started == false);
202 started = true;
203 setupWalk(req->getVaddr());
204 if (timing) {
205 nextState = state;
206 state = Waiting;
207 timingFault = NoFault;
208 sendPackets();
209 } else {
210 do {
211 walker->port.sendAtomic(read);
212 PacketPtr write = NULL;
213 fault = stepWalk(write);
214 assert(fault == NoFault || read == NULL);
215 state = nextState;
216 nextState = Ready;
217 if (write)
218 walker->port.sendAtomic(write);
219 } while(read);
220 state = Ready;
221 nextState = Waiting;
222 }
223 return fault;
224}
225
226Fault
227Walker::WalkerState::startFunctional(Addr &addr, Addr &pageSize)
228{
229 Fault fault = NoFault;
230 assert(started == false);
231 started = true;
232 setupWalk(addr);
233
234 do {
235 walker->port.sendFunctional(read);
236 // On a functional access (page table lookup), writes should
237 // not happen so this pointer is ignored after stepWalk
238 PacketPtr write = NULL;
239 fault = stepWalk(write);
240 assert(fault == NoFault || read == NULL);
241 state = nextState;
242 nextState = Ready;
243 } while(read);
244 pageSize = entry.size;
245 addr = entry.paddr;
246
247 return fault;
248}
249
250Fault
251Walker::WalkerState::stepWalk(PacketPtr &write)
252{
253 assert(state != Ready && state != Waiting);
254 Fault fault = NoFault;
255 write = NULL;
256 PageTableEntry pte;
257 if (dataSize == 8)
258 pte = read->get<uint64_t>();
259 else
260 pte = read->get<uint32_t>();
261 VAddr vaddr = entry.vaddr;
262 bool uncacheable = pte.pcd;
263 Addr nextRead = 0;
264 bool doWrite = false;
265 bool doTLBInsert = false;
266 bool doEndWalk = false;
267 bool badNX = pte.nx && mode == BaseTLB::Execute && enableNX;
268 switch(state) {
269 case LongPML4:
270 DPRINTF(PageTableWalker,
271 "Got long mode PML4 entry %#016x.\n", (uint64_t)pte);
272 nextRead = ((uint64_t)pte & (mask(40) << 12)) + vaddr.longl3 * dataSize;
273 doWrite = !pte.a;
274 pte.a = 1;
275 entry.writable = pte.w;
276 entry.user = pte.u;
277 if (badNX || !pte.p) {
278 doEndWalk = true;
279 fault = pageFault(pte.p);
280 break;
281 }
282 entry.noExec = pte.nx;
283 nextState = LongPDP;
284 break;
285 case LongPDP:
286 DPRINTF(PageTableWalker,
287 "Got long mode PDP entry %#016x.\n", (uint64_t)pte);
288 nextRead = ((uint64_t)pte & (mask(40) << 12)) + vaddr.longl2 * dataSize;
289 doWrite = !pte.a;
290 pte.a = 1;
291 entry.writable = entry.writable && pte.w;
292 entry.user = entry.user && pte.u;
293 if (badNX || !pte.p) {
294 doEndWalk = true;
295 fault = pageFault(pte.p);
296 break;
297 }
298 nextState = LongPD;
299 break;
300 case LongPD:
301 DPRINTF(PageTableWalker,
302 "Got long mode PD entry %#016x.\n", (uint64_t)pte);
303 doWrite = !pte.a;
304 pte.a = 1;
305 entry.writable = entry.writable && pte.w;
306 entry.user = entry.user && pte.u;
307 if (badNX || !pte.p) {
308 doEndWalk = true;
309 fault = pageFault(pte.p);
310 break;
311 }
312 if (!pte.ps) {
313 // 4 KB page
314 entry.size = 4 * (1 << 10);
315 nextRead =
316 ((uint64_t)pte & (mask(40) << 12)) + vaddr.longl1 * dataSize;
317 nextState = LongPTE;
318 break;
319 } else {
320 // 2 MB page
321 entry.size = 2 * (1 << 20);
322 entry.paddr = (uint64_t)pte & (mask(31) << 21);
323 entry.uncacheable = uncacheable;
324 entry.global = pte.g;
325 entry.patBit = bits(pte, 12);
326 entry.vaddr = entry.vaddr & ~((2 * (1 << 20)) - 1);
327 doTLBInsert = true;
328 doEndWalk = true;
329 break;
330 }
331 case LongPTE:
332 DPRINTF(PageTableWalker,
333 "Got long mode PTE entry %#016x.\n", (uint64_t)pte);
334 doWrite = !pte.a;
335 pte.a = 1;
336 entry.writable = entry.writable && pte.w;
337 entry.user = entry.user && pte.u;
338 if (badNX || !pte.p) {
339 doEndWalk = true;
340 fault = pageFault(pte.p);
341 break;
342 }
343 entry.paddr = (uint64_t)pte & (mask(40) << 12);
344 entry.uncacheable = uncacheable;
345 entry.global = pte.g;
346 entry.patBit = bits(pte, 12);
347 entry.vaddr = entry.vaddr & ~((4 * (1 << 10)) - 1);
348 doTLBInsert = true;
349 doEndWalk = true;
350 break;
351 case PAEPDP:
352 DPRINTF(PageTableWalker,
353 "Got legacy mode PAE PDP entry %#08x.\n", (uint32_t)pte);
354 nextRead = ((uint64_t)pte & (mask(40) << 12)) + vaddr.pael2 * dataSize;
355 if (!pte.p) {
356 doEndWalk = true;
357 fault = pageFault(pte.p);
358 break;
359 }
360 nextState = PAEPD;
361 break;
362 case PAEPD:
363 DPRINTF(PageTableWalker,
364 "Got legacy mode PAE PD entry %#08x.\n", (uint32_t)pte);
365 doWrite = !pte.a;
366 pte.a = 1;
367 entry.writable = pte.w;
368 entry.user = pte.u;
369 if (badNX || !pte.p) {
370 doEndWalk = true;
371 fault = pageFault(pte.p);
372 break;
373 }
374 if (!pte.ps) {
375 // 4 KB page
376 entry.size = 4 * (1 << 10);
377 nextRead = ((uint64_t)pte & (mask(40) << 12)) + vaddr.pael1 * dataSize;
378 nextState = PAEPTE;
379 break;
380 } else {
381 // 2 MB page
382 entry.size = 2 * (1 << 20);
383 entry.paddr = (uint64_t)pte & (mask(31) << 21);
384 entry.uncacheable = uncacheable;
385 entry.global = pte.g;
386 entry.patBit = bits(pte, 12);
387 entry.vaddr = entry.vaddr & ~((2 * (1 << 20)) - 1);
388 doTLBInsert = true;
389 doEndWalk = true;
390 break;
391 }
392 case PAEPTE:
393 DPRINTF(PageTableWalker,
394 "Got legacy mode PAE PTE entry %#08x.\n", (uint32_t)pte);
395 doWrite = !pte.a;
396 pte.a = 1;
397 entry.writable = entry.writable && pte.w;
398 entry.user = entry.user && pte.u;
399 if (badNX || !pte.p) {
400 doEndWalk = true;
401 fault = pageFault(pte.p);
402 break;
403 }
404 entry.paddr = (uint64_t)pte & (mask(40) << 12);
405 entry.uncacheable = uncacheable;
406 entry.global = pte.g;
407 entry.patBit = bits(pte, 7);
408 entry.vaddr = entry.vaddr & ~((4 * (1 << 10)) - 1);
409 doTLBInsert = true;
410 doEndWalk = true;
411 break;
412 case PSEPD:
413 DPRINTF(PageTableWalker,
414 "Got legacy mode PSE PD entry %#08x.\n", (uint32_t)pte);
415 doWrite = !pte.a;
416 pte.a = 1;
417 entry.writable = pte.w;
418 entry.user = pte.u;
419 if (!pte.p) {
420 doEndWalk = true;
421 fault = pageFault(pte.p);
422 break;
423 }
424 if (!pte.ps) {
425 // 4 KB page
426 entry.size = 4 * (1 << 10);
427 nextRead =
428 ((uint64_t)pte & (mask(20) << 12)) + vaddr.norml2 * dataSize;
429 nextState = PTE;
430 break;
431 } else {
432 // 4 MB page
433 entry.size = 4 * (1 << 20);
434 entry.paddr = bits(pte, 20, 13) << 32 | bits(pte, 31, 22) << 22;
435 entry.uncacheable = uncacheable;
436 entry.global = pte.g;
437 entry.patBit = bits(pte, 12);
438 entry.vaddr = entry.vaddr & ~((4 * (1 << 20)) - 1);
439 doTLBInsert = true;
440 doEndWalk = true;
441 break;
442 }
443 case PD:
444 DPRINTF(PageTableWalker,
445 "Got legacy mode PD entry %#08x.\n", (uint32_t)pte);
446 doWrite = !pte.a;
447 pte.a = 1;
448 entry.writable = pte.w;
449 entry.user = pte.u;
450 if (!pte.p) {
451 doEndWalk = true;
452 fault = pageFault(pte.p);
453 break;
454 }
455 // 4 KB page
456 entry.size = 4 * (1 << 10);
457 nextRead = ((uint64_t)pte & (mask(20) << 12)) + vaddr.norml2 * dataSize;
458 nextState = PTE;
459 break;
460 case PTE:
461 DPRINTF(PageTableWalker,
462 "Got legacy mode PTE entry %#08x.\n", (uint32_t)pte);
463 doWrite = !pte.a;
464 pte.a = 1;
465 entry.writable = pte.w;
466 entry.user = pte.u;
467 if (!pte.p) {
468 doEndWalk = true;
469 fault = pageFault(pte.p);
470 break;
471 }
472 entry.paddr = (uint64_t)pte & (mask(20) << 12);
473 entry.uncacheable = uncacheable;
474 entry.global = pte.g;
475 entry.patBit = bits(pte, 7);
476 entry.vaddr = entry.vaddr & ~((4 * (1 << 10)) - 1);
477 doTLBInsert = true;
478 doEndWalk = true;
479 break;
480 default:
481 panic("Unknown page table walker state %d!\n");
482 }
483 if (doEndWalk) {
484 if (doTLBInsert)
485 if (!functional)
486 walker->tlb->insert(entry.vaddr, entry);
487 endWalk();
488 } else {
489 PacketPtr oldRead = read;
490 //If we didn't return, we're setting up another read.
491 Request::Flags flags = oldRead->req->getFlags();
492 flags.set(Request::UNCACHEABLE, uncacheable);
493 RequestPtr request =
494 new Request(nextRead, oldRead->getSize(), flags, walker->masterId);
495 read = new Packet(request, MemCmd::ReadReq, Packet::Broadcast);
496 read->allocate();
497 // If we need to write, adjust the read packet to write the modified
498 // value back to memory.
499 if (doWrite) {
500 write = oldRead;
501 write->set<uint64_t>(pte);
502 write->cmd = MemCmd::WriteReq;
503 write->setDest(Packet::Broadcast);
504 } else {
505 write = NULL;
506 delete oldRead->req;
507 delete oldRead;
508 }
509 }
510 return fault;
511}
512
513void
514Walker::WalkerState::endWalk()
515{
516 nextState = Ready;
517 delete read->req;
518 delete read;
519 read = NULL;
520}
521
522void
523Walker::WalkerState::setupWalk(Addr vaddr)
524{
525 VAddr addr = vaddr;
526 CR3 cr3 = tc->readMiscRegNoEffect(MISCREG_CR3);
527 // Check if we're in long mode or not
528 Efer efer = tc->readMiscRegNoEffect(MISCREG_EFER);
529 dataSize = 8;
530 Addr topAddr;
531 if (efer.lma) {
532 // Do long mode.
533 state = LongPML4;
534 topAddr = (cr3.longPdtb << 12) + addr.longl4 * dataSize;
535 enableNX = efer.nxe;
536 } else {
537 // We're in some flavor of legacy mode.
538 CR4 cr4 = tc->readMiscRegNoEffect(MISCREG_CR4);
539 if (cr4.pae) {
540 // Do legacy PAE.
541 state = PAEPDP;
542 topAddr = (cr3.paePdtb << 5) + addr.pael3 * dataSize;
543 enableNX = efer.nxe;
544 } else {
545 dataSize = 4;
546 topAddr = (cr3.pdtb << 12) + addr.norml2 * dataSize;
547 if (cr4.pse) {
548 // Do legacy PSE.
549 state = PSEPD;
550 } else {
551 // Do legacy non PSE.
552 state = PD;
553 }
554 enableNX = false;
555 }
556 }
557
558 nextState = Ready;
559 entry.vaddr = vaddr;
560
561 Request::Flags flags = Request::PHYSICAL;
562 if (cr3.pcd)
563 flags.set(Request::UNCACHEABLE);
564 RequestPtr request = new Request(topAddr, dataSize, flags, walker->masterId);
565 read = new Packet(request, MemCmd::ReadReq, Packet::Broadcast);
566 read->allocate();
567}
568
569bool
570Walker::WalkerState::recvPacket(PacketPtr pkt)
571{
|
575 if (pkt->isResponse() && !pkt->wasNacked()) {
| 572 assert(pkt->isResponse());
573 if (!pkt->wasNacked()) {
|
576 assert(inflight);
577 assert(state == Waiting);
578 assert(!read);
579 inflight--;
580 if (pkt->isRead()) {
581 state = nextState;
582 nextState = Ready;
583 PacketPtr write = NULL;
584 read = pkt;
585 timingFault = stepWalk(write);
586 state = Waiting;
587 assert(timingFault == NoFault || read == NULL);
588 if (write) {
589 writes.push_back(write);
590 }
591 sendPackets();
592 } else {
593 sendPackets();
594 }
595 if (inflight == 0 && read == NULL && writes.size() == 0) {
596 state = Ready;
597 nextState = Waiting;
598 if (timingFault == NoFault) {
599 /*
600 * Finish the translation. Now that we now the right entry is
601 * in the TLB, this should work with no memory accesses.
602 * There could be new faults unrelated to the table walk like
603 * permissions violations, so we'll need the return value as
604 * well.
605 */
606 bool delayedResponse;
607 Fault fault = walker->tlb->translate(req, tc, NULL, mode,
608 delayedResponse, true);
609 assert(!delayedResponse);
610 // Let the CPU continue.
611 translation->finish(fault, req, tc, mode);
612 } else {
613 // There was a fault during the walk. Let the CPU know.
614 translation->finish(timingFault, req, tc, mode);
615 }
616 return true;
617 }
| 574 assert(inflight);
575 assert(state == Waiting);
576 assert(!read);
577 inflight--;
578 if (pkt->isRead()) {
579 state = nextState;
580 nextState = Ready;
581 PacketPtr write = NULL;
582 read = pkt;
583 timingFault = stepWalk(write);
584 state = Waiting;
585 assert(timingFault == NoFault || read == NULL);
586 if (write) {
587 writes.push_back(write);
588 }
589 sendPackets();
590 } else {
591 sendPackets();
592 }
593 if (inflight == 0 && read == NULL && writes.size() == 0) {
594 state = Ready;
595 nextState = Waiting;
596 if (timingFault == NoFault) {
597 /*
598 * Finish the translation. Now that we now the right entry is
599 * in the TLB, this should work with no memory accesses.
600 * There could be new faults unrelated to the table walk like
601 * permissions violations, so we'll need the return value as
602 * well.
603 */
604 bool delayedResponse;
605 Fault fault = walker->tlb->translate(req, tc, NULL, mode,
606 delayedResponse, true);
607 assert(!delayedResponse);
608 // Let the CPU continue.
609 translation->finish(fault, req, tc, mode);
610 } else {
611 // There was a fault during the walk. Let the CPU know.
612 translation->finish(timingFault, req, tc, mode);
613 }
614 return true;
615 }
|
618 } else if (pkt->wasNacked()) {
| 616 } else {
|
619 DPRINTF(PageTableWalker, "Request was nacked. Entering retry state\n");
620 pkt->reinitNacked();
621 if (!walker->sendTiming(this, pkt)) {
622 inflight--;
623 retrying = true;
624 if (pkt->isWrite()) {
625 writes.push_back(pkt);
626 } else {
627 assert(!read);
628 read = pkt;
629 }
630 }
631 }
632 return false;
633}
634
635void
636Walker::WalkerState::sendPackets()
637{
638 //If we're already waiting for the port to become available, just return.
639 if (retrying)
640 return;
641
642 //Reads always have priority
643 if (read) {
644 PacketPtr pkt = read;
645 read = NULL;
646 inflight++;
647 if (!walker->sendTiming(this, pkt)) {
648 retrying = true;
649 read = pkt;
650 inflight--;
651 return;
652 }
653 }
654 //Send off as many of the writes as we can.
655 while (writes.size()) {
656 PacketPtr write = writes.back();
657 writes.pop_back();
658 inflight++;
659 if (!walker->sendTiming(this, write)) {
660 retrying = true;
661 writes.push_back(write);
662 inflight--;
663 return;
664 }
665 }
666}
667
668bool
669Walker::WalkerState::isRetrying()
670{
671 return retrying;
672}
673
674bool
675Walker::WalkerState::isTiming()
676{
677 return timing;
678}
679
680bool
681Walker::WalkerState::wasStarted()
682{
683 return started;
684}
685
686void
687Walker::WalkerState::retry()
688{
689 retrying = false;
690 sendPackets();
691}
692
693Fault
694Walker::WalkerState::pageFault(bool present)
695{
696 DPRINTF(PageTableWalker, "Raising page fault.\n");
697 HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
698 if (mode == BaseTLB::Execute && !enableNX)
699 mode = BaseTLB::Read;
700 return new PageFault(entry.vaddr, present, mode, m5reg.cpl == 3, false);
701}
702
703/* end namespace X86ISA */ }
704
705X86ISA::Walker *
706X86PagetableWalkerParams::create()
707{
708 return new X86ISA::Walker(this);
709}
| 617 DPRINTF(PageTableWalker, "Request was nacked. Entering retry state\n");
618 pkt->reinitNacked();
619 if (!walker->sendTiming(this, pkt)) {
620 inflight--;
621 retrying = true;
622 if (pkt->isWrite()) {
623 writes.push_back(pkt);
624 } else {
625 assert(!read);
626 read = pkt;
627 }
628 }
629 }
630 return false;
631}
632
633void
634Walker::WalkerState::sendPackets()
635{
636 //If we're already waiting for the port to become available, just return.
637 if (retrying)
638 return;
639
640 //Reads always have priority
641 if (read) {
642 PacketPtr pkt = read;
643 read = NULL;
644 inflight++;
645 if (!walker->sendTiming(this, pkt)) {
646 retrying = true;
647 read = pkt;
648 inflight--;
649 return;
650 }
651 }
652 //Send off as many of the writes as we can.
653 while (writes.size()) {
654 PacketPtr write = writes.back();
655 writes.pop_back();
656 inflight++;
657 if (!walker->sendTiming(this, write)) {
658 retrying = true;
659 writes.push_back(write);
660 inflight--;
661 return;
662 }
663 }
664}
665
666bool
667Walker::WalkerState::isRetrying()
668{
669 return retrying;
670}
671
672bool
673Walker::WalkerState::isTiming()
674{
675 return timing;
676}
677
678bool
679Walker::WalkerState::wasStarted()
680{
681 return started;
682}
683
684void
685Walker::WalkerState::retry()
686{
687 retrying = false;
688 sendPackets();
689}
690
691Fault
692Walker::WalkerState::pageFault(bool present)
693{
694 DPRINTF(PageTableWalker, "Raising page fault.\n");
695 HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
696 if (mode == BaseTLB::Execute && !enableNX)
697 mode = BaseTLB::Read;
698 return new PageFault(entry.vaddr, present, mode, m5reg.cpl == 3, false);
699}
700
701/* end namespace X86ISA */ }
702
703X86ISA::Walker *
704X86PagetableWalkerParams::create()
705{
706 return new X86ISA::Walker(this);
707}
|