pagetable.hh (9115:6a0ab7d94d4e) pagetable.hh (10299:bec0c5ffc323)
1/*
1/*
2 * Copyright (c) 2014 Advanced Micro Devices, Inc.
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license

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37 * Authors: Gabe Black
38 */
39
40#ifndef __ARCH_X86_PAGETABLE_HH__
41#define __ARCH_X86_PAGETABLE_HH__
42
43#include <iostream>
44#include <string>
3 * Copyright (c) 2007 The Hewlett-Packard Development Company
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license

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38 * Authors: Gabe Black
39 */
40
41#ifndef __ARCH_X86_PAGETABLE_HH__
42#define __ARCH_X86_PAGETABLE_HH__
43
44#include <iostream>
45#include <string>
46#include <vector>
45
46#include "base/bitunion.hh"
47#include "base/misc.hh"
48#include "base/types.hh"
49#include "base/trie.hh"
47
48#include "base/bitunion.hh"
49#include "base/misc.hh"
50#include "base/types.hh"
51#include "base/trie.hh"
52#include "cpu/thread_context.hh"
53#include "arch/x86/system.hh"
54#include "debug/MMU.hh"
50
51class Checkpoint;
52
53namespace X86ISA
54{
55 struct TlbEntry;
56}
57

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68 Bitfield<20, 12> pael1;
69 Bitfield<29, 21> pael2;
70 Bitfield<31, 30> pael3;
71
72 Bitfield<21, 12> norml1;
73 Bitfield<31, 22> norml2;
74 EndBitUnion(VAddr)
75
55
56class Checkpoint;
57
58namespace X86ISA
59{
60 struct TlbEntry;
61}
62

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73 Bitfield<20, 12> pael1;
74 Bitfield<29, 21> pael2;
75 Bitfield<31, 30> pael3;
76
77 Bitfield<21, 12> norml1;
78 Bitfield<31, 22> norml2;
79 EndBitUnion(VAddr)
80
81 // Unfortunately, the placement of the base field in a page table entry is
82 // very erratic and would make a mess here. It might be moved here at some
83 // point in the future.
84 BitUnion64(PageTableEntry)
85 Bitfield<63> nx;
86 Bitfield<51, 12> base;
87 Bitfield<11, 9> avl;
88 Bitfield<8> g;
89 Bitfield<7> ps;
90 Bitfield<6> d;
91 Bitfield<5> a;
92 Bitfield<4> pcd;
93 Bitfield<3> pwt;
94 Bitfield<2> u;
95 Bitfield<1> w;
96 Bitfield<0> p;
97 EndBitUnion(PageTableEntry)
98
99
76 struct TlbEntry
77 {
78 // The base of the physical page.
79 Addr paddr;
80
81 // The beginning of the virtual page this entry maps.
82 Addr vaddr;
83 // The size of the page this represents, in address bits.

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122 int size()
123 {
124 return (1 << logBytes);
125 }
126
127 void serialize(std::ostream &os);
128 void unserialize(Checkpoint *cp, const std::string &section);
129 };
100 struct TlbEntry
101 {
102 // The base of the physical page.
103 Addr paddr;
104
105 // The beginning of the virtual page this entry maps.
106 Addr vaddr;
107 // The size of the page this represents, in address bits.

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146 int size()
147 {
148 return (1 << logBytes);
149 }
150
151 void serialize(std::ostream &os);
152 void unserialize(Checkpoint *cp, const std::string &section);
153 };
154
155 /** The size of each level of the page table expressed in base 2
156 * logarithmic values
157 */
158 const std::vector<uint8_t> PageTableLayout = {9, 9, 9, 9};
159
160 enum PTEField{
161 PTE_NotPresent = 0,
162 PTE_Present,
163 PTE_ReadOnly = 0,
164 PTE_ReadWrite,
165 PTE_Supervisor = 0,
166 PTE_UserSupervisor,
167 };
168
169 /** Page table operations specific to x86 ISA.
170 * Indended to be used as parameter of MultiLevelPageTable.
171 */
172 class PageTableOps
173 {
174 public:
175 void setPTEFields(PageTableEntry& PTE,
176 uint64_t present = PTE_Present,
177 uint64_t read_write = PTE_ReadWrite,
178 uint64_t user_supervisor = PTE_UserSupervisor)
179 {
180 PTE.p = present;
181 PTE.w = read_write;
182 PTE.u = user_supervisor;// both user and supervisor access allowed
183 }
184
185 /** returns the physical memory address of the page table */
186 Addr getBasePtr(ThreadContext* tc)
187 {
188 CR3 cr3 = pageTablePhysAddr;
189 DPRINTF(MMU, "CR3: %d\n", cr3);
190 return cr3.longPdtb;
191 }
192
193 /** returns the page number out of a page table entry */
194 Addr getPnum(PageTableEntry PTE)
195 {
196 return PTE.base;
197 }
198
199 /** sets the page number in a page table entry */
200 void setPnum(PageTableEntry& PTE, Addr paddr)
201 {
202 PTE.base = paddr;
203 }
204
205 /** returns the offsets to index in every level of a page
206 * table, contained in a virtual address
207 */
208 std::vector<uint64_t> getOffsets(Addr vaddr)
209 {
210 X86ISA::VAddr addr(vaddr);
211 return {addr.longl1, addr.longl2, addr.longl3, addr.longl4};
212 }
213 };
214
130}
131
132#endif
215}
216
217#endif