pagetable.hh (7087:fb8d5786ff30) pagetable.hh (8953:488d45aeb672)
1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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41#define __ARCH_X86_PAGETABLE_HH__
42
43#include <iostream>
44#include <string>
45
46#include "base/bitunion.hh"
47#include "base/misc.hh"
48#include "base/types.hh"
1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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41#define __ARCH_X86_PAGETABLE_HH__
42
43#include <iostream>
44#include <string>
45
46#include "base/bitunion.hh"
47#include "base/misc.hh"
48#include "base/types.hh"
49#include "base/trie.hh"
49
50class Checkpoint;
51
52namespace X86ISA
53{
50
51class Checkpoint;
52
53namespace X86ISA
54{
55 struct TlbEntry;
56}
57
58typedef Trie<Addr, X86ISA::TlbEntry> TlbEntryTrie;
59
60namespace X86ISA
61{
54 BitUnion64(VAddr)
55 Bitfield<20, 12> longl1;
56 Bitfield<29, 21> longl2;
57 Bitfield<38, 30> longl3;
58 Bitfield<47, 39> longl4;
59
60 Bitfield<20, 12> pael1;
61 Bitfield<29, 21> pael2;

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67
68 struct TlbEntry
69 {
70 // The base of the physical page.
71 Addr paddr;
72
73 // The beginning of the virtual page this entry maps.
74 Addr vaddr;
62 BitUnion64(VAddr)
63 Bitfield<20, 12> longl1;
64 Bitfield<29, 21> longl2;
65 Bitfield<38, 30> longl3;
66 Bitfield<47, 39> longl4;
67
68 Bitfield<20, 12> pael1;
69 Bitfield<29, 21> pael2;

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75
76 struct TlbEntry
77 {
78 // The base of the physical page.
79 Addr paddr;
80
81 // The beginning of the virtual page this entry maps.
82 Addr vaddr;
75 // The size of the page this entry represents.
76 Addr size;
83 // The size of the page this represents, in address bits.
84 unsigned logBytes;
77
78 // Read permission is always available, assuming it isn't blocked by
79 // other mechanisms.
80 bool writable;
81 // Whether this page is accesible without being in supervisor mode.
82 bool user;
83 // Whether to use write through or write back. M5 ignores this and
84 // lets the caches handle the writeback policy.
85 //bool pwt;
86 // Whether the page is cacheable or not.
87 bool uncacheable;
88 // Whether or not to kick this page out on a write to CR3.
89 bool global;
90 // A bit used to form an index into the PAT table.
91 bool patBit;
92 // Whether or not memory on this page can be executed.
93 bool noExec;
85
86 // Read permission is always available, assuming it isn't blocked by
87 // other mechanisms.
88 bool writable;
89 // Whether this page is accesible without being in supervisor mode.
90 bool user;
91 // Whether to use write through or write back. M5 ignores this and
92 // lets the caches handle the writeback policy.
93 //bool pwt;
94 // Whether the page is cacheable or not.
95 bool uncacheable;
96 // Whether or not to kick this page out on a write to CR3.
97 bool global;
98 // A bit used to form an index into the PAT table.
99 bool patBit;
100 // Whether or not memory on this page can be executed.
101 bool noExec;
102 // A sequence number to keep track of LRU.
103 uint64_t lruSeq;
94
104
105 TlbEntryTrie::Handle trieHandle;
106
95 TlbEntry(Addr asn, Addr _vaddr, Addr _paddr);
96 TlbEntry() {}
97
98 void
99 updateVaddr(Addr new_vaddr)
100 {
101 vaddr = new_vaddr;
102 }

--- 12 unchanged lines hidden --- 		107 TlbEntry(Addr asn, Addr _vaddr, Addr _paddr);
108 TlbEntry() {}
109
110 void
111 updateVaddr(Addr new_vaddr)
112 {
113 vaddr = new_vaddr;
114 }

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