pagetable.hh (10558:426665ec11a9) | pagetable.hh (10905:a6ca6831e775) |
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1/* 2 * Copyright (c) 2014 Advanced Micro Devices, Inc. 3 * Copyright (c) 2007 The Hewlett-Packard Development Company 4 * All rights reserved. 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 83 unchanged lines hidden (view full) --- 92 Bitfield<4> pcd; 93 Bitfield<3> pwt; 94 Bitfield<2> u; 95 Bitfield<1> w; 96 Bitfield<0> p; 97 EndBitUnion(PageTableEntry) 98 99 | 1/* 2 * Copyright (c) 2014 Advanced Micro Devices, Inc. 3 * Copyright (c) 2007 The Hewlett-Packard Development Company 4 * All rights reserved. 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 83 unchanged lines hidden (view full) --- 92 Bitfield<4> pcd; 93 Bitfield<3> pwt; 94 Bitfield<2> u; 95 Bitfield<1> w; 96 Bitfield<0> p; 97 EndBitUnion(PageTableEntry) 98 99 |
100 struct TlbEntry | 100 struct TlbEntry : public Serializable |
101 { 102 // The base of the physical page. 103 Addr paddr; 104 105 // The beginning of the virtual page this entry maps. 106 Addr vaddr; 107 // The size of the page this represents, in address bits. 108 unsigned logBytes; --- 16 unchanged lines hidden (view full) --- 125 bool noExec; 126 // A sequence number to keep track of LRU. 127 uint64_t lruSeq; 128 129 TlbEntryTrie::Handle trieHandle; 130 131 TlbEntry(Addr asn, Addr _vaddr, Addr _paddr, 132 bool uncacheable, bool read_only); | 101 { 102 // The base of the physical page. 103 Addr paddr; 104 105 // The beginning of the virtual page this entry maps. 106 Addr vaddr; 107 // The size of the page this represents, in address bits. 108 unsigned logBytes; --- 16 unchanged lines hidden (view full) --- 125 bool noExec; 126 // A sequence number to keep track of LRU. 127 uint64_t lruSeq; 128 129 TlbEntryTrie::Handle trieHandle; 130 131 TlbEntry(Addr asn, Addr _vaddr, Addr _paddr, 132 bool uncacheable, bool read_only); |
133 TlbEntry() {} | 133 TlbEntry(); |
134 135 void 136 updateVaddr(Addr new_vaddr) 137 { 138 vaddr = new_vaddr; 139 } 140 141 Addr pageStart() 142 { 143 return paddr; 144 } 145 146 // Return the page size in bytes 147 int size() 148 { 149 return (1 << logBytes); 150 } 151 | 134 135 void 136 updateVaddr(Addr new_vaddr) 137 { 138 vaddr = new_vaddr; 139 } 140 141 Addr pageStart() 142 { 143 return paddr; 144 } 145 146 // Return the page size in bytes 147 int size() 148 { 149 return (1 << logBytes); 150 } 151 |
152 void serialize(std::ostream &os); 153 void unserialize(Checkpoint *cp, const std::string §ion); | 152 void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; 153 void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; |
154 }; 155 156 /** The size of each level of the page table expressed in base 2 157 * logarithmic values 158 */ 159 const std::vector<uint8_t> PageTableLayout = {9, 9, 9, 9}; 160 161 /* x86 specific PTE flags */ --- 64 unchanged lines hidden --- | 154 }; 155 156 /** The size of each level of the page table expressed in base 2 157 * logarithmic values 158 */ 159 const std::vector<uint8_t> PageTableLayout = {9, 9, 9, 9}; 160 161 /* x86 specific PTE flags */ --- 64 unchanged lines hidden --- |