pagetable.hh (10299:bec0c5ffc323) | pagetable.hh (10558:426665ec11a9) |
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1/* 2 * Copyright (c) 2014 Advanced Micro Devices, Inc. 3 * Copyright (c) 2007 The Hewlett-Packard Development Company 4 * All rights reserved. 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 114 unchanged lines hidden (view full) --- 123 bool patBit; 124 // Whether or not memory on this page can be executed. 125 bool noExec; 126 // A sequence number to keep track of LRU. 127 uint64_t lruSeq; 128 129 TlbEntryTrie::Handle trieHandle; 130 | 1/* 2 * Copyright (c) 2014 Advanced Micro Devices, Inc. 3 * Copyright (c) 2007 The Hewlett-Packard Development Company 4 * All rights reserved. 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 114 unchanged lines hidden (view full) --- 123 bool patBit; 124 // Whether or not memory on this page can be executed. 125 bool noExec; 126 // A sequence number to keep track of LRU. 127 uint64_t lruSeq; 128 129 TlbEntryTrie::Handle trieHandle; 130 |
131 TlbEntry(Addr asn, Addr _vaddr, Addr _paddr); | 131 TlbEntry(Addr asn, Addr _vaddr, Addr _paddr, 132 bool uncacheable, bool read_only); |
132 TlbEntry() {} 133 134 void 135 updateVaddr(Addr new_vaddr) 136 { 137 vaddr = new_vaddr; 138 } 139 --- 12 unchanged lines hidden (view full) --- 152 void unserialize(Checkpoint *cp, const std::string §ion); 153 }; 154 155 /** The size of each level of the page table expressed in base 2 156 * logarithmic values 157 */ 158 const std::vector<uint8_t> PageTableLayout = {9, 9, 9, 9}; 159 | 133 TlbEntry() {} 134 135 void 136 updateVaddr(Addr new_vaddr) 137 { 138 vaddr = new_vaddr; 139 } 140 --- 12 unchanged lines hidden (view full) --- 153 void unserialize(Checkpoint *cp, const std::string §ion); 154 }; 155 156 /** The size of each level of the page table expressed in base 2 157 * logarithmic values 158 */ 159 const std::vector<uint8_t> PageTableLayout = {9, 9, 9, 9}; 160 |
161 /* x86 specific PTE flags */ |
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160 enum PTEField{ | 162 enum PTEField{ |
161 PTE_NotPresent = 0, 162 PTE_Present, 163 PTE_ReadOnly = 0, 164 PTE_ReadWrite, 165 PTE_Supervisor = 0, 166 PTE_UserSupervisor, | 163 PTE_NotPresent = 1, 164 PTE_Supervisor = 2, 165 PTE_ReadOnly = 4, 166 PTE_Uncacheable = 8, |
167 }; 168 169 /** Page table operations specific to x86 ISA. 170 * Indended to be used as parameter of MultiLevelPageTable. 171 */ 172 class PageTableOps 173 { 174 public: | 167 }; 168 169 /** Page table operations specific to x86 ISA. 170 * Indended to be used as parameter of MultiLevelPageTable. 171 */ 172 class PageTableOps 173 { 174 public: |
175 void setPTEFields(PageTableEntry& PTE, 176 uint64_t present = PTE_Present, 177 uint64_t read_write = PTE_ReadWrite, 178 uint64_t user_supervisor = PTE_UserSupervisor) | 175 void setPTEFields(PageTableEntry& PTE, uint64_t flags = 0) |
179 { | 176 { |
180 PTE.p = present; 181 PTE.w = read_write; 182 PTE.u = user_supervisor;// both user and supervisor access allowed | 177 PTE.p = flags & PTE_NotPresent ? 0 : 1; 178 PTE.pcd = flags & PTE_Uncacheable ? 1 : 0; 179 PTE.w = flags & PTE_ReadOnly ? 0 : 1; 180 PTE.u = flags & PTE_Supervisor ? 0 : 1; |
183 } 184 185 /** returns the physical memory address of the page table */ 186 Addr getBasePtr(ThreadContext* tc) 187 { 188 CR3 cr3 = pageTablePhysAddr; 189 DPRINTF(MMU, "CR3: %d\n", cr3); 190 return cr3.longPdtb; 191 } 192 193 /** returns the page number out of a page table entry */ 194 Addr getPnum(PageTableEntry PTE) 195 { 196 return PTE.base; 197 } 198 | 181 } 182 183 /** returns the physical memory address of the page table */ 184 Addr getBasePtr(ThreadContext* tc) 185 { 186 CR3 cr3 = pageTablePhysAddr; 187 DPRINTF(MMU, "CR3: %d\n", cr3); 188 return cr3.longPdtb; 189 } 190 191 /** returns the page number out of a page table entry */ 192 Addr getPnum(PageTableEntry PTE) 193 { 194 return PTE.base; 195 } 196 |
197 bool isUncacheable(const PageTableEntry PTE) 198 { 199 return PTE.pcd; 200 } 201 202 bool isReadOnly(PageTableEntry PTE) 203 { 204 return !PTE.w; 205 } 206 |
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199 /** sets the page number in a page table entry */ 200 void setPnum(PageTableEntry& PTE, Addr paddr) 201 { 202 PTE.base = paddr; 203 } 204 205 /** returns the offsets to index in every level of a page 206 * table, contained in a virtual address 207 */ 208 std::vector<uint64_t> getOffsets(Addr vaddr) 209 { 210 X86ISA::VAddr addr(vaddr); 211 return {addr.longl1, addr.longl2, addr.longl3, addr.longl4}; 212 } 213 }; 214 215} 216 217#endif | 207 /** sets the page number in a page table entry */ 208 void setPnum(PageTableEntry& PTE, Addr paddr) 209 { 210 PTE.base = paddr; 211 } 212 213 /** returns the offsets to index in every level of a page 214 * table, contained in a virtual address 215 */ 216 std::vector<uint64_t> getOffsets(Addr vaddr) 217 { 218 X86ISA::VAddr addr(vaddr); 219 return {addr.longl1, addr.longl2, addr.longl3, addr.longl4}; 220 } 221 }; 222 223} 224 225#endif |