9 * The software must be used only for Non-Commercial Use which means any
10 * use which is NOT directed to receiving any direct monetary
11 * compensation for, or commercial advantage from such use. Illustrative
12 * examples of non-commercial use are academic research, personal study,
13 * teaching, education and corporate research & development.
14 * Illustrative examples of commercial use are distributing products for
15 * commercial advantage and providing services using the software for
16 * commercial advantage.
17 *
18 * If you wish to use this software or functionality therein that may be
19 * covered by patents for commercial use, please contact:
20 * Director of Intellectual Property Licensing
21 * Office of Strategy and Technology
22 * Hewlett-Packard Company
23 * 1501 Page Mill Road
24 * Palo Alto, California 94304
25 *
26 * Redistributions of source code must retain the above copyright notice,
27 * this list of conditions and the following disclaimer. Redistributions
28 * in binary form must reproduce the above copyright notice, this list of
29 * conditions and the following disclaimer in the documentation and/or
30 * other materials provided with the distribution. Neither the name of
31 * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
| 14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
|
42 *
43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
46 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
47 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
49 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 *
55 * Authors: Gabe Black
56 */
57
58#ifndef __ARCH_X86_PAGETABLE_HH__
59#define __ARCH_X86_PAGETABLE_HH__
60
61#include <iostream>
62#include <string>
63
64#include "base/bitunion.hh"
65#include "base/misc.hh"
66#include "base/types.hh"
67
68class Checkpoint;
69
70namespace X86ISA
71{
72 BitUnion64(VAddr)
73 Bitfield<20, 12> longl1;
74 Bitfield<29, 21> longl2;
75 Bitfield<38, 30> longl3;
76 Bitfield<47, 39> longl4;
77
78 Bitfield<20, 12> pael1;
79 Bitfield<29, 21> pael2;
80 Bitfield<31, 30> pael3;
81
82 Bitfield<21, 12> norml1;
83 Bitfield<31, 22> norml2;
84 EndBitUnion(VAddr)
85
86 struct TlbEntry
87 {
88 // The base of the physical page.
89 Addr paddr;
90
91 // The beginning of the virtual page this entry maps.
92 Addr vaddr;
93 // The size of the page this entry represents.
94 Addr size;
95
96 // Read permission is always available, assuming it isn't blocked by
97 // other mechanisms.
98 bool writable;
99 // Whether this page is accesible without being in supervisor mode.
100 bool user;
101 // Whether to use write through or write back. M5 ignores this and
102 // lets the caches handle the writeback policy.
103 //bool pwt;
104 // Whether the page is cacheable or not.
105 bool uncacheable;
106 // Whether or not to kick this page out on a write to CR3.
107 bool global;
108 // A bit used to form an index into the PAT table.
109 bool patBit;
110 // Whether or not memory on this page can be executed.
111 bool noExec;
112
113 TlbEntry(Addr asn, Addr _vaddr, Addr _paddr);
114 TlbEntry() {}
115
116 void
117 updateVaddr(Addr new_vaddr)
118 {
119 vaddr = new_vaddr;
120 }
121
122 Addr pageStart()
123 {
124 return paddr;
125 }
126
127 void serialize(std::ostream &os);
128 void unserialize(Checkpoint *cp, const std::string §ion);
129 };
130}
131
132#endif
| 24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 */
39
40#ifndef __ARCH_X86_PAGETABLE_HH__
41#define __ARCH_X86_PAGETABLE_HH__
42
43#include <iostream>
44#include <string>
45
46#include "base/bitunion.hh"
47#include "base/misc.hh"
48#include "base/types.hh"
49
50class Checkpoint;
51
52namespace X86ISA
53{
54 BitUnion64(VAddr)
55 Bitfield<20, 12> longl1;
56 Bitfield<29, 21> longl2;
57 Bitfield<38, 30> longl3;
58 Bitfield<47, 39> longl4;
59
60 Bitfield<20, 12> pael1;
61 Bitfield<29, 21> pael2;
62 Bitfield<31, 30> pael3;
63
64 Bitfield<21, 12> norml1;
65 Bitfield<31, 22> norml2;
66 EndBitUnion(VAddr)
67
68 struct TlbEntry
69 {
70 // The base of the physical page.
71 Addr paddr;
72
73 // The beginning of the virtual page this entry maps.
74 Addr vaddr;
75 // The size of the page this entry represents.
76 Addr size;
77
78 // Read permission is always available, assuming it isn't blocked by
79 // other mechanisms.
80 bool writable;
81 // Whether this page is accesible without being in supervisor mode.
82 bool user;
83 // Whether to use write through or write back. M5 ignores this and
84 // lets the caches handle the writeback policy.
85 //bool pwt;
86 // Whether the page is cacheable or not.
87 bool uncacheable;
88 // Whether or not to kick this page out on a write to CR3.
89 bool global;
90 // A bit used to form an index into the PAT table.
91 bool patBit;
92 // Whether or not memory on this page can be executed.
93 bool noExec;
94
95 TlbEntry(Addr asn, Addr _vaddr, Addr _paddr);
96 TlbEntry() {}
97
98 void
99 updateVaddr(Addr new_vaddr)
100 {
101 vaddr = new_vaddr;
102 }
103
104 Addr pageStart()
105 {
106 return paddr;
107 }
108
109 void serialize(std::ostream &os);
110 void unserialize(Checkpoint *cp, const std::string §ion);
111 };
112}
113
114#endif
|