1/* 2 * Copyright (c) 2011 Google 3 * Copyright (c) 2015 Advanced Micro Devices, Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright --- 21 unchanged lines hidden (view full) --- 30 */ 31 32#ifndef __ARCH_X86_MEMHELPERS_HH__ 33#define __ARCH_X86_MEMHELPERS_HH__ 34 35#include <array> 36 37#include "base/types.hh" |
38#include "cpu/exec_context.hh" |
39#include "sim/byteswap.hh" 40#include "sim/insttracer.hh" 41 42namespace X86ISA 43{ 44 45/// Initiate a read from memory in timing mode. |
46static Fault 47initiateMemRead(ExecContext *xc, Trace::InstRecord *traceData, Addr addr, |
48 unsigned dataSize, Request::Flags flags) 49{ 50 return xc->initiateMemRead(addr, dataSize, flags); 51} 52 53static void 54getMem(PacketPtr pkt, uint64_t &mem, unsigned dataSize, 55 Trace::InstRecord *traceData) --- 36 unchanged lines hidden (view full) --- 92 93 // traceData record only has space for 64 bits, so we just record 94 // the first qword 95 if (traceData) 96 traceData->setData(mem[0]); 97} 98 99 |
100static Fault 101readMemAtomic(ExecContext *xc, Trace::InstRecord *traceData, Addr addr, 102 uint64_t &mem, unsigned dataSize, Request::Flags flags) |
103{ 104 memset(&mem, 0, sizeof(mem)); 105 Fault fault = xc->readMem(addr, (uint8_t *)&mem, dataSize, flags); 106 if (fault == NoFault) { 107 // If LE to LE, this is a nop, if LE to BE, the actual data ends up 108 // in the right place because the LSBs where at the low addresses on 109 // access. This doesn't work for BE guests. 110 mem = gtoh(mem); 111 if (traceData) 112 traceData->setData(mem); 113 } 114 return fault; 115} 116 |
117template |
118Fault |
119readMemAtomic(ExecContext *xc, Trace::InstRecord *traceData, Addr addr, |
120 std::array<uint64_t, N> &mem, unsigned dataSize, 121 unsigned flags) 122{ 123 assert(dataSize >= 8); 124 assert((dataSize % 8) == 0); 125 126 Fault fault = xc->readMem(addr, (uint8_t *)&mem, dataSize, flags); 127 --- 5 unchanged lines hidden (view full) --- 133 mem[i] = gtoh(mem[i]); 134 135 if (traceData) 136 traceData->setData(mem[0]); 137 } 138 return fault; 139} 140 |
141static Fault 142writeMemTiming(ExecContext *xc, Trace::InstRecord *traceData, uint64_t mem, |
143 unsigned dataSize, Addr addr, Request::Flags flags, 144 uint64_t *res) 145{ 146 if (traceData) { 147 traceData->setData(mem); 148 } 149 mem = TheISA::htog(mem); 150 return xc->writeMem((uint8_t *)&mem, dataSize, addr, flags, res); 151} 152 |
153template |
154Fault |
155writeMemTiming(ExecContext *xc, Trace::InstRecord *traceData, |
156 std::array<uint64_t, N> &mem, unsigned dataSize, 157 Addr addr, unsigned flags, uint64_t *res) 158{ 159 assert(dataSize >= 8); 160 assert((dataSize % 8) == 0); 161 162 if (traceData) { 163 traceData->setData(mem[0]); 164 } 165 166 int num_words = dataSize / 8; 167 assert(num_words <= N); 168 169 for (int i = 0; i < num_words; ++i) 170 mem[i] = htog(mem[i]); 171 172 return xc->writeMem((uint8_t *)&mem, dataSize, addr, flags, res); 173} 174 |
175static Fault 176writeMemAtomic(ExecContext *xc, Trace::InstRecord *traceData, uint64_t mem, |
177 unsigned dataSize, Addr addr, Request::Flags flags, 178 uint64_t *res) 179{ 180 if (traceData) { 181 traceData->setData(mem); 182 } 183 uint64_t host_mem = TheISA::htog(mem); 184 Fault fault = 185 xc->writeMem((uint8_t *)&host_mem, dataSize, addr, flags, res); 186 if (fault == NoFault && res != NULL) { 187 *res = gtoh(*res); 188 } 189 return fault; 190} 191 |
192template |
193Fault |
194writeMemAtomic(ExecContext *xc, Trace::InstRecord *traceData, |
195 std::array<uint64_t, N> &mem, unsigned dataSize, 196 Addr addr, unsigned flags, uint64_t *res) 197{ 198 if (traceData) { 199 traceData->setData(mem[0]); 200 } 201 202 int num_words = dataSize / 8; --- 17 unchanged lines hidden --- |