isa_traits.hh (5152:20fc3ce35147) | isa_traits.hh (5228:b08c9c42907a) |
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1/* 2 * Copyright (c) 2007 The Hewlett-Packard Development Company 3 * All rights reserved. 4 * 5 * Redistribution and use of this software in source and binary forms, 6 * with or without modification, are permitted provided that the 7 * following conditions are met: 8 * --- 45 unchanged lines hidden (view full) --- 54 * 55 * Authors: Gabe Black 56 */ 57 58#ifndef __ARCH_X86_ISATRAITS_HH__ 59#define __ARCH_X86_ISATRAITS_HH__ 60 61#include "arch/x86/intregs.hh" | 1/* 2 * Copyright (c) 2007 The Hewlett-Packard Development Company 3 * All rights reserved. 4 * 5 * Redistribution and use of this software in source and binary forms, 6 * with or without modification, are permitted provided that the 7 * following conditions are met: 8 * --- 45 unchanged lines hidden (view full) --- 54 * 55 * Authors: Gabe Black 56 */ 57 58#ifndef __ARCH_X86_ISATRAITS_HH__ 59#define __ARCH_X86_ISATRAITS_HH__ 60 61#include "arch/x86/intregs.hh" |
62#include "arch/x86/max_inst_regs.hh" |
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62#include "arch/x86/types.hh" 63#include "arch/x86/x86_traits.hh" 64#include "sim/host.hh" 65 66class StaticInstPtr; 67 68namespace LittleEndianGuest {} 69 70namespace X86ISA 71{ 72 //This makes sure the little endian version of certain functions 73 //are used. 74 using namespace LittleEndianGuest; | 63#include "arch/x86/types.hh" 64#include "arch/x86/x86_traits.hh" 65#include "sim/host.hh" 66 67class StaticInstPtr; 68 69namespace LittleEndianGuest {} 70 71namespace X86ISA 72{ 73 //This makes sure the little endian version of certain functions 74 //are used. 75 using namespace LittleEndianGuest; |
76 using X86ISAInst::MaxInstSrcRegs; 77 using X86ISAInst::MaxInstDestRegs; |
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75 76 // X86 does not have a delay slot 77#define ISA_HAS_DELAY_SLOT 0 78 79 // X86 NOP (XCHG rAX, rAX) 80 //XXX This needs to be set to an intermediate instruction struct 81 //which encodes this instruction 82 --- 33 unchanged lines hidden (view full) --- 116 INTREG_R9W 117 }; 118 const int NumArgumentRegs = sizeof(ArgumentReg) / sizeof(const int); 119 120 // Some OS syscalls use a second register (rdx) to return a second 121 // value 122 const int SyscallPseudoReturnReg = INTREG_RDX; 123 | 78 79 // X86 does not have a delay slot 80#define ISA_HAS_DELAY_SLOT 0 81 82 // X86 NOP (XCHG rAX, rAX) 83 //XXX This needs to be set to an intermediate instruction struct 84 //which encodes this instruction 85 --- 33 unchanged lines hidden (view full) --- 119 INTREG_R9W 120 }; 121 const int NumArgumentRegs = sizeof(ArgumentReg) / sizeof(const int); 122 123 // Some OS syscalls use a second register (rdx) to return a second 124 // value 125 const int SyscallPseudoReturnReg = INTREG_RDX; 126 |
124 //XXX These numbers are bogus 125 const int MaxInstSrcRegs = 10; 126 const int MaxInstDestRegs = 10; 127 | |
128 //4k. This value is not constant on x86. 129 const int LogVMPageSize = 12; 130 const int VMPageSize = (1 << LogVMPageSize); 131 132 const int PageShift = 12; 133 const int PageBytes = 1ULL << PageShift; 134 135 const int BranchPredAddrShiftAmt = 0; 136 137 StaticInstPtr decodeInst(ExtMachInst); 138 139 const Addr LoadAddrMask = ULL(-1); 140}; 141 142#endif // __ARCH_X86_ISATRAITS_HH__ | 127 //4k. This value is not constant on x86. 128 const int LogVMPageSize = 12; 129 const int VMPageSize = (1 << LogVMPageSize); 130 131 const int PageShift = 12; 132 const int PageBytes = 1ULL << PageShift; 133 134 const int BranchPredAddrShiftAmt = 0; 135 136 StaticInstPtr decodeInst(ExtMachInst); 137 138 const Addr LoadAddrMask = ULL(-1); 139}; 140 141#endif // __ARCH_X86_ISATRAITS_HH__ |