isa_traits.hh (4141:80c20b40a01f) | isa_traits.hh (4166:ecebe3ac19b4) |
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1/* 2 * Copyright (c) 2007 The Hewlett-Packard Development Company 3 * All rights reserved. 4 * 5 * Redistribution and use of this software in source and binary forms, 6 * with or without modification, are permitted provided that the 7 * following conditions are met: 8 * --- 44 unchanged lines hidden (view full) --- 53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 54 * 55 * Authors: Gabe Black 56 */ 57 58#ifndef __ARCH_X86_ISATRAITS_HH__ 59#define __ARCH_X86_ISATRAITS_HH__ 60 | 1/* 2 * Copyright (c) 2007 The Hewlett-Packard Development Company 3 * All rights reserved. 4 * 5 * Redistribution and use of this software in source and binary forms, 6 * with or without modification, are permitted provided that the 7 * following conditions are met: 8 * --- 44 unchanged lines hidden (view full) --- 53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 54 * 55 * Authors: Gabe Black 56 */ 57 58#ifndef __ARCH_X86_ISATRAITS_HH__ 59#define __ARCH_X86_ISATRAITS_HH__ 60 |
61#include "arch/x86/intregs.hh" |
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61#include "arch/x86/types.hh" 62#include "arch/x86/x86_traits.hh" 63 64class StaticInstPtr; 65 66namespace LittleEndianGuest {} 67 68namespace X86ISA --- 19 unchanged lines hidden (view full) --- 88 8 + 89 //xmm registers 90 16 91 }; 92 93 // semantically meaningful register indices 94 //There is no such register in X86 95 const int ZeroReg = 0; | 62#include "arch/x86/types.hh" 63#include "arch/x86/x86_traits.hh" 64 65class StaticInstPtr; 66 67namespace LittleEndianGuest {} 68 69namespace X86ISA --- 19 unchanged lines hidden (view full) --- 89 8 + 90 //xmm registers 91 16 92 }; 93 94 // semantically meaningful register indices 95 //There is no such register in X86 96 const int ZeroReg = 0; |
96 const int StackPointerReg = 4; //RSP | 97 const int StackPointerReg = INTREG_RSP; |
97 //X86 doesn't seem to have a link register 98 const int ReturnAddressReg = 0; | 98 //X86 doesn't seem to have a link register 99 const int ReturnAddressReg = 0; |
99 const int ReturnValueReg = 0; //RAX 100 const int FramePointerReg = 5; //RBP 101 const int ArgumentReg0 = 7; //RDI 102 const int ArgumentReg1 = 6; //RSI 103 const int ArgumentReg2 = 2; //RDX 104 const int ArgumentReg3 = 1; //RCX 105 const int ArgumentReg4 = 8; //R8W 106 const int ArgumentReg5 = 9; //R9W | 100 const int ReturnValueReg = INTREG_RAX; 101 const int FramePointerReg = INTREG_RBP; 102 const int ArgumentReg0 = INTREG_RDI; 103 const int ArgumentReg1 = INTREG_RSI; 104 const int ArgumentReg2 = INTREG_RDX; 105 const int ArgumentReg3 = INTREG_RCX; 106 const int ArgumentReg4 = INTREG_R8W; 107 const int ArgumentReg5 = INTREG_R9W; |
107 108 // Some OS syscalls use a second register (rdx) to return a second 109 // value | 108 109 // Some OS syscalls use a second register (rdx) to return a second 110 // value |
110 const int SyscallPseudoReturnReg = 2; //RDX | 111 const int SyscallPseudoReturnReg = INTREG_RDX; |
111 112 //XXX These numbers are bogus 113 const int MaxInstSrcRegs = 10; 114 const int MaxInstDestRegs = 10; 115 116 //4k. This value is not constant on x86. 117 const int LogVMPageSize = 12; 118 const int VMPageSize = (1 << LogVMPageSize); 119 120 const int PageShift = 13; 121 const int PageBytes = 1ULL << PageShift; 122 123 const int BranchPredAddrShiftAmt = 0; 124 125 StaticInstPtr decodeInst(ExtMachInst); 126}; 127 128#endif // __ARCH_X86_ISATRAITS_HH__ | 112 113 //XXX These numbers are bogus 114 const int MaxInstSrcRegs = 10; 115 const int MaxInstDestRegs = 10; 116 117 //4k. This value is not constant on x86. 118 const int LogVMPageSize = 12; 119 const int VMPageSize = (1 << LogVMPageSize); 120 121 const int PageShift = 13; 122 const int PageBytes = 1ULL << PageShift; 123 124 const int BranchPredAddrShiftAmt = 0; 125 126 StaticInstPtr decodeInst(ExtMachInst); 127}; 128 129#endif // __ARCH_X86_ISATRAITS_HH__ |