operands.isa (9582:0632d2d1575c) operands.isa (9921:ee049bfce978)
1// Copyright (c) 2007-2008 The Hewlett-Packard Development Company
2// All rights reserved.
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license
9// terms below provided that you ensure that this notice is replicated
10// unmodified and in its entirety in all distributions of the software,
11// modified or unmodified, in source code or in binary form.
12//
13// Copyright (c) 2007 The Regents of The University of Michigan
1// Copyright (c) 2007-2008 The Hewlett-Packard Development Company
2// All rights reserved.
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license
9// terms below provided that you ensure that this notice is replicated
10// unmodified and in its entirety in all distributions of the software,
11// modified or unmodified, in source code or in binary form.
12//
13// Copyright (c) 2007 The Regents of The University of Michigan
14// Copyright (c) 2012 Mark D. Hill and David A. Wood
15// Copyright (c) 2012-2013 Advanced Micro Devices, Inc.
14// All rights reserved.
15//
16// Redistribution and use in source and binary forms, with or without
17// modification, are permitted provided that the following conditions are
18// met: redistributions of source code must retain the above copyright
19// notice, this list of conditions and the following disclaimer;
20// redistributions in binary form must reproduce the above copyright
21// notice, this list of conditions and the following disclaimer in the

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56 return ('IntReg', 'uqw', 'INTREG_FOLDED(%s, %s)' % (idx, foldBit),
57 'IsInteger', id)
58 def intReg(idx, id):
59 return ('IntReg', 'uqw', idx, 'IsInteger', id)
60 def impIntReg(idx, id):
61 return ('IntReg', 'uqw', 'INTREG_IMPLICIT(%s)' % idx, 'IsInteger', id)
62 def floatReg(idx, id):
63 return ('FloatReg', 'df', idx, 'IsFloating', id)
16// All rights reserved.
17//
18// Redistribution and use in source and binary forms, with or without
19// modification, are permitted provided that the following conditions are
20// met: redistributions of source code must retain the above copyright
21// notice, this list of conditions and the following disclaimer;
22// redistributions in binary form must reproduce the above copyright
23// notice, this list of conditions and the following disclaimer in the

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58 return ('IntReg', 'uqw', 'INTREG_FOLDED(%s, %s)' % (idx, foldBit),
59 'IsInteger', id)
60 def intReg(idx, id):
61 return ('IntReg', 'uqw', idx, 'IsInteger', id)
62 def impIntReg(idx, id):
63 return ('IntReg', 'uqw', 'INTREG_IMPLICIT(%s)' % idx, 'IsInteger', id)
64 def floatReg(idx, id):
65 return ('FloatReg', 'df', idx, 'IsFloating', id)
66 def ccReg(idx, id):
67 return ('CCReg', 'uqw', idx, 'IsCC', id)
64 def controlReg(idx, id, ctype = 'uqw'):
65 return ('ControlReg', ctype, idx,
66 (None, None, ['IsSerializeAfter',
67 'IsSerializing',
68 'IsNonSpeculative']),
69 id)
70 def squashCheckReg(idx, id, check, ctype = 'uqw'):
71 return ('ControlReg', ctype, idx,

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113 'RIP': ('PCState', 'uqw', 'pc',
114 (None, None, 'IsControl'), 50),
115 'NRIP': ('PCState', 'uqw', 'npc',
116 (None, None, 'IsControl'), 50),
117 'nuIP': ('PCState', 'uqw', 'nupc',
118 (None, None, 'IsControl'), 50),
119 # These registers hold the condition code portion of the flag
120 # register. The nccFlagBits version holds the rest.
68 def controlReg(idx, id, ctype = 'uqw'):
69 return ('ControlReg', ctype, idx,
70 (None, None, ['IsSerializeAfter',
71 'IsSerializing',
72 'IsNonSpeculative']),
73 id)
74 def squashCheckReg(idx, id, check, ctype = 'uqw'):
75 return ('ControlReg', ctype, idx,

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117 'RIP': ('PCState', 'uqw', 'pc',
118 (None, None, 'IsControl'), 50),
119 'NRIP': ('PCState', 'uqw', 'npc',
120 (None, None, 'IsControl'), 50),
121 'nuIP': ('PCState', 'uqw', 'nupc',
122 (None, None, 'IsControl'), 50),
123 # These registers hold the condition code portion of the flag
124 # register. The nccFlagBits version holds the rest.
121 'ccFlagBits': intReg('INTREG_PSEUDO(0)', 60),
122 'cfofBits': intReg('INTREG_PSEUDO(1)', 61),
123 'dfBit': intReg('INTREG_PSEUDO(2)', 62),
124 'ecfBit': intReg('INTREG_PSEUDO(3)', 63),
125 'ezfBit': intReg('INTREG_PSEUDO(4)', 64),
125 'ccFlagBits': ccReg('(CCREG_ZAPS)', 60),
126 'cfofBits': ccReg('(CCREG_CFOF)', 61),
127 'dfBit': ccReg('(CCREG_DF)', 62),
128 'ecfBit': ccReg('(CCREG_ECF)', 63),
129 'ezfBit': ccReg('(CCREG_EZF)', 64),
126
127 # These Pred registers are to be used where reading the portions of
128 # condition code registers is possibly optional, depending on how the
129 # check evaluates. There are two checks being specified, one tests if
130 # a register needs to be read, the other tests whether the register
131 # needs to be written to. It is unlikely that these would need to be
132 # used in the actual operation of the instruction. It is expected
133 # that these are used only in the flag code.
134
135 # Rationale behind the checks: at times, we need to partially update
136 # the condition code bits in a register. So we read the register even
137 # in the case when the all the bits will be written, or none of the
138 # bits will be written. The read predicate checks if any of the bits
139 # would be retained, the write predicate checks if any of the bits
140 # are being written.
141
130
131 # These Pred registers are to be used where reading the portions of
132 # condition code registers is possibly optional, depending on how the
133 # check evaluates. There are two checks being specified, one tests if
134 # a register needs to be read, the other tests whether the register
135 # needs to be written to. It is unlikely that these would need to be
136 # used in the actual operation of the instruction. It is expected
137 # that these are used only in the flag code.
138
139 # Rationale behind the checks: at times, we need to partially update
140 # the condition code bits in a register. So we read the register even
141 # in the case when the all the bits will be written, or none of the
142 # bits will be written. The read predicate checks if any of the bits
143 # would be retained, the write predicate checks if any of the bits
144 # are being written.
145
142 'PredccFlagBits': ('IntReg', 'uqw', 'INTREG_PSEUDO(0)', 'IsInteger',
146 'PredccFlagBits': ('CCReg', 'uqw', '(CCREG_ZAPS)', 'IsCC',
143 60, None, None, '''(((ext & (PFBit | AFBit | ZFBit | SFBit
144 )) != (PFBit | AFBit | ZFBit | SFBit )) &&
145 ((ext & (PFBit | AFBit | ZFBit | SFBit )) != 0))''',
146 '((ext & (PFBit | AFBit | ZFBit | SFBit )) != 0)'),
147 60, None, None, '''(((ext & (PFBit | AFBit | ZFBit | SFBit
148 )) != (PFBit | AFBit | ZFBit | SFBit )) &&
149 ((ext & (PFBit | AFBit | ZFBit | SFBit )) != 0))''',
150 '((ext & (PFBit | AFBit | ZFBit | SFBit )) != 0)'),
147 'PredcfofBits': ('IntReg', 'uqw', 'INTREG_PSEUDO(1)', 'IsInteger',
151 'PredcfofBits': ('CCReg', 'uqw', '(CCREG_CFOF)', 'IsCC',
148 61, None, None, '''(((ext & CFBit) == 0 ||
149 (ext & OFBit) == 0) && ((ext & (CFBit | OFBit)) != 0))''',
150 '((ext & (CFBit | OFBit)) != 0)'),
152 61, None, None, '''(((ext & CFBit) == 0 ||
153 (ext & OFBit) == 0) && ((ext & (CFBit | OFBit)) != 0))''',
154 '((ext & (CFBit | OFBit)) != 0)'),
151 'PreddfBit': ('IntReg', 'uqw', 'INTREG_PSEUDO(2)', 'IsInteger',
155 'PreddfBit': ('CCReg', 'uqw', '(CCREG_DF)', 'IsCC',
152 62, None, None, '(false)', '((ext & DFBit) != 0)'),
156 62, None, None, '(false)', '((ext & DFBit) != 0)'),
153 'PredecfBit': ('IntReg', 'uqw', 'INTREG_PSEUDO(3)', 'IsInteger',
157 'PredecfBit': ('CCReg', 'uqw', '(CCREG_ECF)', 'IsCC',
154 63, None, None, '(false)', '((ext & ECFBit) != 0)'),
158 63, None, None, '(false)', '((ext & ECFBit) != 0)'),
155 'PredezfBit': ('IntReg', 'uqw', 'INTREG_PSEUDO(4)', 'IsInteger',
159 'PredezfBit': ('CCReg', 'uqw', '(CCREG_EZF)', 'IsCC',
156 64, None, None, '(false)', '((ext & EZFBit) != 0)'),
157
158 # These register should needs to be more protected so that later
159 # instructions don't map their indexes with an old value.
160 'nccFlagBits': controlReg('MISCREG_RFLAGS', 65),
161
162 # Registers related to the state of x87 floating point unit.
163 'TOP': controlReg('MISCREG_X87_TOP', 66, ctype='ub'),

--- 40 unchanged lines hidden --- 		160 64, None, None, '(false)', '((ext & EZFBit) != 0)'),
161
162 # These register should needs to be more protected so that later
163 # instructions don't map their indexes with an old value.
164 'nccFlagBits': controlReg('MISCREG_RFLAGS', 65),
165
166 # Registers related to the state of x87 floating point unit.
167 'TOP': controlReg('MISCREG_X87_TOP', 66, ctype='ub'),

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