operands.isa (9211:46c3a74952ec) operands.isa (9212:dc386ccc1db9)
1// Copyright (c) 2007-2008 The Hewlett-Packard Development Company
2// All rights reserved.
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license

--- 102 unchanged lines hidden (view full) ---

111 'FpDestReg': floatReg('dest', 22),
112 'FpData': floatReg('data', 23),
113 'RIP': ('PCState', 'uqw', 'pc',
114 (None, None, 'IsControl'), 50),
115 'NRIP': ('PCState', 'uqw', 'npc',
116 (None, None, 'IsControl'), 50),
117 'nuIP': ('PCState', 'uqw', 'nupc',
118 (None, None, 'IsControl'), 50),
1// Copyright (c) 2007-2008 The Hewlett-Packard Development Company
2// All rights reserved.
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license

--- 102 unchanged lines hidden (view full) ---

111 'FpDestReg': floatReg('dest', 22),
112 'FpData': floatReg('data', 23),
113 'RIP': ('PCState', 'uqw', 'pc',
114 (None, None, 'IsControl'), 50),
115 'NRIP': ('PCState', 'uqw', 'npc',
116 (None, None, 'IsControl'), 50),
117 'nuIP': ('PCState', 'uqw', 'nupc',
118 (None, None, 'IsControl'), 50),
119 # This holds the condition code portion of the flag register. The
120 # nccFlagBits version holds the rest.
119 # These registers hold the condition code portion of the flag
120 # register. The nccFlagBits version holds the rest.
121 'ccFlagBits': intReg('INTREG_PSEUDO(0)', 60),
122 'cfofBits': intReg('INTREG_PSEUDO(1)', 61),
123 'dfBit': intReg('INTREG_PSEUDO(2)', 62),
124 'ecfBit': intReg('INTREG_PSEUDO(3)', 63),
125 'ezfBit': intReg('INTREG_PSEUDO(4)', 64),
121 'ccFlagBits': intReg('INTREG_PSEUDO(0)', 60),
122 'cfofBits': intReg('INTREG_PSEUDO(1)', 61),
123 'dfBit': intReg('INTREG_PSEUDO(2)', 62),
124 'ecfBit': intReg('INTREG_PSEUDO(3)', 63),
125 'ezfBit': intReg('INTREG_PSEUDO(4)', 64),
126
127 # These Pred registers are to be used where reading the portions of
128 # condition code registers is possibly optional, depending on how the
129 # check evaluates. There are two checks being specified, one tests if
130 # a register needs to be read, the other tests whether the register
131 # needs to be written to. It is unlikely that these would need to be
132 # used in the actual operation of the instruction. It is expected
133 # that these are used only in the flag code.
134
135 # Rationale behind the checks: at times, we need to partially update
136 # the condition code bits in a register. So we read the register even
137 # in the case when the all the bits will be written, or none of the
138 # bits will be written. The read predicate checks if any of the bits
139 # would be retained, the write predicate checks if any of the bits
140 # are being written.
141
142 'PredccFlagBits': ('IntReg', 'uqw', 'INTREG_PSEUDO(0)', 'IsInteger',
143 60, None, None, '''(((ext & (PFBit | AFBit | ZFBit | SFBit
144 )) != (PFBit | AFBit | ZFBit | SFBit )) &&
145 ((ext & (PFBit | AFBit | ZFBit | SFBit )) != 0))''',
146 '((ext & (PFBit | AFBit | ZFBit | SFBit )) != 0)'),
147 'PredcfofBits': ('IntReg', 'uqw', 'INTREG_PSEUDO(1)', 'IsInteger',
148 61, None, None, '''(((ext & CFBit) == 0 ||
149 (ext & OFBit) == 0) && ((ext & (CFBit | OFBit)) != 0))''',
150 '((ext & (CFBit | OFBit)) != 0)'),
151 'PreddfBit': ('IntReg', 'uqw', 'INTREG_PSEUDO(2)', 'IsInteger',
152 62, None, None, '(false)', '((ext & DFBit) != 0)'),
153 'PredecfBit': ('IntReg', 'uqw', 'INTREG_PSEUDO(3)', 'IsInteger',
154 63, None, None, '(false)', '((ext & ECFBit) != 0)'),
155 'PredezfBit': ('IntReg', 'uqw', 'INTREG_PSEUDO(4)', 'IsInteger',
156 64, None, None, '(false)', '((ext & EZFBit) != 0)'),
157
126 # These register should needs to be more protected so that later
127 # instructions don't map their indexes with an old value.
128 'nccFlagBits': controlReg('MISCREG_RFLAGS', 65),
129 'TOP': controlReg('MISCREG_X87_TOP', 66, ctype='ub'),
130 # The segment base as used by memory instructions.
131 'SegBase': controlReg('MISCREG_SEG_EFF_BASE(segment)', 70),
132
133 # Operands to get and set registers indexed by the operands of the

--- 32 unchanged lines hidden --- 		158 # These register should needs to be more protected so that later
159 # instructions don't map their indexes with an old value.
160 'nccFlagBits': controlReg('MISCREG_RFLAGS', 65),
161 'TOP': controlReg('MISCREG_X87_TOP', 66, ctype='ub'),
162 # The segment base as used by memory instructions.
163 'SegBase': controlReg('MISCREG_SEG_EFF_BASE(segment)', 70),
164
165 # Operands to get and set registers indexed by the operands of the

--- 32 unchanged lines hidden ---