| operands.isa (8449:4be49ad47c74) | operands.isa (8500:5bae9eee9482) |
|---|---|
| 1// Copyright (c) 2007-2008 The Hewlett-Packard Development Company 2// All rights reserved. 3// 4// The license below extends only to copyright in the software and shall 5// not be construed as granting a license to any other intellectual 6// property including but not limited to intellectual property relating 7// to a hardware implementation of the functionality of the software 8// licensed hereunder. You may use the software subject to the license --- 53 unchanged lines hidden (view full) --- 62 def floatReg(idx, id): 63 return ('FloatReg', 'df', idx, 'IsFloating', id) 64 def controlReg(idx, id, ctype = 'uqw'): 65 return ('ControlReg', ctype, idx, 66 (None, None, ['IsSerializeAfter', 67 'IsSerializing', 68 'IsNonSpeculative']), 69 id) | 1// Copyright (c) 2007-2008 The Hewlett-Packard Development Company 2// All rights reserved. 3// 4// The license below extends only to copyright in the software and shall 5// not be construed as granting a license to any other intellectual 6// property including but not limited to intellectual property relating 7// to a hardware implementation of the functionality of the software 8// licensed hereunder. You may use the software subject to the license --- 53 unchanged lines hidden (view full) --- 62 def floatReg(idx, id): 63 return ('FloatReg', 'df', idx, 'IsFloating', id) 64 def controlReg(idx, id, ctype = 'uqw'): 65 return ('ControlReg', ctype, idx, 66 (None, None, ['IsSerializeAfter', 67 'IsSerializing', 68 'IsNonSpeculative']), 69 id) |
| 70 def squashCheckReg(idx, id, check, ctype = 'uqw'): 71 return ('ControlReg', ctype, idx, 72 (None, None, ['((%s) ? ' % check+ \ 73 'IsSquashAfter : IsSerializeAfter)', 74 'IsSerializing', 75 'IsNonSpeculative']), 76 id) 77 def squashCReg(idx, id, ctype = 'uqw'): 78 return squashCheckReg(idx, id, 'true', ctype) 79 def squashCSReg(idx, id, ctype = 'uqw'): 80 return squashCheckReg(idx, id, 'dest == SEGMENT_REG_CS', ctype) 81 def squashCR0Reg(idx, id, ctype = 'uqw'): 82 return squashCheckReg(idx, id, 'dest == 0', ctype) |
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| 70}}; 71 72def operands {{ 73 'SrcReg1': foldInt('src1', 'foldOBit', 1), 74 'SSrcReg1': intReg('src1', 1), 75 'SrcReg2': foldInt('src2', 'foldOBit', 2), 76 'SSrcReg2': intReg('src2', 1), 77 'Index': foldInt('index', 'foldABit', 3), --- 32 unchanged lines hidden (view full) --- 110 # instructions don't map their indexes with an old value. 111 'nccFlagBits': controlReg('MISCREG_RFLAGS', 61), 112 'TOP': controlReg('MISCREG_X87_TOP', 62, ctype='ub'), 113 # The segment base as used by memory instructions. 114 'SegBase': controlReg('MISCREG_SEG_EFF_BASE(segment)', 70), 115 116 # Operands to get and set registers indexed by the operands of the 117 # original instruction. | 83}}; 84 85def operands {{ 86 'SrcReg1': foldInt('src1', 'foldOBit', 1), 87 'SSrcReg1': intReg('src1', 1), 88 'SrcReg2': foldInt('src2', 'foldOBit', 2), 89 'SSrcReg2': intReg('src2', 1), 90 'Index': foldInt('index', 'foldABit', 3), --- 32 unchanged lines hidden (view full) --- 123 # instructions don't map their indexes with an old value. 124 'nccFlagBits': controlReg('MISCREG_RFLAGS', 61), 125 'TOP': controlReg('MISCREG_X87_TOP', 62, ctype='ub'), 126 # The segment base as used by memory instructions. 127 'SegBase': controlReg('MISCREG_SEG_EFF_BASE(segment)', 70), 128 129 # Operands to get and set registers indexed by the operands of the 130 # original instruction. |
| 118 'ControlDest': controlReg('MISCREG_CR(dest)', 100), | 131 'ControlDest': squashCR0Reg('MISCREG_CR(dest)', 100), |
| 119 'ControlSrc1': controlReg('MISCREG_CR(src1)', 101), 120 'DebugDest': controlReg('MISCREG_DR(dest)', 102), 121 'DebugSrc1': controlReg('MISCREG_DR(src1)', 103), | 132 'ControlSrc1': controlReg('MISCREG_CR(src1)', 101), 133 'DebugDest': controlReg('MISCREG_DR(dest)', 102), 134 'DebugSrc1': controlReg('MISCREG_DR(src1)', 103), |
| 122 'SegBaseDest': controlReg('MISCREG_SEG_BASE(dest)', 104), | 135 'SegBaseDest': squashCSReg('MISCREG_SEG_BASE(dest)', 104), |
| 123 'SegBaseSrc1': controlReg('MISCREG_SEG_BASE(src1)', 105), | 136 'SegBaseSrc1': controlReg('MISCREG_SEG_BASE(src1)', 105), |
| 124 'SegLimitDest': controlReg('MISCREG_SEG_LIMIT(dest)', 106), | 137 'SegLimitDest': squashCSReg('MISCREG_SEG_LIMIT(dest)', 106), |
| 125 'SegLimitSrc1': controlReg('MISCREG_SEG_LIMIT(src1)', 107), 126 'SegSelDest': controlReg('MISCREG_SEG_SEL(dest)', 108), 127 'SegSelSrc1': controlReg('MISCREG_SEG_SEL(src1)', 109), | 138 'SegLimitSrc1': controlReg('MISCREG_SEG_LIMIT(src1)', 107), 139 'SegSelDest': controlReg('MISCREG_SEG_SEL(dest)', 108), 140 'SegSelSrc1': controlReg('MISCREG_SEG_SEL(src1)', 109), |
| 128 'SegAttrDest': controlReg('MISCREG_SEG_ATTR(dest)', 110), | 141 'SegAttrDest': squashCSReg('MISCREG_SEG_ATTR(dest)', 110), |
| 129 'SegAttrSrc1': controlReg('MISCREG_SEG_ATTR(src1)', 111), 130 131 # Operands to access specific control registers directly. | 142 'SegAttrSrc1': controlReg('MISCREG_SEG_ATTR(src1)', 111), 143 144 # Operands to access specific control registers directly. |
| 132 'EferOp': controlReg('MISCREG_EFER', 200), | 145 'EferOp': squashCReg('MISCREG_EFER', 200), |
| 133 'CR4Op': controlReg('MISCREG_CR4', 201), 134 'DR7Op': controlReg('MISCREG_DR7', 202), 135 'LDTRBase': controlReg('MISCREG_TSL_BASE', 203), 136 'LDTRLimit': controlReg('MISCREG_TSL_LIMIT', 204), 137 'LDTRSel': controlReg('MISCREG_TSL', 205), 138 'GDTRBase': controlReg('MISCREG_TSG_BASE', 206), 139 'GDTRLimit': controlReg('MISCREG_TSG_LIMIT', 207), | 146 'CR4Op': controlReg('MISCREG_CR4', 201), 147 'DR7Op': controlReg('MISCREG_DR7', 202), 148 'LDTRBase': controlReg('MISCREG_TSL_BASE', 203), 149 'LDTRLimit': controlReg('MISCREG_TSL_LIMIT', 204), 150 'LDTRSel': controlReg('MISCREG_TSL', 205), 151 'GDTRBase': controlReg('MISCREG_TSG_BASE', 206), 152 'GDTRLimit': controlReg('MISCREG_TSG_LIMIT', 207), |
| 140 'CSBase': controlReg('MISCREG_CS_EFF_BASE', 208), 141 'CSAttr': controlReg('MISCREG_CS_ATTR', 209), | 153 'CSBase': squashCReg('MISCREG_CS_EFF_BASE', 208), 154 'CSAttr': squashCReg('MISCREG_CS_ATTR', 209), |
| 142 'MiscRegDest': controlReg('dest', 210), 143 'MiscRegSrc1': controlReg('src1', 211), 144 'TscOp': controlReg('MISCREG_TSC', 212), | 155 'MiscRegDest': controlReg('dest', 210), 156 'MiscRegSrc1': controlReg('src1', 211), 157 'TscOp': controlReg('MISCREG_TSC', 212), |
| 145 'M5Reg': controlReg('MISCREG_M5_REG', 213), | 158 'M5Reg': squashCReg('MISCREG_M5_REG', 213), |
| 146 'Mem': ('Mem', 'uqw', None, \ 147 ('IsMemRef', 'IsLoad', 'IsStore'), 300) 148}}; | 159 'Mem': ('Mem', 'uqw', None, \ 160 ('IsMemRef', 'IsLoad', 'IsStore'), 300) 161}}; |