operands.isa (7720:65d338a8dba4) operands.isa (7789:f455790bcd47)
1// Copyright (c) 2007-2008 The Hewlett-Packard Development Company
2// All rights reserved.
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license

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92 'Rsp': intReg('(INTREG_RSP)', 16),
93 'Rbp': intReg('(INTREG_RBP)', 17),
94 'Rsi': intReg('(INTREG_RSI)', 18),
95 'Rdi': intReg('(INTREG_RDI)', 19),
96 'FpSrcReg1': floatReg('src1', 20),
97 'FpSrcReg2': floatReg('src2', 21),
98 'FpDestReg': floatReg('dest', 22),
99 'FpData': floatReg('data', 23),
1// Copyright (c) 2007-2008 The Hewlett-Packard Development Company
2// All rights reserved.
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license

--- 83 unchanged lines hidden (view full) ---

92 'Rsp': intReg('(INTREG_RSP)', 16),
93 'Rbp': intReg('(INTREG_RBP)', 17),
94 'Rsi': intReg('(INTREG_RSI)', 18),
95 'Rdi': intReg('(INTREG_RDI)', 19),
96 'FpSrcReg1': floatReg('src1', 20),
97 'FpSrcReg2': floatReg('src2', 21),
98 'FpDestReg': floatReg('dest', 22),
99 'FpData': floatReg('data', 23),
100 'PCS': ('PCState', 'udw', None,
100 'RIP': ('PCState', 'uqw', 'pc',
101 (None, None, 'IsControl'), 50),
101 (None, None, 'IsControl'), 50),
102 'NRIP': ('PCState', 'uqw', 'npc',
103 (None, None, 'IsControl'), 50),
104 'nuIP': ('PCState', 'uqw', 'nupc',
105 (None, None, 'IsControl'), 50),
102 # This holds the condition code portion of the flag register. The
103 # nccFlagBits version holds the rest.
104 'ccFlagBits': intReg('INTREG_PSEUDO(0)', 60),
105 # These register should needs to be more protected so that later
106 # instructions don't map their indexes with an old value.
107 'nccFlagBits': controlReg('MISCREG_RFLAGS', 61),
108 'TOP': controlReg('MISCREG_X87_TOP', 62, ctype='ub'),
109 # The segment base as used by memory instructions.

--- 35 unchanged lines hidden --- 		106 # This holds the condition code portion of the flag register. The
107 # nccFlagBits version holds the rest.
108 'ccFlagBits': intReg('INTREG_PSEUDO(0)', 60),
109 # These register should needs to be more protected so that later
110 # instructions don't map their indexes with an old value.
111 'nccFlagBits': controlReg('MISCREG_RFLAGS', 61),
112 'TOP': controlReg('MISCREG_X87_TOP', 62, ctype='ub'),
113 # The segment base as used by memory instructions.

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