| operands.isa (5926:c182698e1ab3) | operands.isa (6360:c3058964d06f) |
|---|---|
| 1// Copyright (c) 2007 The Regents of The University of Michigan 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: redistributions of source code must retain the above copyright 7// notice, this list of conditions and the following disclaimer; 8// redistributions in binary form must reproduce the above copyright --- 80 unchanged lines hidden (view full) --- 89 'sdw' : ('signed int', 32), 90 'udw' : ('unsigned int', 32), 91 'sqw' : ('signed int', 64), 92 'uqw' : ('unsigned int', 64), 93 'sf' : ('float', 32), 94 'df' : ('float', 64), 95}}; 96 | 1// Copyright (c) 2007 The Regents of The University of Michigan 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: redistributions of source code must retain the above copyright 7// notice, this list of conditions and the following disclaimer; 8// redistributions in binary form must reproduce the above copyright --- 80 unchanged lines hidden (view full) --- 89 'sdw' : ('signed int', 32), 90 'udw' : ('unsigned int', 32), 91 'sqw' : ('signed int', 64), 92 'uqw' : ('unsigned int', 64), 93 'sf' : ('float', 32), 94 'df' : ('float', 64), 95}}; 96 |
| 97let {{ 98 def foldInt(idx, foldBit, id): 99 return ('IntReg', 'uqw', 'INTREG_FOLDED(%s, %s)' % (idx, foldBit), 100 'IsInteger', id) 101 def intReg(idx, id): 102 return ('IntReg', 'uqw', idx, 'IsInteger', id) 103 def impIntReg(idx, id): 104 return ('IntReg', 'uqw', 'INTREG_IMPLICIT(%s)' % idx, 'IsInteger', id) 105 def floatReg(idx, id): 106 return ('FloatReg', 'df', idx, 'IsFloating', id) 107 def controlReg(idx, id, ctype = 'uqw'): 108 return ('ControlReg', ctype, idx, 109 (None, None, ['IsSerializeAfter', 110 'IsSerializing', 111 'IsNonSpeculative']), 112 id) 113}}; 114 |
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| 97def operands {{ | 115def operands {{ |
| 98 'SrcReg1': ('IntReg', 'uqw', 'INTREG_FOLDED(src1, foldOBit)', 'IsInteger', 1), 99 'SSrcReg1': ('IntReg', 'uqw', 'src1', 'IsInteger', 1), 100 'SrcReg2': ('IntReg', 'uqw', 'INTREG_FOLDED(src2, foldOBit)', 'IsInteger', 2), 101 'SSrcReg2': ('IntReg', 'uqw', 'src2', 'IsInteger', 1), 102 'Index': ('IntReg', 'uqw', 'INTREG_FOLDED(index, foldABit)', 'IsInteger', 3), 103 'Base': ('IntReg', 'uqw', 'INTREG_FOLDED(base, foldABit)', 'IsInteger', 4), 104 'DestReg': ('IntReg', 'uqw', 'INTREG_FOLDED(dest, foldOBit)', 'IsInteger', 5), 105 'SDestReg': ('IntReg', 'uqw', 'dest', 'IsInteger', 5), 106 'Data': ('IntReg', 'uqw', 'INTREG_FOLDED(data, foldOBit)', 'IsInteger', 6), 107 'ProdLow': ('IntReg', 'uqw', 'INTREG_IMPLICIT(0)', 'IsInteger', 7), 108 'ProdHi': ('IntReg', 'uqw', 'INTREG_IMPLICIT(1)', 'IsInteger', 8), 109 'Quotient': ('IntReg', 'uqw', 'INTREG_IMPLICIT(2)', 'IsInteger', 9), 110 'Remainder': ('IntReg', 'uqw', 'INTREG_IMPLICIT(3)', 'IsInteger', 10), 111 'Divisor': ('IntReg', 'uqw', 'INTREG_IMPLICIT(4)', 'IsInteger', 11), 112 'Rax': ('IntReg', 'uqw', '(INTREG_RAX)', 'IsInteger', 12), 113 'Rbx': ('IntReg', 'uqw', '(INTREG_RBX)', 'IsInteger', 13), 114 'Rcx': ('IntReg', 'uqw', '(INTREG_RCX)', 'IsInteger', 14), 115 'Rdx': ('IntReg', 'uqw', '(INTREG_RDX)', 'IsInteger', 15), 116 'Rsp': ('IntReg', 'uqw', '(INTREG_RSP)', 'IsInteger', 16), 117 'Rbp': ('IntReg', 'uqw', '(INTREG_RBP)', 'IsInteger', 17), 118 'Rsi': ('IntReg', 'uqw', '(INTREG_RSI)', 'IsInteger', 18), 119 'Rdi': ('IntReg', 'uqw', '(INTREG_RDI)', 'IsInteger', 19), 120 'FpSrcReg1': ('FloatReg', 'df', 'src1', 'IsFloating', 20), 121 'FpSrcReg2': ('FloatReg', 'df', 'src2', 'IsFloating', 21), 122 'FpDestReg': ('FloatReg', 'df', 'dest', 'IsFloating', 22), 123 'FpData': ('FloatReg', 'df', 'data', 'IsFloating', 23), | 116 'SrcReg1': foldInt('src1', 'foldOBit', 1), 117 'SSrcReg1': intReg('src1', 1), 118 'SrcReg2': foldInt('src2', 'foldOBit', 2), 119 'SSrcReg2': intReg('src2', 1), 120 'Index': foldInt('index', 'foldABit', 3), 121 'Base': foldInt('base', 'foldABit', 4), 122 'DestReg': foldInt('dest', 'foldOBit', 5), 123 'SDestReg': intReg('dest', 5), 124 'Data': foldInt('data', 'foldOBit', 6), 125 'ProdLow': impIntReg(0, 7), 126 'ProdHi': impIntReg(1, 8), 127 'Quotient': impIntReg(2, 9), 128 'Remainder': impIntReg(3, 10), 129 'Divisor': impIntReg(4, 11), 130 'Rax': intReg('(INTREG_RAX)', 12), 131 'Rbx': intReg('(INTREG_RBX)', 13), 132 'Rcx': intReg('(INTREG_RCX)', 14), 133 'Rdx': intReg('(INTREG_RDX)', 15), 134 'Rsp': intReg('(INTREG_RSP)', 16), 135 'Rbp': intReg('(INTREG_RBP)', 17), 136 'Rsi': intReg('(INTREG_RSI)', 18), 137 'Rdi': intReg('(INTREG_RDI)', 19), 138 'FpSrcReg1': floatReg('src1', 20), 139 'FpSrcReg2': floatReg('src2', 21), 140 'FpDestReg': floatReg('dest', 22), 141 'FpData': floatReg('data', 23), |
| 124 'RIP': ('NPC', 'uqw', None, (None, None, 'IsControl'), 50), 125 'uIP': ('UPC', 'uqw', None, (None, None, 'IsControl'), 51), 126 'nuIP': ('NUPC', 'uqw', None, (None, None, 'IsControl'), 52), 127 # This holds the condition code portion of the flag register. The 128 # nccFlagBits version holds the rest. | 142 'RIP': ('NPC', 'uqw', None, (None, None, 'IsControl'), 50), 143 'uIP': ('UPC', 'uqw', None, (None, None, 'IsControl'), 51), 144 'nuIP': ('NUPC', 'uqw', None, (None, None, 'IsControl'), 52), 145 # This holds the condition code portion of the flag register. The 146 # nccFlagBits version holds the rest. |
| 129 'ccFlagBits': ('IntReg', 'uqw', 'INTREG_PSEUDO(0)', None, 60), | 147 'ccFlagBits': intReg('INTREG_PSEUDO(0)', 60), |
| 130 # These register should needs to be more protected so that later 131 # instructions don't map their indexes with an old value. | 148 # These register should needs to be more protected so that later 149 # instructions don't map their indexes with an old value. |
| 132 'nccFlagBits': ('ControlReg', 'uqw', 'MISCREG_RFLAGS', None, 61), 133 'TOP': ('ControlReg', 'ub', 'MISCREG_X87_TOP', None, 62), | 150 'nccFlagBits': controlReg('MISCREG_RFLAGS', 61), 151 'TOP': controlReg('MISCREG_X87_TOP', 62, ctype='ub'), |
| 134 # The segment base as used by memory instructions. | 152 # The segment base as used by memory instructions. |
| 135 'SegBase': ('ControlReg', 'uqw', 'MISCREG_SEG_EFF_BASE(segment)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 70), | 153 'SegBase': controlReg('MISCREG_SEG_EFF_BASE(segment)', 70), |
| 136 137 # Operands to get and set registers indexed by the operands of the 138 # original instruction. | 154 155 # Operands to get and set registers indexed by the operands of the 156 # original instruction. |
| 139 'ControlDest': ('ControlReg', 'uqw', 'MISCREG_CR(dest)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 100), 140 'ControlSrc1': ('ControlReg', 'uqw', 'MISCREG_CR(src1)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 101), 141 'DebugDest': ('ControlReg', 'uqw', 'MISCREG_DR(dest)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 102), 142 'DebugSrc1': ('ControlReg', 'uqw', 'MISCREG_DR(src1)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 103), 143 'SegBaseDest': ('ControlReg', 'uqw', 'MISCREG_SEG_BASE(dest)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 104), 144 'SegBaseSrc1': ('ControlReg', 'uqw', 'MISCREG_SEG_BASE(src1)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 105), 145 'SegLimitDest': ('ControlReg', 'uqw', 'MISCREG_SEG_LIMIT(dest)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 106), 146 'SegLimitSrc1': ('ControlReg', 'uqw', 'MISCREG_SEG_LIMIT(src1)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 107), 147 'SegSelDest': ('ControlReg', 'uqw', 'MISCREG_SEG_SEL(dest)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 108), 148 'SegSelSrc1': ('ControlReg', 'uqw', 'MISCREG_SEG_SEL(src1)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 109), 149 'SegAttrDest': ('ControlReg', 'uqw', 'MISCREG_SEG_ATTR(dest)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 110), 150 'SegAttrSrc1': ('ControlReg', 'uqw', 'MISCREG_SEG_ATTR(src1)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 111), | 157 'ControlDest': controlReg('MISCREG_CR(dest)', 100), 158 'ControlSrc1': controlReg('MISCREG_CR(src1)', 101), 159 'DebugDest': controlReg('MISCREG_DR(dest)', 102), 160 'DebugSrc1': controlReg('MISCREG_DR(src1)', 103), 161 'SegBaseDest': controlReg('MISCREG_SEG_BASE(dest)', 104), 162 'SegBaseSrc1': controlReg('MISCREG_SEG_BASE(src1)', 105), 163 'SegLimitDest': controlReg('MISCREG_SEG_LIMIT(dest)', 106), 164 'SegLimitSrc1': controlReg('MISCREG_SEG_LIMIT(src1)', 107), 165 'SegSelDest': controlReg('MISCREG_SEG_SEL(dest)', 108), 166 'SegSelSrc1': controlReg('MISCREG_SEG_SEL(src1)', 109), 167 'SegAttrDest': controlReg('MISCREG_SEG_ATTR(dest)', 110), 168 'SegAttrSrc1': controlReg('MISCREG_SEG_ATTR(src1)', 111), |
| 151 152 # Operands to access specific control registers directly. | 169 170 # Operands to access specific control registers directly. |
| 153 'EferOp': ('ControlReg', 'uqw', 'MISCREG_EFER', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 200), 154 'CR4Op': ('ControlReg', 'uqw', 'MISCREG_CR4', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 201), 155 'DR7Op': ('ControlReg', 'uqw', 'MISCREG_DR7', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 202), 156 'LDTRBase': ('ControlReg', 'uqw', 'MISCREG_TSL_BASE', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 203), 157 'LDTRLimit': ('ControlReg', 'uqw', 'MISCREG_TSL_LIMIT', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 204), 158 'LDTRSel': ('ControlReg', 'uqw', 'MISCREG_TSL', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 205), 159 'GDTRBase': ('ControlReg', 'uqw', 'MISCREG_TSG_BASE', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 206), 160 'GDTRLimit': ('ControlReg', 'uqw', 'MISCREG_TSG_LIMIT', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 207), 161 'CSBase': ('ControlReg', 'udw', 'MISCREG_CS_EFF_BASE', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 208), 162 'CSAttr': ('ControlReg', 'udw', 'MISCREG_CS_ATTR', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 209), 163 'MiscRegDest': ('ControlReg', 'uqw', 'dest', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 210), 164 'MiscRegSrc1': ('ControlReg', 'uqw', 'src1', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 211), 165 'TscOp': ('ControlReg', 'uqw', 'MISCREG_TSC', (None, None, ['IsSerializeAfter', 'IsSerializing', 'IsNonSpeculative']), 212), 166 'M5Reg': ('ControlReg', 'uqw', 'MISCREG_M5_REG', (None, None, None), 213), 167 'Mem': ('Mem', 'uqw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 300) | 171 'EferOp': controlReg('MISCREG_EFER', 200), 172 'CR4Op': controlReg('MISCREG_CR4', 201), 173 'DR7Op': controlReg('MISCREG_DR7', 202), 174 'LDTRBase': controlReg('MISCREG_TSL_BASE', 203), 175 'LDTRLimit': controlReg('MISCREG_TSL_LIMIT', 204), 176 'LDTRSel': controlReg('MISCREG_TSL', 205), 177 'GDTRBase': controlReg('MISCREG_TSG_BASE', 206), 178 'GDTRLimit': controlReg('MISCREG_TSG_LIMIT', 207), 179 'CSBase': controlReg('MISCREG_CS_EFF_BASE', 208), 180 'CSAttr': controlReg('MISCREG_CS_ATTR', 209), 181 'MiscRegDest': controlReg('dest', 210), 182 'MiscRegSrc1': controlReg('src1', 211), 183 'TscOp': controlReg('MISCREG_TSC', 212), 184 'M5Reg': controlReg('MISCREG_M5_REG', 213), 185 'Mem': ('Mem', 'uqw', None, \ 186 ('IsMemRef', 'IsLoad', 'IsStore'), 300) |
| 168}}; | 187}}; |