operands.isa (5409:0343cd06df4f) operands.isa (5426:0bdcc60ccc45)
1// Copyright (c) 2007 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

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112 'rax': ('IntReg', 'uqw', '(INTREG_RAX)', 'IsInteger', 12),
113 'FpSrcReg1': ('FloatReg', 'df', 'src1', 'IsFloating', 20),
114 'FpSrcReg2': ('FloatReg', 'df', 'src2', 'IsFloating', 21),
115 'FpDestReg': ('FloatReg', 'df', 'dest', 'IsFloating', 22),
116 'FpData': ('FloatReg', 'df', 'data', 'IsFloating', 23),
117 'RIP': ('NPC', 'uqw', None, (None, None, 'IsControl'), 50),
118 'uIP': ('UPC', 'uqw', None, (None, None, 'IsControl'), 51),
119 'nuIP': ('NUPC', 'uqw', None, (None, None, 'IsControl'), 52),
1// Copyright (c) 2007 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

--- 103 unchanged lines hidden (view full) ---

112 'rax': ('IntReg', 'uqw', '(INTREG_RAX)', 'IsInteger', 12),
113 'FpSrcReg1': ('FloatReg', 'df', 'src1', 'IsFloating', 20),
114 'FpSrcReg2': ('FloatReg', 'df', 'src2', 'IsFloating', 21),
115 'FpDestReg': ('FloatReg', 'df', 'dest', 'IsFloating', 22),
116 'FpData': ('FloatReg', 'df', 'data', 'IsFloating', 23),
117 'RIP': ('NPC', 'uqw', None, (None, None, 'IsControl'), 50),
118 'uIP': ('UPC', 'uqw', None, (None, None, 'IsControl'), 51),
119 'nuIP': ('NUPC', 'uqw', None, (None, None, 'IsControl'), 52),
120 # This holds the condition code portion of the flag register. The
121 # nccFlagBits version holds the rest.
120 'ccFlagBits': ('IntReg', 'uqw', 'INTREG_PSEUDO(0)', None, 60),
122 'ccFlagBits': ('IntReg', 'uqw', 'INTREG_PSEUDO(0)', None, 60),
121 # The TOP register should needs to be more protected so that later
123 # These register should needs to be more protected so that later
122 # instructions don't map their indexes with an old value.
124 # instructions don't map their indexes with an old value.
123 'TOP': ('ControlReg', 'ub', 'MISCREG_X87_TOP', None, 61),
125 'nccFlagBits': ('ControlReg', 'uqw', 'MISCREG_RFLAGS', None, 61),
126 'TOP': ('ControlReg', 'ub', 'MISCREG_X87_TOP', None, 62),
124 # The segment base as used by memory instructions.
125 'SegBase': ('ControlReg', 'uqw', 'MISCREG_SEG_EFF_BASE(segment)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 70),
126
127 # Operands to get and set registers indexed by the operands of the
128 # original instruction.
129 'ControlDest': ('ControlReg', 'uqw', 'MISCREG_CR(dest)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 100),
130 'ControlSrc1': ('ControlReg', 'uqw', 'MISCREG_CR(src1)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 101),
131 'SegBaseDest': ('ControlReg', 'uqw', 'MISCREG_SEG_BASE(dest)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 102),

--- 20 unchanged lines hidden --- 		127 # The segment base as used by memory instructions.
128 'SegBase': ('ControlReg', 'uqw', 'MISCREG_SEG_EFF_BASE(segment)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 70),
129
130 # Operands to get and set registers indexed by the operands of the
131 # original instruction.
132 'ControlDest': ('ControlReg', 'uqw', 'MISCREG_CR(dest)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 100),
133 'ControlSrc1': ('ControlReg', 'uqw', 'MISCREG_CR(src1)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 101),
134 'SegBaseDest': ('ControlReg', 'uqw', 'MISCREG_SEG_BASE(dest)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 102),

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