Cross Reference: /gem5/src/arch/x86/isa/operands.isa

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operands.isa (5083:49559a8060e8)	operands.isa (5241:a6602acdd046)
1// Copyright (c) 2007 The Regents of The University of Michigan 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: redistributions of source code must retain the above copyright 7// notice, this list of conditions and the following disclaimer; 8// redistributions in binary form must reproduce the above copyright --- 108 unchanged lines hidden (view full) --- 117 'RIP': ('NPC', 'uqw', None, (None, None, 'IsControl'), 50), 118 'uIP': ('UPC', 'uqw', None, (None, None, 'IsControl'), 51), 119 'nuIP': ('NUPC', 'uqw', None, (None, None, 'IsControl'), 52), 120 'ccFlagBits': ('IntReg', 'uqw', 'INTREG_PSEUDO(0)', None, 60), 121 # The TOP register should needs to be more protected so that later 122 # instructions don't map their indexes with an old value. 123 'TOP': ('ControlReg', 'ub', 'MISCREG_X87_TOP', None, 61), 124 'SegBase': ('ControlReg', 'uqw', 'MISCREG_SEG_BASE(segment)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 70),	1// Copyright (c) 2007 The Regents of The University of Michigan 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: redistributions of source code must retain the above copyright 7// notice, this list of conditions and the following disclaimer; 8// redistributions in binary form must reproduce the above copyright --- 108 unchanged lines hidden (view full) --- 117 'RIP': ('NPC', 'uqw', None, (None, None, 'IsControl'), 50), 118 'uIP': ('UPC', 'uqw', None, (None, None, 'IsControl'), 51), 119 'nuIP': ('NUPC', 'uqw', None, (None, None, 'IsControl'), 52), 120 'ccFlagBits': ('IntReg', 'uqw', 'INTREG_PSEUDO(0)', None, 60), 121 # The TOP register should needs to be more protected so that later 122 # instructions don't map their indexes with an old value. 123 'TOP': ('ControlReg', 'ub', 'MISCREG_X87_TOP', None, 61), 124 'SegBase': ('ControlReg', 'uqw', 'MISCREG_SEG_BASE(segment)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 70),
	125 'ControlDest': ('ControlReg', 'uqw', 'MISCREG_CR(dest)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 71), 126 'ControlSrc1': ('ControlReg', 'uqw', 'MISCREG_CR(src1)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 72), 127 'EferOp': ('ControlReg', 'uqw', 'MISCREG_EFER', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 73), 128 'CR4Op': ('ControlReg', 'uqw', 'MISCREG_CR4', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 74),
125 'Mem': ('Mem', 'uqw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100) 126}};	129 'Mem': ('Mem', 'uqw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100) 130}};