operands.isa (5063:8eb72b1bd3c6) operands.isa (5075:4ae876c5037d)
1// Copyright (c) 2007 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

--- 91 unchanged lines hidden (view full) ---

100 'Index': ('IntReg', 'uqw', 'INTREG_FOLDED(index, foldABit)', 'IsInteger', 3),
101 'Base': ('IntReg', 'uqw', 'INTREG_FOLDED(base, foldABit)', 'IsInteger', 4),
102 'DestReg': ('IntReg', 'uqw', 'INTREG_FOLDED(dest, foldOBit)', 'IsInteger', 5),
103 'Data': ('IntReg', 'uqw', 'INTREG_FOLDED(data, foldOBit)', 'IsInteger', 6),
104 'ProdLow': ('IntReg', 'uqw', 'INTREG_IMPLICIT(0)', 'IsInteger', 7),
105 'ProdHi': ('IntReg', 'uqw', 'INTREG_IMPLICIT(1)', 'IsInteger', 8),
106 'Quotient': ('IntReg', 'uqw', 'INTREG_IMPLICIT(2)', 'IsInteger', 9),
107 'Remainder': ('IntReg', 'uqw', 'INTREG_IMPLICIT(3)', 'IsInteger', 10),
1// Copyright (c) 2007 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

--- 91 unchanged lines hidden (view full) ---

100 'Index': ('IntReg', 'uqw', 'INTREG_FOLDED(index, foldABit)', 'IsInteger', 3),
101 'Base': ('IntReg', 'uqw', 'INTREG_FOLDED(base, foldABit)', 'IsInteger', 4),
102 'DestReg': ('IntReg', 'uqw', 'INTREG_FOLDED(dest, foldOBit)', 'IsInteger', 5),
103 'Data': ('IntReg', 'uqw', 'INTREG_FOLDED(data, foldOBit)', 'IsInteger', 6),
104 'ProdLow': ('IntReg', 'uqw', 'INTREG_IMPLICIT(0)', 'IsInteger', 7),
105 'ProdHi': ('IntReg', 'uqw', 'INTREG_IMPLICIT(1)', 'IsInteger', 8),
106 'Quotient': ('IntReg', 'uqw', 'INTREG_IMPLICIT(2)', 'IsInteger', 9),
107 'Remainder': ('IntReg', 'uqw', 'INTREG_IMPLICIT(3)', 'IsInteger', 10),
108 'rax': ('IntReg', 'uqw', '(INTREG_RAX)', 'IsInteger', 11),
108 'Divisor': ('IntReg', 'uqw', 'INTREG_IMPLICIT(4)', 'IsInteger', 11),
109 'rax': ('IntReg', 'uqw', '(INTREG_RAX)', 'IsInteger', 12),
109 'FpSrcReg1': ('FloatReg', 'df', 'src1', 'IsFloating', 20),
110 'FpSrcReg2': ('FloatReg', 'df', 'src2', 'IsFloating', 21),
111 'FpDestReg': ('FloatReg', 'df', 'dest', 'IsFloating', 22),
112 'FpData': ('FloatReg', 'df', 'data', 'IsFloating', 23),
113 'RIP': ('NPC', 'uqw', None, (None, None, 'IsControl'), 50),
114 'uIP': ('UPC', 'uqw', None, (None, None, 'IsControl'), 51),
115 'nuIP': ('NUPC', 'uqw', None, (None, None, 'IsControl'), 52),
116 'ccFlagBits': ('IntReg', 'uqw', 'INTREG_PSEUDO(0)', None, 60),
117 'SegBase': ('ControlReg', 'uqw', 'MISCREG_SEG_BASE(segment)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 70),
118 'Mem': ('Mem', 'uqw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100)
119}};
110 'FpSrcReg1': ('FloatReg', 'df', 'src1', 'IsFloating', 20),
111 'FpSrcReg2': ('FloatReg', 'df', 'src2', 'IsFloating', 21),
112 'FpDestReg': ('FloatReg', 'df', 'dest', 'IsFloating', 22),
113 'FpData': ('FloatReg', 'df', 'data', 'IsFloating', 23),
114 'RIP': ('NPC', 'uqw', None, (None, None, 'IsControl'), 50),
115 'uIP': ('UPC', 'uqw', None, (None, None, 'IsControl'), 51),
116 'nuIP': ('NUPC', 'uqw', None, (None, None, 'IsControl'), 52),
117 'ccFlagBits': ('IntReg', 'uqw', 'INTREG_PSEUDO(0)', None, 60),
118 'SegBase': ('ControlReg', 'uqw', 'MISCREG_SEG_BASE(segment)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 70),
119 'Mem': ('Mem', 'uqw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100)
120}};