operands.isa (5026:46dd8d55f6c9) operands.isa (5063:8eb72b1bd3c6)
1// Copyright (c) 2007 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

--- 81 unchanged lines hidden (view full) ---

90 'udw' : ('unsigned int', 32),
91 'sqw' : ('signed int', 64),
92 'uqw' : ('unsigned int', 64),
93 'sf' : ('float', 32),
94 'df' : ('float', 64),
95}};
96
97def operands {{
1// Copyright (c) 2007 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

--- 81 unchanged lines hidden (view full) ---

90 'udw' : ('unsigned int', 32),
91 'sqw' : ('signed int', 64),
92 'uqw' : ('unsigned int', 64),
93 'sf' : ('float', 32),
94 'df' : ('float', 64),
95}};
96
97def operands {{
98 'SrcReg1': ('IntReg', 'uqw', '(((src1 & 0x1C) == 4 ? foldOBit : 0) | src1)', 'IsInteger', 1),
99 'SrcReg2': ('IntReg', 'uqw', '(((src2 & 0x1C) == 4 ? foldOBit : 0) | src2)', 'IsInteger', 2),
100 'Index': ('IntReg', 'uqw', '(((index & 0x1C) == 4 ? foldABit : 0) | index)', 'IsInteger', 3),
101 'Base': ('IntReg', 'uqw', '(((base & 0x1C) == 4 ? foldABit : 0) | base)', 'IsInteger', 4),
102 'DestReg': ('IntReg', 'uqw', '(((dest & 0x1C) == 4 ? foldOBit : 0) | dest)', 'IsInteger', 5),
103 'Data': ('IntReg', 'uqw', '(((data & 0x1C) == 4 ? foldOBit : 0) | data)', 'IsInteger', 6),
104 'rax': ('IntReg', 'uqw', '(INTREG_RAX)', 'IsInteger', 7),
98 'SrcReg1': ('IntReg', 'uqw', 'INTREG_FOLDED(src1, foldOBit)', 'IsInteger', 1),
99 'SrcReg2': ('IntReg', 'uqw', 'INTREG_FOLDED(src2, foldOBit)', 'IsInteger', 2),
100 'Index': ('IntReg', 'uqw', 'INTREG_FOLDED(index, foldABit)', 'IsInteger', 3),
101 'Base': ('IntReg', 'uqw', 'INTREG_FOLDED(base, foldABit)', 'IsInteger', 4),
102 'DestReg': ('IntReg', 'uqw', 'INTREG_FOLDED(dest, foldOBit)', 'IsInteger', 5),
103 'Data': ('IntReg', 'uqw', 'INTREG_FOLDED(data, foldOBit)', 'IsInteger', 6),
104 'ProdLow': ('IntReg', 'uqw', 'INTREG_IMPLICIT(0)', 'IsInteger', 7),
105 'ProdHi': ('IntReg', 'uqw', 'INTREG_IMPLICIT(1)', 'IsInteger', 8),
106 'Quotient': ('IntReg', 'uqw', 'INTREG_IMPLICIT(2)', 'IsInteger', 9),
107 'Remainder': ('IntReg', 'uqw', 'INTREG_IMPLICIT(3)', 'IsInteger', 10),
108 'rax': ('IntReg', 'uqw', '(INTREG_RAX)', 'IsInteger', 11),
105 'FpSrcReg1': ('FloatReg', 'df', 'src1', 'IsFloating', 20),
106 'FpSrcReg2': ('FloatReg', 'df', 'src2', 'IsFloating', 21),
107 'FpDestReg': ('FloatReg', 'df', 'dest', 'IsFloating', 22),
108 'FpData': ('FloatReg', 'df', 'data', 'IsFloating', 23),
109 'RIP': ('NPC', 'uqw', None, (None, None, 'IsControl'), 50),
110 'uIP': ('UPC', 'uqw', None, (None, None, 'IsControl'), 51),
111 'nuIP': ('NUPC', 'uqw', None, (None, None, 'IsControl'), 52),
109 'FpSrcReg1': ('FloatReg', 'df', 'src1', 'IsFloating', 20),
110 'FpSrcReg2': ('FloatReg', 'df', 'src2', 'IsFloating', 21),
111 'FpDestReg': ('FloatReg', 'df', 'dest', 'IsFloating', 22),
112 'FpData': ('FloatReg', 'df', 'data', 'IsFloating', 23),
113 'RIP': ('NPC', 'uqw', None, (None, None, 'IsControl'), 50),
114 'uIP': ('UPC', 'uqw', None, (None, None, 'IsControl'), 51),
115 'nuIP': ('NUPC', 'uqw', None, (None, None, 'IsControl'), 52),
112 'ccFlagBits': ('IntReg', 'uqw', 'NUM_INTREGS + NumMicroIntRegs', None, 60),
116 'ccFlagBits': ('IntReg', 'uqw', 'INTREG_PSEUDO(0)', None, 60),
113 'SegBase': ('ControlReg', 'uqw', 'MISCREG_SEG_BASE(segment)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 70),
114 'Mem': ('Mem', 'uqw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100)
115}};
117 'SegBase': ('ControlReg', 'uqw', 'MISCREG_SEG_BASE(segment)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 70),
118 'Mem': ('Mem', 'uqw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100)
119}};