operands.isa (5025:5c264911b7a9) | operands.isa (5026:46dd8d55f6c9) |
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1// Copyright (c) 2007 The Regents of The University of Michigan 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: redistributions of source code must retain the above copyright 7// notice, this list of conditions and the following disclaimer; 8// redistributions in binary form must reproduce the above copyright --- 78 unchanged lines hidden (view full) --- 87 'sw' : ('signed int', 16), 88 'uw' : ('unsigned int', 16), 89 'sdw' : ('signed int', 32), 90 'udw' : ('unsigned int', 32), 91 'sqw' : ('signed int', 64), 92 'uqw' : ('unsigned int', 64), 93 'sf' : ('float', 32), 94 'df' : ('float', 64), | 1// Copyright (c) 2007 The Regents of The University of Michigan 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: redistributions of source code must retain the above copyright 7// notice, this list of conditions and the following disclaimer; 8// redistributions in binary form must reproduce the above copyright --- 78 unchanged lines hidden (view full) --- 87 'sw' : ('signed int', 16), 88 'uw' : ('unsigned int', 16), 89 'sdw' : ('signed int', 32), 90 'udw' : ('unsigned int', 32), 91 'sqw' : ('signed int', 64), 92 'uqw' : ('unsigned int', 64), 93 'sf' : ('float', 32), 94 'df' : ('float', 64), |
95 'qf' : ('float', 128) | |
96}}; 97 98def operands {{ 99 'SrcReg1': ('IntReg', 'uqw', '(((src1 & 0x1C) == 4 ? foldOBit : 0) | src1)', 'IsInteger', 1), 100 'SrcReg2': ('IntReg', 'uqw', '(((src2 & 0x1C) == 4 ? foldOBit : 0) | src2)', 'IsInteger', 2), 101 'Index': ('IntReg', 'uqw', '(((index & 0x1C) == 4 ? foldABit : 0) | index)', 'IsInteger', 3), 102 'Base': ('IntReg', 'uqw', '(((base & 0x1C) == 4 ? foldABit : 0) | base)', 'IsInteger', 4), 103 'DestReg': ('IntReg', 'uqw', '(((dest & 0x1C) == 4 ? foldOBit : 0) | dest)', 'IsInteger', 5), 104 'Data': ('IntReg', 'uqw', '(((data & 0x1C) == 4 ? foldOBit : 0) | data)', 'IsInteger', 6), 105 'rax': ('IntReg', 'uqw', '(INTREG_RAX)', 'IsInteger', 7), | 95}}; 96 97def operands {{ 98 'SrcReg1': ('IntReg', 'uqw', '(((src1 & 0x1C) == 4 ? foldOBit : 0) | src1)', 'IsInteger', 1), 99 'SrcReg2': ('IntReg', 'uqw', '(((src2 & 0x1C) == 4 ? foldOBit : 0) | src2)', 'IsInteger', 2), 100 'Index': ('IntReg', 'uqw', '(((index & 0x1C) == 4 ? foldABit : 0) | index)', 'IsInteger', 3), 101 'Base': ('IntReg', 'uqw', '(((base & 0x1C) == 4 ? foldABit : 0) | base)', 'IsInteger', 4), 102 'DestReg': ('IntReg', 'uqw', '(((dest & 0x1C) == 4 ? foldOBit : 0) | dest)', 'IsInteger', 5), 103 'Data': ('IntReg', 'uqw', '(((data & 0x1C) == 4 ? foldOBit : 0) | data)', 'IsInteger', 6), 104 'rax': ('IntReg', 'uqw', '(INTREG_RAX)', 'IsInteger', 7), |
106 'RIP': ('NPC', 'uqw', None, (None, None, 'IsControl'), 10), 107 'uIP': ('UPC', 'uqw', None, (None, None, 'IsControl'), 11), 108 'nuIP': ('NUPC', 'uqw', None, (None, None, 'IsControl'), 12), 109 'ccFlagBits': ('IntReg', 'uqw', 'NUM_INTREGS + NumMicroIntRegs', None, 20), 110 'SegBase': ('ControlReg', 'uqw', 'MISCREG_SEG_BASE(segment)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 50), | 105 'FpSrcReg1': ('FloatReg', 'df', 'src1', 'IsFloating', 20), 106 'FpSrcReg2': ('FloatReg', 'df', 'src2', 'IsFloating', 21), 107 'FpDestReg': ('FloatReg', 'df', 'dest', 'IsFloating', 22), 108 'FpData': ('FloatReg', 'df', 'data', 'IsFloating', 23), 109 'RIP': ('NPC', 'uqw', None, (None, None, 'IsControl'), 50), 110 'uIP': ('UPC', 'uqw', None, (None, None, 'IsControl'), 51), 111 'nuIP': ('NUPC', 'uqw', None, (None, None, 'IsControl'), 52), 112 'ccFlagBits': ('IntReg', 'uqw', 'NUM_INTREGS + NumMicroIntRegs', None, 60), 113 'SegBase': ('ControlReg', 'uqw', 'MISCREG_SEG_BASE(segment)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 70), |
111 'Mem': ('Mem', 'uqw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100) 112}}; | 114 'Mem': ('Mem', 'uqw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100) 115}}; |